From patchwork Thu Aug 1 03:44:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Stultz X-Patchwork-Id: 170280 Delivered-To: patches@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp4835969ile; Wed, 31 Jul 2019 20:44:48 -0700 (PDT) X-Received: by 2002:a17:90a:20c6:: with SMTP id f64mr6241618pjg.57.1564631087971; Wed, 31 Jul 2019 20:44:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564631087; cv=none; d=google.com; s=arc-20160816; b=nddLdnIvQV08B5brAQQdj5xDdF9Pp7ImYJPmBORsuQMDt4bi2TKADVcc1urWSD70AH xcir9De6yXXVC/rr2VXxNW19T5AuCuS8FgYbjgCLPMMqUJajBm7xl7hEpKyArsuEMBKa s8WUzVmB+ANv2yjMV4+1tr+J6GDXTMlT925F+Y/bGVxbF4Bvn9q/IXSANHtAgtqNQF50 dlfYhJuvCYKyjZWL69YxJZfUa1EUd2hM7qHOaAMvJIdrD6zuCv3Tf5x2NMT1rIzB0oEA e/+mlE8h8rywsc2vqNQw3yy0NXjV6znyI9oF55T7fe87/RI6CGktyXM1QyMl3OTjJKJy Ep7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=/QjSI1b8alIth1E7HJtMuZLsPsx44ZXhw7/4SnNJJUk=; b=YWOjtk3XfuZnt7q+6I3Rb0n6SWX8mjCPGL7YhTT4rY6r9rwfXthUB6izLHMqHi2bPA 5EleMwbvxkKrS7ejcoyf/qaciTdKyWZVOAwd9gtjf1Rt6eMEO3vmBFpTmJXjrPqd1DsK OIkULWnmsFUNWSb8tJT+6a8IdM5SVFtlyoaXoh1SRVyMkMKgxzgng9fAvd6jQ6uS6xhc kBIk81bRbFi120yfiuxQqT21xDyDi06Mjq4H+z9MEg6GFGVdHJqY0IFQ2nCu51UfaLkU iVPgm7XRtWYnCPZyjvcJhEOs/IAI/Zvcdjw47I71PMQjzpkVVFP9ajFegzV//VhBGswM bxrg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Z9EGW8Ep; spf=pass (google.com: domain of john.stultz@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=john.stultz@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id n13sor4477849pjc.24.2019.07.31.20.44.47 for (Google Transport Security); Wed, 31 Jul 2019 20:44:47 -0700 (PDT) Received-SPF: pass (google.com: domain of john.stultz@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Z9EGW8Ep; spf=pass (google.com: domain of john.stultz@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=john.stultz@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/QjSI1b8alIth1E7HJtMuZLsPsx44ZXhw7/4SnNJJUk=; b=Z9EGW8Ep6iZzB6WcT1yvuoOLW03dKeUayVCnQHc9y9QdNBavUwlMez4gbLQk/LbsF7 LCH59XX31xuyCrwxPuWmkqkwW4R+5tt+sQ+4V34L1ozXCXAfD0YQPEpvhU0WXzYBxxYH Snq3t4ydBqLPZ5R9Jzg0UofhXZmn7TAMwPahrPHrR6t1S9aYZGG782YeJDh/LKHSVfBh 2KtqomAW9xZ0RasEXxXt9JoW4KsPD4khMr3lHmCzE+wu7Kodwgs1sba341KEQ8gb34XE xv+JAZQ46ubfd6OPx0vXFPAJ68eroDUg0X1hN8llrzdOkQ5FhfXZgjoi/RQ1unW7c8T4 ec6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/QjSI1b8alIth1E7HJtMuZLsPsx44ZXhw7/4SnNJJUk=; b=Pn2LtlFvRRRtb3um1qohbrMXqNRKruya1bO33RO7I+FPOSV6kfJeNn8AHCkVcOFE0H 32Hs5ltBIgnYS8e9O9ocp2jor62WJRb4+cMIkZQkOqV8IwZ5kMGazZjahlsgHjVTYzUc o0ICQeFkdvxNVzYeegt6kxG7H/nV2GLYx00Zc6PRURQb3Jow27HvpH8DN5CC45I3W2NZ UPmchlCVuBjGjhR2k12biNU5uty336wHe38YnAA+U0GBcW2cSIdbfdAkULZx26u80S9S lu2cPZs97bGWcVBLdbqwy+zSmS1PJhieHevAwIoinjm6NQOWCivaaiwPCkQZSpLUzqKv oJJw== X-Gm-Message-State: APjAAAWHJNFDU/tOVWFg8w4XNNSLZYKIr0tWKE6wcgE6V+IJOwftqM6f EaIDYogQLooRmfCw2aB/yUvNxHnJ X-Google-Smtp-Source: APXvYqz5tjq2NsRmnAofXBfa6ee/WnT/EZxT80QAkU/SM9rc9yFnRqsKdy5zrDajaeuaEnnpa8mSsg== X-Received: by 2002:a17:90a:9bca:: with SMTP id b10mr6190126pjw.90.1564631087485; Wed, 31 Jul 2019 20:44:47 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([2601:1c2:680:1319:692:26ff:feda:3a81]) by smtp.gmail.com with ESMTPSA id h70sm64775674pgc.36.2019.07.31.20.44.45 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Wed, 31 Jul 2019 20:44:46 -0700 (PDT) From: John Stultz To: lkml Cc: Da Lv , Rongrong Zou , David Airlie , Daniel Vetter , dri-devel , Sam Ravnborg , Yidong Lin , John Stultz Subject: [PATCH v3 01/26] drm: kirin: Fix for hikey620 display offset problem Date: Thu, 1 Aug 2019 03:44:14 +0000 Message-Id: <20190801034439.98227-2-john.stultz@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190801034439.98227-1-john.stultz@linaro.org> References: <20190801034439.98227-1-john.stultz@linaro.org> From: Da Lv The original HiKey (620) board has had a long running issue where when using a 1080p montior, the display would occasionally blink and come come back with a horizontal offset (usually also shifting the colors, depending on the value of the offset%4). After lots of analysis by HiSi developers, they found the issue was due to when running at 1080p, it was possible to hit the device memory bandwidth limits, which could cause the DSI signal to get out of sync. Unfortunately the DSI logic doesn't have the ability to automatically recover from this situation, but we can get a an LDI underflow interrupt when it happens. To then correct the issue, when we get an LDI underflow irq, we we can simply suspend and resume the display, which resets the hardware. Thus, this patch enables the ldi underflow interrupt, and initializes a workqueue that is used to suspend/resume the display to recover. Then when the irq occurs we clear it and schedule the workqueue to reset display engine. Cc: Rongrong Zou Cc: David Airlie Cc: Daniel Vetter Cc: dri-devel Cc: Sam Ravnborg Reviewed-by: Sam Ravnborg Signed-off-by: Da Lv Signed-off-by: Yidong Lin [jstultz: Reworded the commit message, checkpatch cleanups] Signed-off-by: John Stultz --- v2: Minor cleanups v3: Rename workqueue entry for clarity (suggested by Sam) --- .../gpu/drm/hisilicon/kirin/kirin_ade_reg.h | 1 + .../gpu/drm/hisilicon/kirin/kirin_drm_ade.c | 22 +++++++++++++++++++ 2 files changed, 23 insertions(+) -- 2.17.1 diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h b/drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h index e2ac09894a6d..0da860200410 100644 --- a/drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h +++ b/drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h @@ -83,6 +83,7 @@ #define VSIZE_OFST 20 #define LDI_INT_EN 0x741C #define FRAME_END_INT_EN_OFST 1 +#define UNDERFLOW_INT_EN_OFST 2 #define LDI_CTRL 0x7420 #define BPP_OFST 3 #define DATA_GATE_EN BIT(2) diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c index ad7042ae2241..d69b5d458950 100644 --- a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c +++ b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c @@ -54,6 +54,7 @@ struct ade_hw_ctx { struct ade_crtc { struct drm_crtc base; struct ade_hw_ctx *ctx; + struct work_struct display_reset_wq; bool enable; u32 out_format; }; @@ -172,6 +173,7 @@ static void ade_init(struct ade_hw_ctx *ctx) */ ade_update_bits(base + ADE_CTRL, FRM_END_START_OFST, FRM_END_START_MASK, REG_EFFECTIVE_IN_ADEEN_FRMEND); + ade_update_bits(base + LDI_INT_EN, UNDERFLOW_INT_EN_OFST, MASK(1), 1); } static bool ade_crtc_mode_fixup(struct drm_crtc *crtc, @@ -341,6 +343,17 @@ static void ade_crtc_disable_vblank(struct drm_crtc *crtc) MASK(1), 0); } +static void drm_underflow_wq(struct work_struct *work) +{ + struct ade_crtc *acrtc = container_of(work, struct ade_crtc, + display_reset_wq); + struct drm_device *drm_dev = (&acrtc->base)->dev; + struct drm_atomic_state *state; + + state = drm_atomic_helper_suspend(drm_dev); + drm_atomic_helper_resume(drm_dev, state); +} + static irqreturn_t ade_irq_handler(int irq, void *data) { struct ade_crtc *acrtc = data; @@ -358,6 +371,12 @@ static irqreturn_t ade_irq_handler(int irq, void *data) MASK(1), 1); drm_crtc_handle_vblank(crtc); } + if (status & BIT(UNDERFLOW_INT_EN_OFST)) { + ade_update_bits(base + LDI_INT_CLR, UNDERFLOW_INT_EN_OFST, + MASK(1), 1); + DRM_ERROR("LDI underflow!"); + schedule_work(&acrtc->display_reset_wq); + } return IRQ_HANDLED; } @@ -1034,6 +1053,9 @@ static int ade_drm_init(struct platform_device *pdev) /* vblank irq init */ ret = devm_request_irq(dev->dev, ctx->irq, ade_irq_handler, IRQF_SHARED, dev->driver->name, acrtc); + + INIT_WORK(&acrtc->display_reset_wq, drm_underflow_wq); + if (ret) return ret;