From patchwork Tue Aug 20 23:06:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Stultz X-Patchwork-Id: 171860 Delivered-To: patches@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp179837ily; Tue, 20 Aug 2019 16:06:32 -0700 (PDT) X-Received: by 2002:a17:902:aa08:: with SMTP id be8mr31272272plb.144.1566342392178; Tue, 20 Aug 2019 16:06:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566342392; cv=none; d=google.com; s=arc-20160816; b=WMLM9Ag4RbYxbFAQE5kKjIrqf1Rq3P8veAiiy+EfiOXpUyRaotz6dED1y8aF5n2397 sdFbwjQHvm3rfWucL+wl1XdTpA/MsM4Ji/HVPb1yspG9sWqki8lwdiJVUk5ts6nRLPAB eDV9H15DAwG+hrW9R9UUwr/oD0lM6hyU4D+xBaSk3xZ7mDKLW7FYeV7wap778Po6mRfI r2hlfr5flMFrHeafYf6qdsxMIxbue7iqqFPl4ufUjL4r0qaPtxP3dAWF8Hc8r5QhnGAF 9FSUC9LkVB176PhQk1Uv9/m70sdwdot/ByclCPMbNWQDFxuavyXDT8we8qKOhbG1Pb4t 9hIg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=q1UYVKf1UgYkHQbbceABIVFSdc5VY9rhqkw1qWPFE+g=; b=b16dmmBztXjNnwcQm/KySRxGnhSwC0P7IMoobJP1NtqaQML2Q5YtHT0ajX98QHtKca u8fnTrIZWp6Tn3XtAMBXjALyjJK+FofIvpD8r3qWVU5cFG+2wWMkQfVA6ftcvPGJcGIf W8mVy5V7ia7hvME2KD/FegosVqeXUyi3k2+CScX5M++ksYDaHY3EUYxkVo1BPZxsxHJ/ P2cpQM9Utg4tftYUeLIBUlOyQ0/pQ9rpeCnpvpCjj380S3ItJxUg/ZdPH3CZJ55zP8y6 ACTOL6IZQ/Pst/YmV/yFD2ivPSHs7S7CwmDlEQTcOIKemIPcmnongw0hCllBX5bChvXn kxyQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RJ0xYmr+; spf=pass (google.com: domain of john.stultz@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=john.stultz@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id cb8sor6815164plb.4.2019.08.20.16.06.32 for (Google Transport Security); Tue, 20 Aug 2019 16:06:32 -0700 (PDT) Received-SPF: pass (google.com: domain of john.stultz@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RJ0xYmr+; spf=pass (google.com: domain of john.stultz@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=john.stultz@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=q1UYVKf1UgYkHQbbceABIVFSdc5VY9rhqkw1qWPFE+g=; b=RJ0xYmr+le6e0PlBTw1zfPraNay7cF0OyB+nOHMyagiieh4nJXKPXaQvS3aMZyvjTO Dmk6dfoWGfWJkSpVdRwNjNYFsKpUZv/XyhMjb5cR/jkPe1xfhvU5GQb/mYk98XWCrRC/ hPu6nj+BMp2Yp5fK72qMJzbYwo/+3+MvQ0/3QmbQb7UvOVNhCwuys+knWVVbUj/WGzrq 5t+Z0pcOS3tIeJzDbdFTrjDoTkODIjDU1gC9ZudISnCQ7kbGGkZrDEswpYDtE30wx3tb Sd3hLENL8vNNiIh5S1hSRAhpRF/ZlPpW72Vs+AgHzTX5T6wwgAg08by4npeNAxrO3ZDu i6Sg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=q1UYVKf1UgYkHQbbceABIVFSdc5VY9rhqkw1qWPFE+g=; b=GXyNaIHnc8MXNBiYBc5pRFKd56ZZ/J5iVnIEMg/wWDeHsLhzJY6hVoP6o80UyOvPo/ RVbPrzb5wo91WX13GKBt4iTOOnZ+XjIUZUST5YceRdnYKgGbKBNWGT31uMB0avZPjtch 46NmroP8p0rsqJIFumnaF9X5nZoKPvGquJbcnfhdHhavO3fl+DC8/SbFlAkI8Ndpw05N d8EU+9PEja20IvQIatGtWeiOKEvHKPHW7z9ylswLH4yzUhUd7ngEOC5idSYpdxonJVIQ cWzln/fIz8Tz1qWlWSVVjJMKisv5jrPRAxD0ry/iqbqguY6XDaV3cn0gJEsSc1WG0gTI nCGw== X-Gm-Message-State: APjAAAV67YuvbRK/Fw9jIfW+eXMqSnfm5DGOTvhsynYTAjJ/dxF3fo66 KJXqta9RrCHa/ZiIzASEZMxRgJr+ X-Google-Smtp-Source: APXvYqw5D4BZDetSBcN2Jnla7obS49bgLF/nwN7GXXGmMfCHVZaEj82kGnEeoSYhj3aNYpuZGpkXRg== X-Received: by 2002:a17:902:9895:: with SMTP id s21mr16299078plp.255.1566342391778; Tue, 20 Aug 2019 16:06:31 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([2601:1c2:680:1319:692:26ff:feda:3a81]) by smtp.gmail.com with ESMTPSA id q4sm27564747pff.183.2019.08.20.16.06.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Aug 2019 16:06:31 -0700 (PDT) From: John Stultz To: lkml Cc: Da Lv , Rongrong Zou , Xinliang Liu , David Airlie , Daniel Vetter , dri-devel , Sam Ravnborg , Yidong Lin , John Stultz Subject: [PATCH v5 01/25] drm: kirin: Fix for hikey620 display offset problem Date: Tue, 20 Aug 2019 23:06:02 +0000 Message-Id: <20190820230626.23253-2-john.stultz@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190820230626.23253-1-john.stultz@linaro.org> References: <20190820230626.23253-1-john.stultz@linaro.org> From: Da Lv The original HiKey (620) board has had a long running issue where when using a 1080p montior, the display would occasionally blink and come come back with a horizontal offset (usually also shifting the colors, depending on the value of the offset%4). After lots of analysis by HiSi developers, they found the issue was due to when running at 1080p, it was possible to hit the device memory bandwidth limits, which could cause the DSI signal to get out of sync. Unfortunately the DSI logic doesn't have the ability to automatically recover from this situation, but we can get a an LDI underflow interrupt when it happens. To then correct the issue, when we get an LDI underflow irq, we we can simply suspend and resume the display, which resets the hardware. Thus, this patch enables the ldi underflow interrupt, and initializes a workqueue that is used to suspend/resume the display to recover. Then when the irq occurs we clear it and schedule the workqueue to reset display engine. Cc: Rongrong Zou Cc: Xinliang Liu Cc: David Airlie Cc: Daniel Vetter Cc: dri-devel Cc: Sam Ravnborg Acked-by: Xinliang Liu Reviewed-by: Sam Ravnborg Signed-off-by: Da Lv Signed-off-by: Yidong Lin [jstultz: Reworded the commit message, checkpatch cleanups] Signed-off-by: John Stultz --- v2: Minor cleanups v3: Rename workqueue entry for clarity (suggested by Sam) --- .../gpu/drm/hisilicon/kirin/kirin_ade_reg.h | 1 + .../gpu/drm/hisilicon/kirin/kirin_drm_ade.c | 22 +++++++++++++++++++ 2 files changed, 23 insertions(+) -- 2.17.1 diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h b/drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h index e2ac09894a6d..0da860200410 100644 --- a/drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h +++ b/drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h @@ -83,6 +83,7 @@ #define VSIZE_OFST 20 #define LDI_INT_EN 0x741C #define FRAME_END_INT_EN_OFST 1 +#define UNDERFLOW_INT_EN_OFST 2 #define LDI_CTRL 0x7420 #define BPP_OFST 3 #define DATA_GATE_EN BIT(2) diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c index 0df1afdf319d..d972342527b8 100644 --- a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c +++ b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c @@ -58,6 +58,7 @@ struct ade_hw_ctx { struct ade_crtc { struct drm_crtc base; struct ade_hw_ctx *ctx; + struct work_struct display_reset_wq; bool enable; u32 out_format; }; @@ -176,6 +177,7 @@ static void ade_init(struct ade_hw_ctx *ctx) */ ade_update_bits(base + ADE_CTRL, FRM_END_START_OFST, FRM_END_START_MASK, REG_EFFECTIVE_IN_ADEEN_FRMEND); + ade_update_bits(base + LDI_INT_EN, UNDERFLOW_INT_EN_OFST, MASK(1), 1); } static bool ade_crtc_mode_fixup(struct drm_crtc *crtc, @@ -345,6 +347,17 @@ static void ade_crtc_disable_vblank(struct drm_crtc *crtc) MASK(1), 0); } +static void drm_underflow_wq(struct work_struct *work) +{ + struct ade_crtc *acrtc = container_of(work, struct ade_crtc, + display_reset_wq); + struct drm_device *drm_dev = (&acrtc->base)->dev; + struct drm_atomic_state *state; + + state = drm_atomic_helper_suspend(drm_dev); + drm_atomic_helper_resume(drm_dev, state); +} + static irqreturn_t ade_irq_handler(int irq, void *data) { struct ade_crtc *acrtc = data; @@ -362,6 +375,12 @@ static irqreturn_t ade_irq_handler(int irq, void *data) MASK(1), 1); drm_crtc_handle_vblank(crtc); } + if (status & BIT(UNDERFLOW_INT_EN_OFST)) { + ade_update_bits(base + LDI_INT_CLR, UNDERFLOW_INT_EN_OFST, + MASK(1), 1); + DRM_ERROR("LDI underflow!"); + schedule_work(&acrtc->display_reset_wq); + } return IRQ_HANDLED; } @@ -1038,6 +1057,9 @@ static int ade_drm_init(struct platform_device *pdev) /* vblank irq init */ ret = devm_request_irq(dev->dev, ctx->irq, ade_irq_handler, IRQF_SHARED, dev->driver->name, acrtc); + + INIT_WORK(&acrtc->display_reset_wq, drm_underflow_wq); + if (ret) return ret;