| Message ID | 20190913192807.8423-4-daniel.baluta@nxp.com |
|---|---|
| State | New |
| Headers | show |
| Series | Several SAI fixes | expand |
Hello Daniel, On Fri, Sep 13, 2019 at 10:28:07PM +0300, Daniel Baluta wrote: > The SAI transmitter and receiver can be configured to operate with > synchronous bit clock and frame sync. > > When Tx is synchronous with receiver RCSR.RE should be set in playback > to enable the receiver which provides bit clock and frame sync. > > When Rx is synchronous with transmitter TCSR.TE should be set in record > to enable the transmitter which provides bit clock and frame sync. I don't quite get what this patch fixes....can you explain? > @@ -539,8 +539,8 @@ static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd, > sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0); > > /* > - * It is recommended that the transmitter is the last enabled > - * and the first disabled. This is copied from iMX6SX Reference Manual, IIRC...And I just took a look at iMX8DXP/QXP RM: it has the exact same statement in "16.16.3.3.1 Synchronous mode" section. > + * it is recommended that the asynchronous block to be the last enabled > + * and the first disabled So... why are we changing to this? Any update/explain? Thank you
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index 6598a1ae0a2d..a59300e37549 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -539,8 +539,8 @@ static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd, sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0); /* - * It is recommended that the transmitter is the last enabled - * and the first disabled. + * it is recommended that the asynchronous block to be the last enabled + * and the first disabled */ switch (cmd) { case SNDRV_PCM_TRIGGER_START: @@ -549,9 +549,11 @@ static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd, regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE); - regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs), - FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); - regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), + if (sai->synchronous[tx]) + regmap_update_bits(sai->regmap, FSL_SAI_xCSR(!tx, ofs), + FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); + + regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
The SAI transmitter and receiver can be configured to operate with synchronous bit clock and frame sync. When Tx is synchronous with receiver RCSR.RE should be set in playback to enable the receiver which provides bit clock and frame sync. When Rx is synchronous with transmitter TCSR.TE should be set in record to enable the transmitter which provides bit clock and frame sync. Cc: NXP Linux Team <linux-imx@nxp.com> Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> --- Changes since v1: * new patch sound/soc/fsl/fsl_sai.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) -- 2.17.1