From patchwork Thu Oct 3 15:51:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg KH X-Patchwork-Id: 175150 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp573565ill; Thu, 3 Oct 2019 09:43:15 -0700 (PDT) X-Google-Smtp-Source: APXvYqzvFtOwMxqZtVcVDCxvuh45H2+7xQ+n6MOFYRuLSFDdDbm6JeKXsrjLs29iBDuI8hV+8kes X-Received: by 2002:a50:aa96:: with SMTP id q22mr10485404edc.179.1570120995364; Thu, 03 Oct 2019 09:43:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570120995; cv=none; d=google.com; s=arc-20160816; b=S3tNutB6Zz7NPjSTvKhnhRzjpAgiF6uawNBH7H7YU5jzIVVz3tYueJsQivKzbflo+r 3fBz8jJN9rrOO6e1umfanwFXf2TsVC79SFX+KJnCt2f/ohYc2gj1zWORjU0GR8FopBEX K82xhbfxe9eiIG/ixSP5IZZ69fPuQEbaewcuJD/BdY5k9wf23QSVaSyxP1Bw/F28C2TB jsw7rpu2iPFpdJPS+jBX6wUMVJY9/RWLG541cJ+3sNhR72jjWIwxl48DC9+wYLVTknt1 4NjRR6FpLQpiwauXZn8XS06xMNPsFfs6OqCjkm4sB6c2ky9buUsZiHEqemr4GOpB1s6n XJtA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :user-agent:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=m6I3xn6EKZt4rJcOF1XQQjGGJ6TiIyyFBwU5bD4MkHg=; b=rOmWuqI1ByFbMCwSGVaPhlFITcxwfUvTMADEEYVFFMvehnfpnW8swVp+emnWNMUbAA i3UZTyApYIlDglBL/n6sYeTYnMrcZselI2OXyQfLzV79keSRpqgVVIUoc+zFrARGu8Hu C7/4d1ebvZpTzdhK2OtL77vPV3R/gS2jwkCt70Selw3IJuoseExR82dooTRMSzh8hL21 HVIEi5v/IHep2ddv68bQtiwdXddm7k0hNsZX0DvOZnvrapnA4nTfrxMjC761Xb8280yu JjIo2xIw7YY/9Rb2xXMsL3/TOe3aJPGCU3EQcI00T8FmxKMHDYRGh+0G3jwK/zlEqnuc kaVw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b="w21k/gQH"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f2si1582235ejq.395.2019.10.03.09.43.15; Thu, 03 Oct 2019 09:43:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b="w21k/gQH"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2405139AbfJCQnN (ORCPT + 27 others); Thu, 3 Oct 2019 12:43:13 -0400 Received: from mail.kernel.org ([198.145.29.99]:54490 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2405120AbfJCQnL (ORCPT ); Thu, 3 Oct 2019 12:43:11 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id C3EB920865; Thu, 3 Oct 2019 16:43:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1570120990; bh=R84mSIxpEX1AcPIuhZJU0uwLWQyn3K4b+Mpvg9kxH0k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=w21k/gQHvA1HwrHNFFaHb55uh9WCsPGo8ikcYBrCtc2F1lRqcEku4MkPMkgui5MHO N5QXXH/QhkgvOAH/t5FuuO9FshM+J4qMYsMFBNaeWhZBZS/JPecCaRMXtWd4Cu/bwM bbU3rk0lFGdRoiQlizrR2eMp/UDYlX5aES7k6LuQ= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Arnd Bergmann , Sasha Levin Subject: [PATCH 5.3 114/344] ARM: xscale: fix multi-cpu compilation Date: Thu, 3 Oct 2019 17:51:19 +0200 Message-Id: <20191003154551.446518473@linuxfoundation.org> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191003154540.062170222@linuxfoundation.org> References: <20191003154540.062170222@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Arnd Bergmann [ Upstream commit c7b68049943079550d4e6af0f10aa3aabd64131a ] Building a combined ARMv4+XScale kernel produces these and other build failures: /tmp/copypage-xscale-3aa821.s: Assembler messages: /tmp/copypage-xscale-3aa821.s:167: Error: selected processor does not support `pld [r7,#0]' in ARM mode /tmp/copypage-xscale-3aa821.s:168: Error: selected processor does not support `pld [r7,#32]' in ARM mode /tmp/copypage-xscale-3aa821.s:169: Error: selected processor does not support `pld [r1,#0]' in ARM mode /tmp/copypage-xscale-3aa821.s:170: Error: selected processor does not support `pld [r1,#32]' in ARM mode /tmp/copypage-xscale-3aa821.s:171: Error: selected processor does not support `pld [r7,#64]' in ARM mode /tmp/copypage-xscale-3aa821.s:176: Error: selected processor does not support `ldrd r4,r5,[r7],#8' in ARM mode /tmp/copypage-xscale-3aa821.s:180: Error: selected processor does not support `strd r4,r5,[r1],#8' in ARM mode Add an explict .arch armv5 in the inline assembly to allow the ARMv5 specific instructions regardless of the compiler -march= target. Link: https://lore.kernel.org/r/20190809163334.489360-5-arnd@arndb.de Signed-off-by: Arnd Bergmann Signed-off-by: Sasha Levin --- arch/arm/mm/copypage-xscale.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) -- 2.20.1 diff --git a/arch/arm/mm/copypage-xscale.c b/arch/arm/mm/copypage-xscale.c index 61d834157bc05..382e1c2855e85 100644 --- a/arch/arm/mm/copypage-xscale.c +++ b/arch/arm/mm/copypage-xscale.c @@ -42,6 +42,7 @@ static void mc_copy_user_page(void *from, void *to) * when prefetching destination as well. (NP) */ asm volatile ("\ +.arch xscale \n\ pld [%0, #0] \n\ pld [%0, #32] \n\ pld [%1, #0] \n\ @@ -106,8 +107,9 @@ void xscale_mc_clear_user_highpage(struct page *page, unsigned long vaddr) { void *ptr, *kaddr = kmap_atomic(page); - asm volatile( - "mov r1, %2 \n\ + asm volatile("\ +.arch xscale \n\ + mov r1, %2 \n\ mov r2, #0 \n\ mov r3, #0 \n\ 1: mov ip, %0 \n\