From patchwork Thu Oct 10 17:15:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suzuki K Poulose X-Patchwork-Id: 175793 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp2583225ocf; Thu, 10 Oct 2019 10:15:43 -0700 (PDT) X-Google-Smtp-Source: APXvYqzO9UvZhWGDmr2tGwbrsVaoU7U+fF1tgTJ/AoBItCACx1kvTdTBKVX1TLxu4OOu167cjHYE X-Received: by 2002:a17:906:e113:: with SMTP id gj19mr9309731ejb.203.1570727743288; Thu, 10 Oct 2019 10:15:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570727743; cv=none; d=google.com; s=arc-20160816; b=tetLvNmVE0WYT9/g6YRwnr9tOMl4+URUtqJGA7fHI6KcLjtuqp/GcA222ucfuc5+eV nyw5zgyvODZgffJK9A7Huvg0xxEUpJPubh/PhDughv/PguCteAGm0CPqbBBMSzBtkrr7 bOxwYKG79xKXmlyCNxtdnn1uFcE6mm07338pRHzyEl/Yz+cB2bvNkV5BIM+xDA2857B5 ta2HlXVTmx1r6EUA9pywRQX5tfV10Nai6ejceFoc5uPaldkCHpZ+cwtQtNECXuop/COM Pp8iUyKdv4/M8G1TlN5YuQcr0tBeJPet7qIjXpxeAOYbcm+lSCJb93Ww4XvX7VuzeIYi VJHQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=BJ4ecw+HrtACYhIwbizW6JZN3rIWyiazTOVeg3qBUcM=; b=AX+HKlodT1lfi82rQx3SFBN3/yjM0oYPZj8q3bvTWMN+tXPYj/MfXE9GEE4gD1cdWi UlVAtynwcMAaOv0LzxhsDl06ndLye7qaAi0K2tz3t/6oMkPDfJI3cEzV75x+tOgWq88h Rgu2wehyR6Y0GN1ofI6QJyYE9g3tmJcPkrNzIBjgwGtcQufHFJanYDGnFYC5t2JZRU5N nZDb4OxAyNa3uSeRoOeaC+l+3FrdFn+kNDRwkesAnzHf6Y8a9fJ/LKPTRUPKzc77aoVJ ty16tRMe0t4Vvtfl63gcBaSplZoNIzqfl7CTYIRznIhbvXpnlUQeuCY+52+vlB5mwRVQ D8Dg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z26si3421168ejw.359.2019.10.10.10.15.43; Thu, 10 Oct 2019 10:15:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726836AbfJJRPm (ORCPT + 21 others); Thu, 10 Oct 2019 13:15:42 -0400 Received: from foss.arm.com ([217.140.110.172]:36362 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726800AbfJJRPi (ORCPT ); Thu, 10 Oct 2019 13:15:38 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E279E1597; Thu, 10 Oct 2019 10:15:37 -0700 (PDT) Received: from dawn-kernel.cambridge.arm.com (unknown [10.1.197.116]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id E02AE3F71A; Thu, 10 Oct 2019 10:15:36 -0700 (PDT) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, will@kernel.org, mark.rutland@arm.com, catalin.marinas@arm.com, dave.martin@arm.com, Suzuki K Poulose Subject: [PATCH 3/3] arm64: cpufeature: Set the FP/SIMD compat HWCAP bits properly Date: Thu, 10 Oct 2019 18:15:17 +0100 Message-Id: <20191010171517.28782-4-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191010171517.28782-1-suzuki.poulose@arm.com> References: <20191010171517.28782-1-suzuki.poulose@arm.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org We set the compat_elf_hwcap bits unconditionally on arm64 to include the VFP and NEON support. However, the FP/SIMD unit is optional on Arm v8 and thus could be missing. We already handle this properly in the kernel, but still advertise to the COMPAT applications that the VFP is available. Fix this to make sure we only advertise when we really have them. Fixes: 82e0191a1aa11abf ("arm64: Support systems without FP/ASIMD") Cc: Will Deacon Cc: Catalin Marinas Cc: Mark Rutland Signed-off-by: Suzuki K Poulose --- Changes since v1: - Switch to using cpuid_feature_extract_unsigned_field() rather than hard coding field extraction. --- arch/arm64/kernel/cpufeature.c | 37 +++++++++++++++++++++++++++++++--- 1 file changed, 34 insertions(+), 3 deletions(-) -- 2.21.0 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 0f9eace6c64b..d260e3bdf07b 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -32,9 +32,7 @@ static unsigned long elf_hwcap __read_mostly; #define COMPAT_ELF_HWCAP_DEFAULT \ (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ - COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\ - COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\ - COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\ + COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ COMPAT_HWCAP_LPAE) unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; unsigned int compat_elf_hwcap2 __read_mostly; @@ -1589,6 +1587,12 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .match_list = list, \ } +#define HWCAP_CAP_MATCH(match, cap_type, cap) \ + { \ + __HWCAP_CAP(#cap, cap_type, cap) \ + .matches = match, \ + } + #ifdef CONFIG_ARM64_PTR_AUTH static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { { @@ -1662,8 +1666,35 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { {}, }; +#ifdef CONFIG_COMPAT +static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) +{ + /* + * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, + * in line with that of arm32 as in vfp_init(). We make sure that the + * check is future proof, by making sure value is non-zero. + */ + u32 mvfr1; + + WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); + if (scope == SCOPE_SYSTEM) + mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); + else + mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); + + return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) && + cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) && + cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT); +} +#endif + static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { #ifdef CONFIG_COMPAT + HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), + HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), + /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ + HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), + HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),