From patchwork Sun Oct 27 21:00:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Kroah-Hartman X-Patchwork-Id: 177832 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp2531174ill; Sun, 27 Oct 2019 14:08:51 -0700 (PDT) X-Google-Smtp-Source: APXvYqyATty8CU9Q154uA493gOYj7ZwUyyJsuRYnGJ9H0sTdbdjkdVKMZfl+H2jWmD6YTFK05CZh X-Received: by 2002:a50:984b:: with SMTP id h11mr16258652edb.248.1572210530921; Sun, 27 Oct 2019 14:08:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1572210530; cv=none; d=google.com; s=arc-20160816; b=o6oq2+IkRoaTaRNWtg7w4dF3262nahahAz8/xiOLYE08W6olAhB2aqByhyDDr/8MAc Z4//QGrns0DL/9a750h7wYorWnfEy6xaZea5J94bRClsDUb8zAWjCxPsamWfufT9mRU1 I57ozKPdfNGMjOiOkuEVE0OKJoS6pwkrLbxj9uK29ODDYqe12j67fIh2KOt5x2FJNdA7 u7LORMZVqz9X7yGAP7QE1ciHhJK+BG9nKQNpb0RX3JNboUkjWJqu7rb4anqca2JKopU3 bROTba0fv6oyPUeltRxjs9HhSXasJIyJ+HloPotzynhSZ52XBJ+jZlGkH02gaI+Phskp 5e4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :user-agent:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=VkUoKI+pFvbx4FACqKES/ygCLVbgJDx9j57Sjewlt24=; b=iZcmSzCDZ+AtbkzxbpxSyTad5gHnbe5MqcrO3PgowzCyGVlIkEG/UnuWfNsdHNYGIm Q4Z87hmrrKl0KdatyxJD1zoub9HX0QPAwdMriV7/EPBOgbinWD3gfK1MBDzBzFcrt5gi mkV2QGYmiHJl7MYtAslkFj/mHajxiSsiRdBlTybE61tHxuM/jD/YWSVAPcreQucquHWy tKbD0xwZBl6popYfm+mQsyo01ez1SjvtqN9UH/0iQ84+4J5O0963sRqwH0FaqchrWKGu UiSVZtG4rMf5igvAh198E/dZgVeDo5CLWEmMApcvvMzgYobBkjeeEZFOSuZ/1cHVu6Jg +rGw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=N0A3QkJ+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id k10si5663486ede.132.2019.10.27.14.08.50; Sun, 27 Oct 2019 14:08:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=N0A3QkJ+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729408AbfJ0VIs (ORCPT + 26 others); Sun, 27 Oct 2019 17:08:48 -0400 Received: from mail.kernel.org ([198.145.29.99]:55076 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729391AbfJ0VIq (ORCPT ); Sun, 27 Oct 2019 17:08:46 -0400 Received: from localhost (100.50.158.77.rev.sfr.net [77.158.50.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id B39252064A; Sun, 27 Oct 2019 21:08:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1572210525; bh=L6AtQUXHVMZgVJXZeNDPYuPpnqtOyjV6wz29rG6+lDU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=N0A3QkJ+jhk1zIn5fKljbDyfL/bgDkyHGgrtoolo+TLrMlrcxA7dFXd5kF+yRaowb UqGCuA+9iYYfDv2/tcz0z+7odb+pkgcnZJsFcQQbH1fAd/I+XwXg35mPTMVMofjIYs e9FjwGwYQRbPnE/nEZSTXA5g6GkNNz/n5bH3yfcc= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Greg Kroah-Hartman , Mark Rutland , Catalin Marinas , Dave Martin , James Morse , Will Deacon , Ard Biesheuvel Subject: [PATCH 4.14 043/119] arm64: move SCTLR_EL{1, 2} assertions to Date: Sun, 27 Oct 2019 22:00:20 +0100 Message-Id: <20191027203316.888729272@linuxfoundation.org> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191027203259.948006506@linuxfoundation.org> References: <20191027203259.948006506@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Mark Rutland [ Upstream commit 1c312e84c2d71da4101754fa6118f703f7473e01 ] Currently we assert that the SCTLR_EL{1,2}_{SET,CLEAR} bits are self-consistent with an assertion in config_sctlr_el1(). This is a bit unusual, since config_sctlr_el1() doesn't make use of these definitions, and is far away from the definitions themselves. We can use the CPP #error directive to have equivalent assertions in , next to the definitions of the set/clear bits, which is a bit clearer and simpler. At the same time, lets fill in the upper 32 bits for both registers in their respective RES0 definitions. This could be a little nicer with GENMASK_ULL(63, 32), but this currently lives in , which cannot safely be included from assembly, as can. Note the when the preprocessor evaluates an expression for an #if directive, all signed or unsigned values are treated as intmax_t or uintmax_t respectively. To avoid ambiguity, we define explicitly define the mask of all 64 bits. Signed-off-by: Mark Rutland Acked-by: Catalin Marinas Cc: Dave Martin Cc: James Morse Cc: Will Deacon Signed-off-by: Will Deacon Signed-off-by: Ard Biesheuvel Signed-off-by: Greg Kroah-Hartman --- arch/arm64/include/asm/sysreg.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -315,7 +315,8 @@ #define SCTLR_EL2_RES0 ((1 << 6) | (1 << 7) | (1 << 8) | (1 << 9) | \ (1 << 10) | (1 << 13) | (1 << 14) | (1 << 15) | \ (1 << 17) | (1 << 20) | (1 << 21) | (1 << 24) | \ - (1 << 26) | (1 << 27) | (1 << 30) | (1 << 31)) + (1 << 26) | (1 << 27) | (1 << 30) | (1 << 31) | \ + (0xffffffffUL << 32)) #ifdef CONFIG_CPU_BIG_ENDIAN #define ENDIAN_SET_EL2 SCTLR_ELx_EE @@ -331,9 +332,9 @@ SCTLR_ELx_SA | SCTLR_ELx_I | SCTLR_ELx_WXN | \ ENDIAN_CLEAR_EL2 | SCTLR_EL2_RES0) -/* Check all the bits are accounted for */ -#define SCTLR_EL2_BUILD_BUG_ON_MISSING_BITS BUILD_BUG_ON((SCTLR_EL2_SET ^ SCTLR_EL2_CLEAR) != ~0) - +#if (SCTLR_EL2_SET ^ SCTLR_EL2_CLEAR) != 0xffffffffffffffff +#error "Inconsistent SCTLR_EL2 set/clear bits" +#endif /* SCTLR_EL1 specific flags. */ #define SCTLR_EL1_UCI (1 << 26) @@ -352,7 +353,8 @@ #define SCTLR_EL1_RES1 ((1 << 11) | (1 << 20) | (1 << 22) | (1 << 28) | \ (1 << 29)) #define SCTLR_EL1_RES0 ((1 << 6) | (1 << 10) | (1 << 13) | (1 << 17) | \ - (1 << 21) | (1 << 27) | (1 << 30) | (1 << 31)) + (1 << 21) | (1 << 27) | (1 << 30) | (1 << 31) | \ + (0xffffffffUL << 32)) #ifdef CONFIG_CPU_BIG_ENDIAN #define ENDIAN_SET_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE) @@ -371,8 +373,9 @@ SCTLR_EL1_UMA | SCTLR_ELx_WXN | ENDIAN_CLEAR_EL1 |\ SCTLR_EL1_RES0) -/* Check all the bits are accounted for */ -#define SCTLR_EL1_BUILD_BUG_ON_MISSING_BITS BUILD_BUG_ON((SCTLR_EL1_SET ^ SCTLR_EL1_CLEAR) != ~0) +#if (SCTLR_EL1_SET ^ SCTLR_EL1_CLEAR) != 0xffffffffffffffff +#error "Inconsistent SCTLR_EL1 set/clear bits" +#endif /* id_aa64isar0 */ #define ID_AA64ISAR0_TS_SHIFT 52 @@ -585,9 +588,6 @@ static inline void config_sctlr_el1(u32 { u32 val; - SCTLR_EL2_BUILD_BUG_ON_MISSING_BITS; - SCTLR_EL1_BUILD_BUG_ON_MISSING_BITS; - val = read_sysreg(sctlr_el1); val &= ~clear; val |= set;