From patchwork Thu Nov 14 14:59:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suzuki K Poulose X-Patchwork-Id: 179448 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp11170000ilf; Thu, 14 Nov 2019 07:00:04 -0800 (PST) X-Google-Smtp-Source: APXvYqzfWHekIQg6Dn/K7CtB+wuvNP0pXYdAZzXClCld2xQNSI/is7uJNVnRnBZ7ZAmRNwWIwYVj X-Received: by 2002:a50:c191:: with SMTP id m17mr1714646edf.259.1573743604098; Thu, 14 Nov 2019 07:00:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1573743604; cv=none; d=google.com; s=arc-20160816; b=NQWj+gxMdz7zkeTURHivveiR9yQcjj5Z9efOPH8fR2/5jJpigxoGBGwtQEFDT0V1Wy Mqr1isFINZ5osbd1sGbashtg9A9cTqQN0jmSaNJM6Us/bj76UGYla5vXRCGv2z3J1MJm ySrSgCyyZa5OrSjuYmZupo2UYGq/dTbUYVw/2jNjn0G5+x6SMnGW1CxiQZ/mt/7WIa0P VULXBK7IxsyPJ+rGMo43sZlrGbyqjRi/izIKJbStcgUSNtFV018zuND0P9mT1bkpPYE/ NSdCyFGxjuQ9kMyM9SeZ+zeux3hK0/ZWfBCbfSuEFm7netb+qJwfnzBNWP9g/rhL/1i3 sPmg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=sbaFBaoSi/IGg3KP39hiSZ2i4vS/njnwPXoIJaWCCTA=; b=VeJybQJjmCEXJ+94h8mBUTpBhcbXMpDGDcsGnaT6B9DKlInAKo2V7+dZXR+uPUrXhe BSSQFnpD0oyYHP5oqlnkubBghX5LS7LSkd7X4v5fPJ4n2Uaj96m3K6BGYQ8ldMdRdNzE 5CD9YL1zFpaAaBT/pzmT91vlbhRaARcv5KZgY7gFrVxjnUSIJ6pl9a8YKwQB0xsnCxBS Joj2KEpqOpK5uVVHdlfTTwAaLmWpiJ5Qdq9hISyR2dlWpRymb3PExHvMKG489jkSeGH3 Gm6mWfDXshpdrfp014Vm1m1SomSQL+rKER40JqAgU5/p10hg40vTapKxMsJ+S2T/Suyj viaA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i14si4010117edr.68.2019.11.14.07.00.03; Thu, 14 Nov 2019 07:00:04 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726605AbfKNPAC (ORCPT + 26 others); Thu, 14 Nov 2019 10:00:02 -0500 Received: from foss.arm.com ([217.140.110.172]:44614 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726251AbfKNO77 (ORCPT ); Thu, 14 Nov 2019 09:59:59 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2FC1F55D; Thu, 14 Nov 2019 06:59:59 -0800 (PST) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.1.197.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 0E4063F52E; Thu, 14 Nov 2019 06:59:57 -0800 (PST) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, james.morse@arm.com, will@kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, maz@kernel.org, suzuki.poulose@arm.com Subject: [PATCH 1/5] arm64: Add MIDR encoding for Arm Cortex-A77 Date: Thu, 14 Nov 2019 14:59:14 +0000 Message-Id: <20191114145918.235339-2-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191114145918.235339-1-suzuki.poulose@arm.com> References: <20191114145918.235339-1-suzuki.poulose@arm.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: James Morse Add Arm Cortex-A77's part-number so we can match against its MIDR_EL1. Signed-off-by: James Morse Signed-off-by: Suzuki K Poulose --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) -- 2.23.0 diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index aca07c2f6e6e..3c8c1580527d 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -71,6 +71,7 @@ #define ARM_CPU_PART_CORTEX_A55 0xD05 #define ARM_CPU_PART_CORTEX_A76 0xD0B #define ARM_CPU_PART_NEOVERSE_N1 0xD0C +#define ARM_CPU_PART_CORTEX_A77 0xD0D #define APM_CPU_PART_POTENZA 0x000 @@ -101,6 +102,7 @@ #define MIDR_CORTEX_A35 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A35) #define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55) #define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76) +#define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77) #define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)