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[209.85.220.65]) by mx.google.com with SMTPS id p4sor18732717pff.66.2020.03.03.08.32.36 for (Google Transport Security); Tue, 03 Mar 2020 08:32:36 -0800 (PST) Received-SPF: pass (google.com: domain of john.stultz@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="AK/rx03P"; spf=pass (google.com: domain of john.stultz@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=john.stultz@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=8obFbtbZXosEJKG//WZlSXOw7/1cIUl4XNv0HtqaUlo=; b=AK/rx03P8zzwEU/tsbGqZR+NHHpLtewT9FuZzrbN0AZosCh0QeP/h0ppzqStM5et5O 7VN0bsmkkA6zGG2JX5Alq2aE2bN9WcEQ2Vb+fwKqZPblwN+ef97ydhQEHPDiYBJIYsdo 2sBxzLSi7kzgvV9mGUp7OmUPeyFKzO7/ybmPjZqeEQPjOFggRtbxgk3Lk9YJLVSFTZgy fmqFxLWIFTkS2MdDToaDd1vyLjmnWg49v9Lrz7PJh+hqnVHJeRGsTj8OJKiGqtPawwqD AeebfheMeE8IBJJqyFJOkrNgVZxrH3ycK2uYcc619d52NTLp1TfQkyVxYULDJN9BBLHu roGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=8obFbtbZXosEJKG//WZlSXOw7/1cIUl4XNv0HtqaUlo=; b=T0bdGZsxnipDJ0oJhcf+NAFxPtywTJ+zm+9w3t5Dk2X9tXI4brB9KxVoJFWG9DKzlG JzuHKkkfUFYMO2eYf1L6cmqIyUQ5nBb52cgS21bXFMInU3pF43nVt75gbAON1b/61BKg LHbYeP/+JaC1XkB0J+okdKPxvdnBSRmnS1SpRqN6H+8YYLYQ/9ZLkRdjI2hpKbPsTdzc vaTVKKhOdtH0JyiafMDnria+zsOI4WOx6MYqxnTQLHhJJfqQfpZmF01WlJIxFFejQpY8 nNXftBpXE/52LKg9cn3g1beXi2pi6/92BYQbBKW8MYRxANvziX6Xp0Om1aVEdqs+3tew TCKw== X-Gm-Message-State: ANhLgQ0RBMUfBKKEkR8jqJ6rxndWOFVdRYkEv3iXaXaBCcQLQ8698ABW SrDQTl5HD/8CsNLnow4E7Pimyqq8qqdsCA== X-Google-Smtp-Source: ADFU+vv86EwZYvOoqv6IIpJ4gZzJ54FtER/PLX6g+gJjN3fjOzVkukpWM/hzrvaTm8KPy/v/uhVYIg== X-Received: by 2002:a62:cd0a:: with SMTP id o10mr4918578pfg.18.1583253155971; Tue, 03 Mar 2020 08:32:35 -0800 (PST) Return-Path: Received: from localhost.localdomain ([2601:1c2:680:1319:692:26ff:feda:3a81]) by smtp.gmail.com with ESMTPSA id z17sm13299439pfk.110.2020.03.03.08.32.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Mar 2020 08:32:35 -0800 (PST) From: John Stultz To: lkml Cc: John Stultz , Xinliang Liu , Rongrong Zou , Xinwei Kong , Chen Feng , Sam Ravnborg , David Airlie , Daniel Vetter , dri-devel Subject: [PATCH] drm: kirin: Revert "Fix for hikey620 display offset problem" Date: Tue, 3 Mar 2020 16:32:28 +0000 Message-Id: <20200303163228.52741-1-john.stultz@linaro.org> X-Mailer: git-send-email 2.17.1 This reverts commit ff57c6513820efe945b61863cf4a51b79f18b592. With the commit ff57c6513820 ("drm: kirin: Fix for hikey620 display offset problem") we added support for handling LDI overflows by resetting the hardware. However, its been observed that when we do hit the LDI overflow condition, the irq seems to be screaming, and we do nothing but stream: [drm:ade_irq_handler [kirin_drm]] *ERROR* LDI underflow! over and over to the screen I've tried a few appraoches to avoid this, but none has yet been successful and the cure here is worse then the original disease, so revert this for now. Cc: Xinliang Liu Cc: Rongrong Zou Cc: Xinwei Kong Cc: Chen Feng Cc: Sam Ravnborg Cc: David Airlie Cc: Daniel Vetter Cc: dri-devel Fixes: ff57c6513820 ("drm: kirin: Fix for hikey620 display offset problem") Signed-off-by: John Stultz --- .../gpu/drm/hisilicon/kirin/kirin_ade_reg.h | 1 - .../gpu/drm/hisilicon/kirin/kirin_drm_ade.c | 20 ------------------- 2 files changed, 21 deletions(-) -- 2.17.1 diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h b/drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h index 0da860200410..e2ac09894a6d 100644 --- a/drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h +++ b/drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h @@ -83,7 +83,6 @@ #define VSIZE_OFST 20 #define LDI_INT_EN 0x741C #define FRAME_END_INT_EN_OFST 1 -#define UNDERFLOW_INT_EN_OFST 2 #define LDI_CTRL 0x7420 #define BPP_OFST 3 #define DATA_GATE_EN BIT(2) diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c index 73cd28a6ea07..86000127d4ee 100644 --- a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c +++ b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c @@ -46,7 +46,6 @@ struct ade_hw_ctx { struct clk *media_noc_clk; struct clk *ade_pix_clk; struct reset_control *reset; - struct work_struct display_reset_wq; bool power_on; int irq; @@ -136,7 +135,6 @@ static void ade_init(struct ade_hw_ctx *ctx) */ ade_update_bits(base + ADE_CTRL, FRM_END_START_OFST, FRM_END_START_MASK, REG_EFFECTIVE_IN_ADEEN_FRMEND); - ade_update_bits(base + LDI_INT_EN, UNDERFLOW_INT_EN_OFST, MASK(1), 1); } static bool ade_crtc_mode_fixup(struct drm_crtc *crtc, @@ -304,17 +302,6 @@ static void ade_crtc_disable_vblank(struct drm_crtc *crtc) MASK(1), 0); } -static void drm_underflow_wq(struct work_struct *work) -{ - struct ade_hw_ctx *ctx = container_of(work, struct ade_hw_ctx, - display_reset_wq); - struct drm_device *drm_dev = ctx->crtc->dev; - struct drm_atomic_state *state; - - state = drm_atomic_helper_suspend(drm_dev); - drm_atomic_helper_resume(drm_dev, state); -} - static irqreturn_t ade_irq_handler(int irq, void *data) { struct ade_hw_ctx *ctx = data; @@ -331,12 +318,6 @@ static irqreturn_t ade_irq_handler(int irq, void *data) MASK(1), 1); drm_crtc_handle_vblank(crtc); } - if (status & BIT(UNDERFLOW_INT_EN_OFST)) { - ade_update_bits(base + LDI_INT_CLR, UNDERFLOW_INT_EN_OFST, - MASK(1), 1); - DRM_ERROR("LDI underflow!"); - schedule_work(&ctx->display_reset_wq); - } return IRQ_HANDLED; } @@ -919,7 +900,6 @@ static void *ade_hw_ctx_alloc(struct platform_device *pdev, if (ret) return ERR_PTR(-EIO); - INIT_WORK(&ctx->display_reset_wq, drm_underflow_wq); ctx->crtc = crtc; return ctx;