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[209.132.180.67]) by mx.google.com with ESMTP id eg4si51408774pac.40.2016.02.08.21.03.55; Mon, 08 Feb 2016 21:03:55 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dkim=pass header.i=@linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756618AbcBIFDx (ORCPT + 30 others); Tue, 9 Feb 2016 00:03:53 -0500 Received: from mail-pf0-f174.google.com ([209.85.192.174]:35998 "EHLO mail-pf0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754417AbcBIFCS (ORCPT ); Tue, 9 Feb 2016 00:02:18 -0500 Received: by mail-pf0-f174.google.com with SMTP id e127so25977777pfe.3 for ; Mon, 08 Feb 2016 21:02:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=S1VkTHYDXtUj+sHYJVQr40r16MH4+YvBAKUCWYSYlI8=; b=Ejr6/JhQBlFIPK0yYin64N0ObfXmTp8qudzPT0JH3eGolgx+NnpI6BqGN2BGORlOSK M3qjXzZx0N2EO6Zwrsqc9d1jILNP/TByTLleIX9OvhfGvyQQr7FZqLcNdmX+6GxYPKST S4/6XEVdl8O8dkZAGYXkFipllSxRPfX5zv1xo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=S1VkTHYDXtUj+sHYJVQr40r16MH4+YvBAKUCWYSYlI8=; b=d5EJy6NSOkAf7khZ8CXy8RyKoaKendSP5hwIfMmL1G+y5K+rQJE0reTepRU+ffoOIE WMsW/xoPeC8BTk6d4Byp/whaPogkvTs8m+jecv/xcggYIpD1cwxbxguY2El0u9rLZ5rv tNUP0ssu9/j98fkICPeKLQOns/AVX5YXZ5Z93rdNUMmtqtT4PfL5AjHRA3Ny++ALuIz/ WoaVGeKlWFDbzuwsbmD+PfzrcZDFm4/LO7/cXyAkABag29ZwTogli8YXLPU6zO8pX5kv XgFoXcH2ZWyIbbMu6z3voK1gSGH6RPjid8W2UGhfd4lmZc4Pr9IEDiRVK+uPk9GqO5R7 2HLA== X-Gm-Message-State: AG10YORzQnVSrOPt5EJ44WmrtKCKMuLXC9EbL+OlzhrfCqnEZg9i3nIqLbVTkya86+CSZnI5 X-Received: by 10.98.68.73 with SMTP id r70mr48155223pfa.136.1454994137730; Mon, 08 Feb 2016 21:02:17 -0800 (PST) Received: from localhost ([122.172.22.246]) by smtp.gmail.com with ESMTPSA id o17sm46865905pfj.50.2016.02.08.21.02.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 08 Feb 2016 21:02:17 -0800 (PST) From: Viresh Kumar To: Rafael Wysocki Cc: linaro-kernel@lists.linaro.org, linux-pm@vger.kernel.org, Stephen Boyd , nm@ti.com, Viresh Kumar , linux-kernel@vger.kernel.org (open list) Subject: [PATCH V3 13/16] cpufreq: dt: Reuse dev_pm_opp_get_max_transition_latency() Date: Tue, 9 Feb 2016 10:30:45 +0530 Message-Id: <434aede394a1dd52ce381f0e5390d85d1b6995ba.1454992187.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.7.1.370.gb2aa7f8 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org OPP layer has all the information now to calculate transition latency (clock_latency + voltage_latency). Lets reuse the OPP layer helper dev_pm_opp_get_max_transition_latency() instead of open coding the same in cpufreq-dt driver. Signed-off-by: Viresh Kumar Reviewed-by: Stephen Boyd --- drivers/cpufreq/cpufreq-dt.c | 48 ++++---------------------------------------- 1 file changed, 4 insertions(+), 44 deletions(-) -- 2.7.1.370.gb2aa7f8 diff --git a/drivers/cpufreq/cpufreq-dt.c b/drivers/cpufreq/cpufreq-dt.c index c3fe89461ff4..6f80ce56b4ec 100644 --- a/drivers/cpufreq/cpufreq-dt.c +++ b/drivers/cpufreq/cpufreq-dt.c @@ -222,7 +222,6 @@ static int cpufreq_init(struct cpufreq_policy *policy) struct regulator *cpu_reg; struct clk *cpu_clk; struct dev_pm_opp *suspend_opp; - unsigned long min_uV = ~0, max_uV = 0; unsigned int transition_latency; bool opp_v1 = false; const char *name; @@ -316,49 +315,6 @@ static int cpufreq_init(struct cpufreq_policy *policy) priv->reg_name = name; of_property_read_u32(np, "voltage-tolerance", &priv->voltage_tolerance); - transition_latency = dev_pm_opp_get_max_clock_latency(cpu_dev); - if (!transition_latency) - transition_latency = CPUFREQ_ETERNAL; - - if (!IS_ERR(cpu_reg)) { - unsigned long opp_freq = 0; - - /* - * Disable any OPPs where the connected regulator isn't able to - * provide the specified voltage and record minimum and maximum - * voltage levels. - */ - while (1) { - struct dev_pm_opp *opp; - unsigned long opp_uV, tol_uV; - - rcu_read_lock(); - opp = dev_pm_opp_find_freq_ceil(cpu_dev, &opp_freq); - if (IS_ERR(opp)) { - rcu_read_unlock(); - break; - } - opp_uV = dev_pm_opp_get_voltage(opp); - rcu_read_unlock(); - - tol_uV = opp_uV * priv->voltage_tolerance / 100; - if (regulator_is_supported_voltage(cpu_reg, - opp_uV - tol_uV, - opp_uV + tol_uV)) { - if (opp_uV < min_uV) - min_uV = opp_uV; - if (opp_uV > max_uV) - max_uV = opp_uV; - } - - opp_freq++; - } - - ret = regulator_set_voltage_time(cpu_reg, min_uV, max_uV); - if (ret > 0) - transition_latency += ret * 1000; - } - ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table); if (ret) { dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret); @@ -393,6 +349,10 @@ static int cpufreq_init(struct cpufreq_policy *policy) cpufreq_dt_attr[1] = &cpufreq_freq_attr_scaling_boost_freqs; } + transition_latency = dev_pm_opp_get_max_transition_latency(cpu_dev); + if (!transition_latency) + transition_latency = CPUFREQ_ETERNAL; + policy->cpuinfo.transition_latency = transition_latency; of_node_put(np);