From patchwork Fri Dec 1 13:44:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Quentin Schulz X-Patchwork-Id: 120331 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp1158442qgn; Fri, 1 Dec 2017 05:47:20 -0800 (PST) X-Google-Smtp-Source: AGs4zMaG4ivQ7QsNAa38aPzDZFMWXzXI4xHboWFU2fz50x1Eh8wjlXNbzDRgo08b8g2ysVEVEkWI X-Received: by 10.101.77.210 with SMTP id q18mr1761105pgt.145.1512136040343; Fri, 01 Dec 2017 05:47:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512136040; cv=none; d=google.com; s=arc-20160816; b=ZHoADKLt2QMNrg6I46gc9c3i1d499CYtyU87Sr3o8CpoAWrllc8Y57lknwnxuAkwF+ zNjEc1X6rlWlYOjupbLkAzSza5uNjfsOmrNqOlokmqF7Yh+GGvhZHItTVRKd/HFjnEdS sE2sla/RKnWo6Z0ZRw7E5MiEbFv64nvNrM6rZrRrMzC9hkmby141hl9mdC7mJpLv3RHx LkNyZC0ir36FRK2FDX/8o7EWsCSFSvZZWhLj2MuECKkQhluuKvzVexOAJyo5ZojxLUh7 nfV1dI6OnyGWA3fJTTjDiuqGNCy50k1HCzbvFexfdyJAPUyj3mej0MRVa09x0swhPik8 zrBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=vx7UpIIGJaorKsXgUqIfWO5HaSurIsQrPUs94FO/QkQ=; b=RlryYF9VUg7NpCC+GCV2OTQyNTZvVtkLyslAyNJ8PwLup19CR91E47AVqyeiOhCbhu ZHNHVYffyYB4bYOxQtdPPl34v8eadHKRMNpjmrqUB04u55Ai34nzerS0dHG4EXRljtiW M5Jf5/NJTVy+xs5wtbGdXmnWA3wzpIC1c3/QuxkO9xsOqdxW4mBftrsPfNQJql1vC0mS OXE8zg5WxSta6vLZQKb6fYgJzNBrHhVsNVa+hXRzjebHDlsTthCxxBFIilITSuM4GKdf mzImJ7xKnDJAeeIQkZWeGT/X2mG5kBp/FwPDBwdNDGBp6Q9h/UeBIB97/Lqdb4euSL6O d0sw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t19si5048738plj.431.2017.12.01.05.47.20; Fri, 01 Dec 2017 05:47:20 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753181AbdLANrS (ORCPT + 28 others); Fri, 1 Dec 2017 08:47:18 -0500 Received: from mail.free-electrons.com ([62.4.15.54]:36264 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752935AbdLANpw (ORCPT ); Fri, 1 Dec 2017 08:45:52 -0500 Received: by mail.free-electrons.com (Postfix, from userid 110) id 510FD20C91; Fri, 1 Dec 2017 14:45:50 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost.localdomain (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id EB46A20989; Fri, 1 Dec 2017 14:45:39 +0100 (CET) From: Quentin Schulz To: linus.walleij@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, wens@csie.org, linux@armlinux.org.uk, maxime.ripard@free-electrons.com, lee.jones@linaro.org Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, thomas.petazzoni@free-electrons.com, linux-sunxi@googlegroups.com, Quentin Schulz Subject: [PATCH v4 06/10] pinctrl: axp209: add programmable ADC muxing value Date: Fri, 1 Dec 2017 14:44:47 +0100 Message-Id: X-Mailer: git-send-email 2.14.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org To prepare for patches that will add support for a new PMIC that has a different GPIO adc muxing value, add an adc_mux within axp20x_pctl structure and use it. Signed-off-by: Quentin Schulz --- drivers/pinctrl/pinctrl-axp209.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) -- git-series 0.9.1 diff --git a/drivers/pinctrl/pinctrl-axp209.c b/drivers/pinctrl/pinctrl-axp209.c index 3fae81f..504e96c 100644 --- a/drivers/pinctrl/pinctrl-axp209.c +++ b/drivers/pinctrl/pinctrl-axp209.c @@ -49,6 +49,7 @@ struct axp20x_pctrl_desc { /* Stores the pins supporting ADC function. Bit offset is pin number. */ u8 adc_mask; u8 gpio_status_offset; + u8 adc_mux; }; struct axp20x_pinctrl_function { @@ -79,6 +80,7 @@ static const struct axp20x_pctrl_desc axp20x_data = { .ldo_mask = BIT(0) | BIT(1), .adc_mask = BIT(0) | BIT(1), .gpio_status_offset = 4, + .adc_mux = AXP20X_MUX_ADC, }; static int axp20x_gpio_get_reg(unsigned offset) @@ -333,7 +335,7 @@ static void axp20x_build_funcs_groups(struct platform_device *pdev) * See comment in axp20x_pmx_set_mux. */ pctl->funcs[AXP20X_FUNC_ADC].name = "adc"; - pctl->funcs[AXP20X_FUNC_ADC].muxval = AXP20X_MUX_ADC; + pctl->funcs[AXP20X_FUNC_ADC].muxval = pctl->desc->adc_mux; /* Every pin supports GPIO_OUT and GPIO_IN functions */ for (i = 0; i <= AXP20X_FUNC_GPIO_IN; i++) {