diff --git a/platform/linux-keystone2/Makefile b/platform/linux-keystone2/Makefile
index 15e2a2c..036f7d5 100644
--- a/platform/linux-keystone2/Makefile
+++ b/platform/linux-keystone2/Makefile
@@ -32,10 +32,24 @@ ODP_ROOT = ../..
 LIB_DIR  = ./lib
 DOC_DIR  = ./doc
 
+MY_PLATFORM = DEVICE_K2K
+OPENEM_PREBUILTS_DIR=./prebuilts/openem/c6638/arm-linux
+
+PLAT_CFLAGS  = -D$(MY_PLATFORM)
+PLAT_CFLAGS += -D_GNU_SOURCE -DEM_32_BIT -DTI_EM_CENTRAL_SCHED
+PLAT_CFLAGS += -DTI_EM_TRACE_LEVEL=3 -DEM_CHECK_LEVEL=1
+PLAT_CFLAGS += -DTI_EM_LINUX -DTI_EM_GCC -DTI_EM_ARM_A15 -DTI_EM_C6638
+PLAT_CFLAGS += -D_LITTLE_ENDIAN -DTI_EM_USE_MSM -DTI_EM_XGE_LOOPBACK
+PLAT_CFLAGS += -DTI_ODP
+
+EXTRA_CFLAGS  += $(PLAT_CFLAGS)
 EXTRA_CFLAGS  += -I$(ODP_ROOT)/include
 EXTRA_CFLAGS  += -I./include
 EXTRA_CFLAGS  += -I./include/api
-EXTRA_CFLAGS  += -fPIC
+EXTRA_CFLAGS  += -I./prebuilts/openem/include
+EXTRA_CFLAGS  += -I./prebuilts/openem/include/linux/keystone2
+EXTRA_CFLAGS  += -I./prebuilts/openem/include/linux/osal
+EXTRA_CFLAGS  += -I./prebuilts/openem/include/linux/rh
 
 ifeq ($(ODP_HAVE_NETMAP),yes)
 EXTRA_CFLAGS  += -DODP_HAVE_NETMAP
@@ -100,8 +114,8 @@ $(OBJ_DIR)/%.o: ./source/%.c
 #
 # Lib rule
 #
-$(STATIC_LIB): $(OBJS)
-	$(AR) -cr $@ $(OBJS)
+$(STATIC_LIB): $(OBJS) extract_prebuilt_libs
+	$(AR) -cr $@ $(OBJ_DIR)/*.o
 
 clean:
 	$(RMDIR) $(OBJ_DIR)
@@ -124,6 +138,11 @@ docs_install: docs
 pdf: docs
 	make --directory doc/latex refman.pdf 1> /dev/null
 
+.PHONY: extract_prebuilt_libs
+extract_prebuilt_libs: $(OBJ_DIR)
+	(cd $(OBJ_DIR) && $(AR) x ../$(OPENEM_PREBUILTS_DIR)/libopenem_osal.a)
+	(cd $(OBJ_DIR) && $(AR) x ../$(OPENEM_PREBUILTS_DIR)/libopenem_rh.a)
+
 .PHONY: libs
 libs: $(OBJ_DIR) $(LIB_DIR) $(STATIC_LIB)
 
diff --git a/platform/linux-keystone2/prebuilts/openem/c6638/arm-linux/em_mod.ko b/platform/linux-keystone2/prebuilts/openem/c6638/arm-linux/em_mod.ko
new file mode 100644
index 0000000000000000000000000000000000000000..9112ec5102579e8f58f017ed760e265c01713b38
GIT binary patch
diff --git a/platform/linux-keystone2/prebuilts/openem/c6638/arm-linux/libopenem_osal.a b/platform/linux-keystone2/prebuilts/openem/c6638/arm-linux/libopenem_osal.a
new file mode 100644
index 0000000000000000000000000000000000000000..c64299e04a3049da641b8c1bca2efa5e18d95a99
GIT binary patch
diff --git a/platform/linux-keystone2/prebuilts/openem/c6638/arm-linux/libopenem_rh.a b/platform/linux-keystone2/prebuilts/openem/c6638/arm-linux/libopenem_rh.a
new file mode 100644
index 0000000000000000000000000000000000000000..015214ca5d8f9d718a4541d66f1475eb7360108f
GIT binary patch
diff --git a/platform/linux-keystone2/prebuilts/openem/include/event_machine.h b/platform/linux-keystone2/prebuilts/openem/include/event_machine.h
new file mode 100644
index 0000000..4987577
--- /dev/null
+++ b/platform/linux-keystone2/prebuilts/openem/include/event_machine.h
@@ -0,0 +1,256 @@
+/*
+ *   Copyright (c) 2012, Nokia Siemens Networks
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *       * Redistributions of source code must retain the above copyright
+ *         notice, this list of conditions and the following disclaimer.
+ *       * Redistributions in binary form must reproduce the above copyright
+ *         notice, this list of conditions and the following disclaimer in the
+ *         documentation and/or other materials provided with the distribution.
+ *       * Neither the name of Nokia Siemens Networks nor the
+ *         names of its contributors may be used to endorse or promote products
+ *         derived from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ *   WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY
+ *   DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ *   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *   ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/**
+ *
+ * Contributors
+ *
+ * The initial developer of the original code is Nokia Siemens Networks.
+ *  The following contributors have made changes to 
+ *  the original code as described below.
+ * 
+ *----------------------------------------------------------------------------------------------
+ * Copyright (c) 2012, Texas Instruments Incorporated. All Rights Reserved. - http://www.ti.com/
+ * 
+ * Changes were done on the original NSN header files in order to avoid 
+ * circular dependencies when called in the TI implementation files.
+ *
+ * From the original event_machine.h, the list of changes are:
+ *   - Functions definitions are now located in:
+ *     - openem/event_machine_functions.h
+ *   - Doxygen tags are added for API documentation generation.
+ *
+ * The event_machine.h is now just an aggregator of include files. It will
+ * be called by the Open Event Machine user. 
+ *
+ * Finally, the Open Event Machine is a RTSC component.
+ * See http://rtsc.eclipse.org/docs-tip/Main_Page for details.
+ *
+ *----------------------------------------------------------------------------------------------
+ */
+
+
+/**
+ * @file : event_machine.h
+ *
+ * @brief
+ * Open Event Machine API v1.0
+ *
+ */
+  
+#ifndef EVENT_MACHINE_H
+#define EVENT_MACHINE_H
+/**
+ * @mainpage
+ *
+ * This document contains information about the Texas Instruments implementation of the Open Event Machine.
+ *
+ * The file event_machine.h represents the interface of the event machine library.
+ * It includes all the specifications needed to use the library.
+ * It shall be included as follows to access the event machine functionality.
+ * @code #include <event_machine.h>
+ * @endcode
+ * 
+ * The file event_machine_firmware.h contains the binary of the micro risc controller implementing the event machine scheduler.
+ * The binary shall be loaded in the micro risc controller when initializing the QMSS.
+ * This file shall be included as follows.
+ * @code #include <firmware/event_machine_firmware.h>
+ * @endcode
+
+ * Limitations of the Texas Instruments implementation of the Open Event Machine are listed in the release notes document.
+ *
+ * @n This document is divided into the following sections:
+ *
+ * - @subpage DOC_intro
+ *
+ * - @subpage DOC_error
+ *
+ * - @subpage DOC_trace
+ *
+ * - @subpage DOC_api_generic
+ *
+ * - @subpage DOC_api_specific
+ */
+
+
+
+#define EM_API_VERSION_MAJOR 1     /**< Major API version number. Step if not backwards compatible  */
+#define EM_API_VERSION_MINOR 0     /**< Minor API version number. Updates and additions             */
+
+
+/** 
+ *
+ * @page DOC_intro Introduction
+ * @section section_1 General
+ * Event Machine (EM) is an architectural abstraction and framework of an event driven
+ * multicore optimized processing concept originally developed for networking data plane.
+ * It offers an easy programming concept for scalable and dynamically load balanced
+ * multicore applications with a very low overhead run-to-completion principle.
+ *
+ * Main elements in the concept are events, queues, scheduler, dispatcher and the
+ * execution objects (EO). Event is an application specific piece of data (like a message
+ * or a network packet) describing work, something to do. Any processing in EM must be
+ * triggered by an event. Events are sent to asynchronous application specific queues.
+ * A single thread on all cores of an EM instance runs a dispatcher loop (a "core" is
+ * used here to refer to a core or one HW thread on multi-threaded cores). Dispatcher
+ * interfaces with the scheduler and asks for an event. Scheduler evaluates the state
+ * of all queues and gives the highest priority event to the dispatcher, which forwards
+ * it to the EO mapped to the queue the event came from by calling the registered receive
+ * function. As the event is handled and receive function returns, the next event is
+ * received from the scheduler and again forwarded to the mapped EO. This happens in
+ * parallel on all cores included. Everything is highly efficient run to completion
+ * single thread, no context switching nor pre-emption (priorities are handled by the
+ * scheduler).
+ * EM can run on bare metal for best performance or under an operating system with special
+ * arrangements (e.g. one thread per core with thread affinity).
+ *
+ * The concept and this API are made to be easy to implement for multiple general purpose or
+ * networking oriented multicore packet processing systems on chip, which typically also
+ * contain accelerators for packet processing needs. Efficient integration with modern HW
+ * accelerators has been a major driver in EM concept.
+ *
+ * One general principle of this API is that all calls are multicore safe, i.e.
+ * no data structure gets broken, if calls are simultaneously made by multiple cores, but
+ * unless explicitly documented per API call, the application also needs to take the parallel
+ * world into consideration. For example if one core asks for a queue mode and another one
+ * changes the mode at the same time, the returned mode may be invalid (valid data, but the old
+ * or the new!). Thus modifications should be done under atomic context (if load balancing is
+ * used) or otherwise synchronized by the application. One simple way of achieving this is to use
+ * one EO with an atomic queue to do all the management functionality. That guarantees
+ * synchronized operations (but also serializes them limiting performance)
+ *
+ * EM_64_BIT or EM_32_BIT (needs to be defined at makefile) defines whether (most of)
+ * the types used in the API are 32 or 64 bits wide. NOTE, that this is a major decision,
+ * since it may limit value passing between different systems using the defined types directly.
+ * Using 64-bits may allow more efficient underlying implementation, as more data can be coded
+ * in 64-bit identifiers for instance.
+ *
+ * @section section_2 Some principles
+ * - This API attempts to guide towards a portable application architecture, but is not defined
+ *  for portability by re-compilation. Many things are system specific giving more possibilities
+ *  for efficient use of HW resources.
+ * - EM does not define event content (one exception, see em_alloc()). This is a choice made for
+ * performance, since most HW devices use proprietary descriptors. This API enables to use those directly.
+ * - EM does not define detailed queue scheduling disciplines or API to set those up (or actually
+ * anything to configure a system). The priority value in this API is a (mapped) system specific
+ * QoS class label only
+ * - In general EM does not implement full SW platform or middleware solution, it implements a sub-
+ * set of such, a driver level part. For best performance it can be used directly from applications.
+ *
+ */
+
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * @defgroup DOC_api_generic Generic API
+ * @brief Generic declarations.
+ */
+/**
+ * @defgroup DOC_api_specific TI specific API
+ * @brief Implementation specific declarations.
+ * @attention Unless otherwise specified values of symbolic constants cannot be changed.
+ */
+
+/** 
+ *
+ * @page DOC_error Error
+ * @section section_101 mechanism
+ * 
+ * The error handler prototype to be provided by the application to the OpenEM when activating the error mecanism shall comply with the following prototype:
+ * 
+ * 
+ * em_status_t (*em_error_handler_t)(em_eo_t eo, em_status_t error, em_escope_t escope, va_list args)
+ * 
+ * 
+ * In the current implementation, the OpenEM does not consider using other parameters other than the 
+ * execution object (eo), the error code (error) and the error scope (escope). 
+ * 
+ * @see em_error_handler_t(), em_register_error_handler(), em_unregister_error_handler, em_eo_register_error_handler, em_eo_unregister_error_handler()
+ * 
+ */
+
+/** 
+ *
+ * @page DOC_trace Trace
+ * @section section_201 mechanism
+ * 
+ * The trace handler prototype to be provided by the application to the OpenEM when activating the trace mechanism shall comply with the following prototype:
+ * 
+ * 
+ * em_status_t (*ti_em_trace_handler_t)(ti_em_tscope_t tscope, ...)
+ * 
+ * 
+ * In the curent implementation, the OpenEM assumes the trace of the following APIs to be associated to the following set of input parameters:
+ * 
+ * - void ti_em_preschedule(void)                                                          -> TI_EM_TSCOPE_PRESCHEDULE
+ * 
+ * - em_status_t ti_em_dispatch_once (void)                                                -> TI_EM_TSCOPE_DISPATCH
+ * 
+ * - void* ti_em_claim_local (void)                                                        -> TI_EM_TSCOPE_CLAIM_LOCAL, (void*)(buffer_ptr)
+ * 
+ * - em_event_t em_alloc(size_t size, em_event_type_t type, em_pool_id_t pool_id)          -> TI_EM_TSCOPE_ALLOC, (em_event_t)(event), (uint32_t)(size), (em_event_type_t)(type), (em_pool_id_t)(pool_id)
+ * 
+ * - void em_atomic_processing_end(void)                                                   -> TI_EM_TSCOPE_ATOMIC_PROCESSING_END
+ * 
+ * - void em_free(em_event_t event)                                                        -> TI_EM_TSCOPE_FREE, (em_event_t)(event)
+ * 
+ * - em_status_t em_send(em_event_t event, em_queue_t queue)                               -> TI_EM_TSCOPE_SEND, (em_event_t)(event), (em_queue_t)(queue)
+ * 
+ * - em_status_t em_send_group(em_event_t event, em_queue_t queue, em_event_group_t group) -> TI_EM_TSCOPE_SEND, (em_event_t)(event), (em_queue_t)(queue), (em_event_group_t)(eventGroup)
+ * 
+ * 
+ * @see ti_em_trace_handler_t(), ti_em_register_trace_handler(), ti_em_unregister_trace_handler() 
+ * 
+ */
+
+/* Basic EM types and HW configuration */
+#include <event_machine_macros.h>
+#include <event_machine_types.h>
+#include <event_machine_functions.h>
+#include <event_machine_group.h>
+#include <event_machine_core_mask.h>
+#include <event_machine_helper.h>
+
+/* EM HW */
+#include <event_machine_hw.h>
+
+/* EM SW */
+#include <event_machine_sw.h>
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* EVENT_MACHINE_H */
+
+
diff --git a/platform/linux-keystone2/prebuilts/openem/include/event_machine_core_mask.h b/platform/linux-keystone2/prebuilts/openem/include/event_machine_core_mask.h
new file mode 100644
index 0000000..9326c88
--- /dev/null
+++ b/platform/linux-keystone2/prebuilts/openem/include/event_machine_core_mask.h
@@ -0,0 +1,434 @@
+/*
+ *   Copyright (c) 2012, Nokia Siemens Networks
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *       * Redistributions of source code must retain the above copyright
+ *         notice, this list of conditions and the following disclaimer.
+ *       * Redistributions in binary form must reproduce the above copyright
+ *         notice, this list of conditions and the following disclaimer in the
+ *         documentation and/or other materials provided with the distribution.
+ *       * Neither the name of Nokia Siemens Networks nor the
+ *         names of its contributors may be used to endorse or promote products
+ *         derived from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ *   WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY
+ *   DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ *   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *   ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ 
+
+/**
+ *
+ * Contributors
+ *
+ * The initial developer of the original code is Nokia Siemens Networks.
+ *  The following contributors have made changes to 
+ *  the original code as described below.
+ * 
+ *----------------------------------------------------------------------------------------------
+ * Copyright (c) 2012, Texas Instruments Incorporated. All Rights Reserved. - http://www.ti.com/
+ * 
+ * Changes were done on the original NSN header files in order to avoid 
+ * circular dependencies when called in the TI implementation files.
+ *
+ * From the original event_machine_helper.h, the list of changes are:
+ *   - The included files are now event_machine_types.h and event_machine_macros.h
+ *   - Doxygen tags are added for API documentation generation.
+ *       - Doxygen comments were copied from the 64-BIT implementation to the 32-BIT section
+ *         since the TI implementation only support 32-BIT section.
+ *----------------------------------------------------------------------------------------------
+ *
+ */
+
+
+/**
+ * @file: event_machine_core_mask.h
+ *
+ * @brief
+ *    Event Machine core mask functions. This implementation is generic C - non HW optimized. 
+ *
+ */
+
+#ifndef EVENT_MACHINE_CORE_MASK_H_
+#define EVENT_MACHINE_CORE_MASK_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <event_machine_macros.h>
+#include <event_machine_types.h>
+
+
+
+
+#if EM_CORE_MASK_SIZE != 64
+#error Core mask functions support only 64 bit mask size
+#endif
+
+
+
+#ifdef EM_64_BIT
+/*
+ *
+ * 64 bit versions.
+ * --------------------------------------------
+ */
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Zero the whole mask.
+ *
+ * @param mask      Core mask
+ */
+static inline void em_core_mask_zero(em_core_mask_t* mask)
+{
+  mask->u64[0] = 0;
+}
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Set a bit in the mask.
+ *
+ * @param core      Core id
+ * @param mask      Core mask
+ */
+static inline void em_core_mask_set(int core, em_core_mask_t* mask)
+{
+  mask->u64[0] |= ((uint64_t)1 << core);
+}
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Clear a bit in the mask.
+ *
+ * @param core      Core id
+ * @param mask      Core mask
+ */
+static inline void em_core_mask_clr(int core, em_core_mask_t* mask)
+{
+  mask->u64[0] &= ~((uint64_t)1 << core);
+}
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Test if a bit is set in the mask.
+ *
+ * @param core      Core id
+ * @param mask      Core mask
+ *
+ * @return Non-zero if core id is set in the mask
+ */
+static inline int em_core_mask_isset(int core, const em_core_mask_t* mask)
+{
+  return (mask->u64[0] & ((uint64_t)1 << core));
+}
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Test if the mask is all zero.
+ *
+ * @param mask      Core mask
+ *
+ * @return Non-zero if the mask is all zero
+ */
+static inline int em_core_mask_iszero(const em_core_mask_t* mask)
+{
+  return (mask->u64[0] == 0);
+}
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Test if two masks are equal
+ *
+ * @param mask1     First core mask
+ * @param mask2     Second core mask
+ *
+ * @return Non-zero if the two masks are equal
+ */
+static inline int em_core_mask_equal(const em_core_mask_t* mask1, const em_core_mask_t* mask2)
+{
+  return (mask1->u64[0] == mask2->u64[0]);
+}
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Set a range (0...count-1) of bits in the mask.
+ * 
+ * @param count     Number of bits to set
+ * @param mask      Core mask
+ */
+static inline void em_core_mask_set_count(int count, em_core_mask_t* mask)
+{
+  mask->u64[0] |= (((uint64_t)1 << count) - 1);
+}
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Copy core mask
+ *
+ * @param dest      Destination core mask
+ * @param src       Source core mask
+ */
+static inline void em_core_mask_copy(em_core_mask_t* dest, const em_core_mask_t* src)
+{
+  dest->u64[0] = src->u64[0];
+}
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Count the number of bits set in the mask.
+ *
+ * @param mask      Core mask
+ *
+ * @return Number of bits set
+ */
+static inline int em_core_mask_count(const em_core_mask_t* mask)
+{
+  uint64_t n = mask->u64[0];
+  int      cnt;
+  
+
+  for(cnt = 0; n; cnt++)
+  {
+    n &= (n - 1); // Clear the least significant bit set
+  }
+  
+  return cnt;
+}
+
+
+
+
+#elif defined(EM_32_BIT)
+/*
+ *
+ * 32 bit versions.
+ * --------------------------------------------
+ */
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Zero the whole mask.
+ *
+ * @param mask      Core mask
+ */
+static inline void em_core_mask_zero(em_core_mask_t* mask)
+{
+  mask->u32[0] = 0;
+  mask->u32[1] = 0;
+}
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Set a bit in the mask.
+ *
+ * @param core      Core id
+ * @param mask      Core mask
+ */
+static inline void em_core_mask_set(int core, em_core_mask_t* mask)
+{
+  if(core < 32)
+  {
+    mask->u32[1] |= ((uint32_t)1 << core);
+  }
+  else
+  {
+    mask->u32[0] |= ((uint32_t)1 << (core - 32) );
+  }
+}
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Clear a bit in the mask.
+ *
+ * @param core      Core id
+ * @param mask      Core mask
+ */
+static inline void em_core_mask_clr(int core, em_core_mask_t* mask)
+{
+  if(core < 32)
+  {
+    mask->u32[1] &= ~((uint32_t)1 << core);
+  }
+  else
+  {
+    mask->u32[0] &= ~((uint32_t)1 << (core - 32) );
+  }
+}
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Test if a bit is set in the mask.
+ *
+ * @param core      Core id
+ * @param mask      Core mask
+ *
+ * @return Non-zero if core id is set in the mask
+ */
+static inline int em_core_mask_isset(int core, const em_core_mask_t* mask)
+{
+  if(core < 32)
+  {
+    return (mask->u32[1] & ((uint32_t)1 << core));
+  }
+  else
+  {
+    return (mask->u32[0] & ((uint32_t)1 << (core - 32)));
+  }
+}
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Test if the mask is all zero.
+ *
+ * @param mask      Core mask
+ *
+ * @return Non-zero if the mask is all zero
+ */
+static inline int em_core_mask_iszero(const em_core_mask_t* mask)
+{
+  return ((mask->u32[0] == 0) && (mask->u32[1] == 0));
+}
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Test if two masks are equal
+ *
+ * @param mask1     First core mask
+ * @param mask2     Second core mask
+ *
+ * @return Non-zero if the two masks are equal
+ */
+static inline int em_core_mask_equal(const em_core_mask_t* mask1, const em_core_mask_t* mask2)
+{
+  return ((mask1->u32[0] == mask2->u32[0]) && (mask1->u32[1] == mask2->u32[1]));
+}
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Set a range (0...count-1) of bits in the mask.
+ * 
+ * @param count     Number of bits to set
+ * @param mask      Core mask
+ */
+static inline void em_core_mask_set_count(int count, em_core_mask_t* mask)
+{
+  if(count <= 32)
+  {
+    mask->u32[1] |= (((uint32_t)1 << count) - 1);
+  }
+  else
+  {
+    mask->u32[1] |= 0xffffffff;
+    mask->u32[0] |= (((uint32_t)1 << (count - 32)) - 1);
+  }
+}
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Copy core mask
+ *
+ * @param dest      Destination core mask
+ * @param src       Source core mask
+ */
+static inline void em_core_mask_copy(em_core_mask_t* dest, const em_core_mask_t* src)
+{
+  dest->u32[0] = src->u32[0];
+  dest->u32[1] = src->u32[1];
+}
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Count the number of bits set in the mask.
+ *
+ * @param mask      Core mask
+ *
+ * @return Number of bits set
+ */
+static inline int em_core_mask_count(const em_core_mask_t* mask)
+{
+  uint32_t n;
+  int      cnt, i;
+  
+  for(i = 0, cnt = 0; i < 2; i++)
+  {
+    n = mask->u32[i];
+    
+    for(; n; cnt++) {
+      n &= (n - 1); // clear the least significant bit set
+    }
+  }
+  
+  return cnt;
+}
+
+#endif
+
+
+
+
+/*
+ *  These mask functions could be added also
+ *
+ *  void em_core_mask_and(em_core_mask_t* dest, const em_core_mask_t* src1, const em_core_mask_t* src2);
+ *  void em_core_mask_or(em_core_mask_t* dest, const em_core_mask_t* src1, const em_core_mask_t* src2);
+ *  void em_core_mask_xor(em_core_mask_t* dest, const em_core_mask_t* src1, const em_core_mask_t* src2);
+ *
+ */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* EVENT_MACHINE_CORE_MASK_H_ */
+
diff --git a/platform/linux-keystone2/prebuilts/openem/include/event_machine_functions.h b/platform/linux-keystone2/prebuilts/openem/include/event_machine_functions.h
new file mode 100644
index 0000000..eec71b8
--- /dev/null
+++ b/platform/linux-keystone2/prebuilts/openem/include/event_machine_functions.h
@@ -0,0 +1,885 @@
+/*
+ *   Copyright (c) 2012, Nokia Siemens Networks
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *       * Redistributions of source code must retain the above copyright
+ *         notice, this list of conditions and the following disclaimer.
+ *       * Redistributions in binary form must reproduce the above copyright
+ *         notice, this list of conditions and the following disclaimer in the
+ *         documentation and/or other materials provided with the distribution.
+ *       * Neither the name of Nokia Siemens Networks nor the
+ *         names of its contributors may be used to endorse or promote products
+ *         derived from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ *   WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY
+ *   DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ *   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *   ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/**
+ *
+ * Contributors
+ *
+ * The initial developer of the original code is Nokia Siemens Networks.
+ *  The following contributors have made changes to 
+ *  the original code as described below.
+ * 
+ *----------------------------------------------------------------------------------------------
+ * Copyright (c) 2012, Texas Instruments Incorporated. All Rights Reserved. - http://www.ti.com/
+ * 
+ * Changes were done on the original NSN header files in order to avoid 
+ * circular dependencies when called in the TI implementation files.
+ *
+ * From the original event_machine.h, openem/event_machine_functions.h was
+ * created with:
+ *   - Functions definitions.
+ *   - Doxygen tags are added for API documentation generation.
+ *
+ *----------------------------------------------------------------------------------------------
+ */
+
+
+/**
+ * @file : event_machine_functions.h
+ *
+ * @brief
+ *    Open Event Machine public functions
+ *
+ */
+  
+#ifndef EVENT_MACHINE_FUNCTIONS_H
+#define EVENT_MACHINE_FUNCTIONS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#include <stdlib.h>
+
+/*
+ *
+ * From application to Event Machine interface
+ * ----------------------------------------------------------------------------
+ *
+ */
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Create a new queue with a dynamic queue id.
+ *
+ * The given name string is copied to EM internal data structure. The maximum
+ * string length is EM_QUEUE_NAME_LEN. 
+ *
+ * @param name          Queue name for debugging purposes (optional, NULL ok)
+ * @param type          Queue scheduling type
+ * @param prio          Queue priority
+ * @param group         Queue group for this queue
+ *
+ * @return New queue id or EM_QUEUE_UNDEF on an error
+ *
+ * @see em_queue_group_create(), em_queue_delete()
+ */
+em_queue_t em_queue_create(const char* name, em_queue_type_t type, em_queue_prio_t prio, em_queue_group_t group);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Create a new queue with a static queue id.
+ *
+ * Note, that system may have limited amount of static identifiers,
+ * so unless really needed use dynamic queues instead.
+ * The range of static identifiers is system dependent, but macros
+ * EM_QUEUE_STATIC_MIN and EM_QUEUE_STATIC_MAX can be used to abstract,
+ * i.e. use EM_QUEUE_STATIC_MIN+x for the application.
+ *
+ * The given name string is copied to EM internal data structure. The maximum
+ * string length is EM_QUEUE_NAME_LEN.
+ *
+ * @param name          Queue name for debugging purposes (optional, NULL ok)
+ * @param type          Queue scheduling type
+ * @param prio          Queue priority
+ * @param group         Queue group for this queue
+ * @param queue         Requested queue id from the static range
+ *
+ * @return EM_OK if successful.
+ *
+ * @see em_queue_group_create(), em_queue_delete()
+ */
+em_status_t em_queue_create_static(const char* name, em_queue_type_t type, em_queue_prio_t prio, em_queue_group_t group, em_queue_t queue);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Delete a queue.
+ *
+ * Unallocates the queue id.
+ * NOTE: this is an immediate deletion and can *only*
+ * be done after the queue has been removed from scheduling
+ * using em_eo_remove_queue() !
+ *
+ * @param queue         Queue id to delete
+ *
+ * @return EM_OK if successful.
+ *
+ * @see em_eo_remove_queue(), em_queue_create(), em_queue_create_static()
+ */
+em_status_t em_queue_delete(em_queue_t queue);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Enable event scheduling for the queue.
+ *
+ * All events sent to a non-enabled queue may get discarded or held
+ * depending on the system. Queue enable/disable is not meant to be used
+ * for additional scheduling nor used frequently. Main purpose is to
+ * synchronize startup or recovery actions.
+ *
+ * @param queue         Queue to enable
+ *
+ * @return EM_OK if successful.
+ *
+ * @see em_eo_start(), em_queue_enable_all(), em_queue_disable()
+ */
+em_status_t em_queue_enable(em_queue_t queue);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Enable event scheduling for all the EO's queues.
+ * 
+ * Otherwise identical to em_queue_enable().
+ *
+ * @param eo            EO id 
+ *
+ * @return EM_OK if successful.
+ *
+ * @see em_queue_enable(), em_queue_disable_all()
+ */
+em_status_t em_queue_enable_all(em_eo_t eo);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Disable scheduling for the queue.
+ *
+ * Note, that this might be an asynchronous operation and actually complete later as
+ * other cores may still be handling existing events. If application needs to
+ * know exactly when all processing is completed, it can use the notification
+ * arguments - the given notification(s) are sent after all cores have completed.
+ *
+ * Implicit disable is done for all queues, that are mapped to an EO when
+ * it's stop-function is called (via em_eo_stop()).
+ *
+ * All events sent to a non-enabled queue may get discarded or held
+ * depending on the system. Queue enable/disable is not meant to be used
+ * for additional scheduling nor used frequently. Main purpose is to
+ * synchronize startup or recovery actions.
+ *
+ * @param queue         Queue to disable
+ * @param num_notif     Number of entries in notif_tbl, use 0 for no notification
+ * @param notif_tbl     Notification events to send
+ *
+ * @return EM_OK if successful.
+ *
+ * @see em_eo_stop(), em_queue_disable_all(), em_queue_enable()
+ */
+em_status_t em_queue_disable(em_queue_t queue, int num_notif, const em_notif_t* notif_tbl);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Disable scheduling for all the EO's queues.
+ *
+ * Otherwise identical to em_queue_disable().
+ *
+ * @param eo            EO id
+ * @param num_notif     Number of entries in notif_tbl, use 0 for no notification
+ * @param notif_tbl     Notification events to send
+ *
+ * @return EM_OK if successful.
+ *
+ * @see em_eo_stop(), em_queue_disable(), em_queue_enable_all()
+ */
+em_status_t em_queue_disable_all(em_eo_t eo, int num_notif, const em_notif_t* notif_tbl);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Set queue specific (application) context.
+ * 
+ * This is just a single pointer associated with a queue. Application can use it
+ * to access some context data quickly (without a lookup). The context is given
+ * as argument for the receive function. EM does not use the value, it just
+ * passes it.
+ *                        
+ * @param queue         Queue to which associate the context
+ * @param context       Context pointer
+ *
+ * @return EM_OK if successful.
+ *
+ * @see em_receive_func_t(), em_queue_get_context()
+ */
+em_status_t em_queue_set_context(em_queue_t queue, const void* context);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Get queue specific (application) context.
+ *
+ * Returns the value application has earlier set with em_queue_set_context().
+ *
+ * @param queue         Queue which context is requested
+ *
+ * @return Queue specific context pointer or NULL on an error
+ *
+ * @see em_queue_set_context()
+ */
+void* em_queue_get_context(em_queue_t queue);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Get queue name.
+ *
+ * Returns the name given to a queue when it was created.
+ * A copy of the queue name string (up to 'maxlen' characters) is
+ * written to the user given buffer.
+ * String is always null terminated even if the given buffer length
+ * is less than the name length.
+ *
+ * If the queue has no name, function returns 0 and writes empty string.
+ *
+ * This is only for debugging purposes.
+ *
+ * @param queue         Queue id
+ * @param name          Destination buffer
+ * @param maxlen        Maximum length (including the terminating '0')
+ *
+ * @return Number of characters written (excludes the terminating '0').
+ * 
+ * @see em_queue_create()
+ */
+size_t em_queue_get_name(em_queue_t queue, char* name, size_t maxlen);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Get queue priority.
+ *
+ * @param  queue        Queue identifier
+ *
+ * @return Priority class or EM_QUEUE_PRIO_UNDEF on an error
+ *
+ * @see em_queue_create()
+ */
+em_queue_prio_t em_queue_get_priority(em_queue_t queue);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Get queue type (scheduling mode).
+ *
+ * @param  queue        Queue identifier
+ *
+ * @return Queue type or EM_QUEUE_TYPE_UNDEF on an error
+ *
+ * @see em_queue_create()
+ */
+em_queue_type_t em_queue_get_type(em_queue_t queue);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Get queue's queue group
+ *
+ * @param  queue        Queue identifier 
+ *
+ * @return Queue group or EM_QUEUE_GROUP_UNDEF on error.
+ * 
+ * @see em_queue_create(), em_queue_group_create(), em_queue_group_modify()
+ */
+em_queue_group_t em_queue_get_group(em_queue_t queue);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Create a new queue group to control queue to core mapping.
+ *
+ * Allocates a new queue group identifier with a given core mask. The group name
+ * can have max EM_QUEUE_GROUP_NAME_LEN characters and must be unique 
+ * since it's used to identify the group. Cores added to the queue group can be 
+ * changed later with em_queue_group_modify().
+ *
+ * This operation may be asynchronous, i.e. the creation may complete well
+ * after this function has returned. Provide notification events, if
+ * application cares about the actual completion time. EM will
+ * send notifications when the operation has completed.
+ *
+ * The core mask is visible through em_queue_group_mask() only after the create
+ * operation is complete. 
+ * 
+ * Note, that depending on the system, the operation can also happen one core at a time, so
+ * an intermediate mask may be active momentarily.
+ *
+ * Only manipulate the core mask with the access macros defined in event_machine_core_mask.h
+ * as the implementation underneath may change.
+ *
+ * EM has a default group (EM_QUEUE_GROUP_DEFAULT) containing 
+ * all cores. It's named "default", otherwise naming scheme is system specific.
+ *
+ * Note, some systems may have a low number of queue groups available.
+ *
+ * @attention  Only call em_queue_enable() after em_queue_group_create() has completed - use
+ *             notifications to synchronize.
+ *
+ * @param name          Queue group name. Unique name for identifying the group. 
+ * @param mask          Core mask for the queue group
+ * @param num_notif     Number of entries in notif_tbl (use 0 for no notification)
+ * @param notif_tbl     Array of notifications to send to signal completion of operation
+ *
+ * @return Queue group or EM_QUEUE_GROUP_UNDEF on error.
+ *
+ * @see em_queue_group_find(), em_queue_group_modify(), em_queue_group_delete()
+ */
+em_queue_group_t em_queue_group_create(const char* name, const em_core_mask_t* mask, int num_notif, const em_notif_t* notif_tbl);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Delete the queue group.
+ * 
+ * Removes all cores from the queue group and free's the identifier for re-use. 
+ * All queues in the group must be deleted with em_queue_delete() before
+ * deleting the group.
+ *
+ * @param group         Queue group to delete
+ * @param num_notif     Number of entries in notif_tbl (use 0 for no notification)
+ * @param notif_tbl     Array of notifications to send to signal completion of operation
+ *
+ * @return EM_OK if successful.
+ *
+ * @see em_queue_group_create(), em_queue_group_modify(), em_queue_delete()
+ */
+em_status_t em_queue_group_delete(em_queue_group_t group, int num_notif, const em_notif_t* notif_tbl);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Modify core mask of an existing queue group.
+ *
+ * The function compares the new core mask to the current mask and changes the 
+ * queue group to core mapping accordingly. 
+ *
+ * This operation may be asynchronous, i.e. the change may complete well
+ * after this function has returned. Provide notification events, if
+ * application cares about the actual completion time. EM will
+ * send notifications when the operation has completed.
+ *
+ * The new core mask is visible through em_queue_group_mask() only after the modify
+ * operation is complete. 
+ * 
+ * Note, that depending on the system, the change can also happen one core at a time, so
+ * an intermediate mask may be active momentarily.
+ *
+ * Only manipulate core mask with the access macros defined in event_machine_core_mask.h
+ * as the implementation underneath may change.
+ *
+ * @param group         Queue group to modify
+ * @param new_mask      New core mask 
+ * @param num_notif     Number of entries in notif_tbl (use 0 for no notification)
+ * @param notif_tbl     Array of notifications to send
+ *
+ * @return EM_OK if successful.
+ *
+ * @see em_queue_group_create(), em_queue_group_find(), em_queue_group_delete(), em_queue_group_mask()
+ */
+em_status_t em_queue_group_modify(em_queue_group_t group, const em_core_mask_t* new_mask, int num_notif, const em_notif_t* notif_tbl);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Finds queue group by name.
+ *
+ * This returns the situation at the moment of the inquiry. If another core is modifying the group
+ * at the same time the result may not be up-to-date. Application may need to synchronize group modifications. 
+ *
+ * @param name          Name of the queue qroup to find
+ *
+ * @return  Queue group or EM_QUEUE_GROUP_UNDEF on an error
+ *
+ * @see em_queue_group_create(), em_queue_group_modify()
+ *
+ */
+em_queue_group_t em_queue_group_find(const char* name);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Get current core mask for a queue group.
+ *
+ * This returns the situation at the moment of the inquiry. If another core is modifying the group
+ * at the same time the result may not be up-to-date. Application may need to synchronize group modifications.
+ *
+ * @param group         Queue group
+ * @param mask          Core mask for the queue group
+ *
+ * @return EM_OK if successful.
+ * 
+ * @see em_queue_group_create(), em_queue_group_modify()
+ */
+em_status_t em_queue_group_mask(em_queue_group_t group, em_core_mask_t* mask);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Create Execution Object (EO).
+ * 
+ * This will allocate identifier and initialize internal data for a new EO.
+ * It is left in a non-active state, i.e. no events are dispatched before
+ * em_eo_start() has called. Start, stop and receive callback function
+ * pointers are mandatory parameters.
+ *
+ * The name given is copied to EO internal data and can be used e.g. for debugging.
+ * The maximum length stored is EM_EO_NAME_LEN.
+ *
+ * @param name          Name of the EO (NULL if no name)
+ * @param start         Start function
+ * @param local_start   Core local start function (NULL if no local start)
+ * @param stop          Stop function
+ * @param local_stop    Core local stop function (NULL if no local stop)
+ * @param receive       Receive function
+ * @param eo_ctx        User defined EO context data, EM just passes the pointer (NULL if not context)
+ *
+ * @return New EO id if successful, otherwise EM_EO_UNDEF
+ *
+ * @see em_eo_start(), em_eo_delete(), em_queue_create(), em_eo_add_queue()
+ * @see em_start_func_t(), em_stop_func_t(), em_receive_func_t()
+ */
+em_eo_t em_eo_create(const char* name,
+                     em_start_func_t start,
+                     em_start_local_func_t local_start,
+                     em_stop_func_t stop,
+                     em_stop_local_func_t local_stop,
+                     em_receive_func_t receive,
+                     const void* eo_ctx);
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Delete Execution Object (EO).
+ *
+ * This will immediately delete the given EO and free the identifier.
+ *
+ * NOTE, that EO can only be deleted after it has been stopped using
+ * em_eo_stop(), otherwise another core might still access the EO data!
+ * Deletion will fail, if the EO is not stopped.
+ *
+ * This will delete all possibly remaining queues.
+ *
+ * @param eo            EO id to delete
+ *
+ * @return EM_OK if successful.
+ *
+ * @see em_eo_stop(), em_eo_create()
+ */
+em_status_t em_eo_delete(em_eo_t eo);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Returns the name given to the EO when it was created.
+ *
+ * A copy of the name string (up to 'maxlen' characters) is
+ * written to the user buffer 'name'.
+ * String is always null terminated even if the given buffer length
+ * is less than the name length.
+ *
+ * If the EO has no name, function returns 0 and writes empty string. 
+ *
+ * This is only for debugging purposes.
+ *
+ * @param eo            EO id
+ * @param name          Destination buffer
+ * @param maxlen        Maximum length (including the terminating '0')
+ *
+ * @return Number of characters written (excludes the terminating '0')
+ *
+ * @see em_eo_create() 
+ */
+size_t em_eo_get_name(em_eo_t eo, char* name, size_t maxlen);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Add a queue to an EO.
+ *
+ * Note, that this does not enable the queue. Although queues added in
+ * (or before) the start function will be enabled automatically.
+ *
+ * @param eo            EO id
+ * @param queue         Queue id
+ *
+ * @return EM_OK if successful.
+ *
+ * @see em_queue_create(), em_eo_create(), em_queue_enable(), em_eo_remove_queue()
+ */
+em_status_t em_eo_add_queue(em_eo_t eo, em_queue_t queue);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Removes a queue from an EO.
+ * 
+ * Function disables scheduling of the queue and removes the queue from the
+ * EO. The operation is asynchronous, to quarantee that all cores have completed
+ * processing of events from the queue (i.e. there's no cores in middle of the
+ * receive function) before removing it.
+ *
+ * If the caller needs to know when the context deletion actually occurred,
+ * the num_notif and notif_tbl can be used. The given notification event(s)
+ * will be sent to given queue(s), when the removal has completed.
+ * If such notification is not needed, use 0 as num_notif.
+ *
+ * If the queue to be removed is still enabled, it will first be disabled.
+ *
+ * @param eo            EO id
+ * @param queue         Queue id to remove
+ * @param num_notif     How many notification events given, 0 for no notification
+ * @param notif_tbl     Array of pairs of event and queue identifiers
+ *
+ * @return EM_OK if successful.
+ *
+ * @see em_eo_add_queue(), em_queue_disable(), em_queue_delete()
+ */
+em_status_t em_eo_remove_queue(em_eo_t eo, em_queue_t queue, int num_notif, const em_notif_t* notif_tbl);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Register EO specific error handler.
+ *
+ * The EO specific error handler is called if error is noticed or em_error() is 
+ * called in the context of the EO. Note, the function will override any previously 
+ * registered error hanler.
+ *
+ * @param eo            EO id
+ * @param handler       New error handler.
+ *
+ * @return EM_OK if successful.
+ *
+ * @see em_register_error_handler(), em_error_handler_t()
+ */
+em_status_t em_eo_register_error_handler(em_eo_t eo, em_error_handler_t handler);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Unregister EO specific error handler.
+ *
+ * Removes previously registered EO specific error handler.
+ *
+ * @param eo            EO id
+ *
+ * @return EM_OK if successful.
+ */
+em_status_t em_eo_unregister_error_handler(em_eo_t eo);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Start Execution Object (EO).
+ *
+ * Calls global EO start function. If that returns EM_OK,
+ * an internal event to trigger local start is sent to all cores belonging to
+ * the queue group of this EO.
+ * If the global start function does not return EM_OK the local start is
+ * not called and event dispatching is not enabled for this EO.
+ *
+ * If the caller needs to know when the EO start was actually completed
+ * on all cores, the num_notif and notif_tbl can be used. The given
+ * notification event(s) will be sent to given queue(s), when the
+ * start is completed on all cores.
+ * If local start does not exist the notification(s) are sent as the global
+ * start returns.
+ * If such notification is not needed, use 0 as num_notif.
+ *
+ * @param eo            EO id
+ * @param result        Optional pointer to em_status_t, which gets updated to the
+ *                      return value of the actual EO global start function
+ *
+ * @param num_notif     If not 0, defines the number of events to send as all cores
+ *                      have returned from the start function (in notif_tbl).
+ *
+ * @param notif_tbl     Array of em_notif_t, the optional notification events (data copied)
+ *
+ * @return EM_OK if successful.
+ *
+ * @see em_start_func_t(), em_start_local_func_t(), em_eo_stop()
+ *
+ * @todo Way to read core local start value or status?
+ */
+em_status_t em_eo_start(em_eo_t eo, em_status_t *result, int num_notif, const em_notif_t* notif_tbl);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Stop Execution Object (EO).
+ *
+ * Disables event dispatch from all related queues, calls core local stop
+ * on all cores and finally calls the global stop function of the EO,
+ * when all cores have returned from the (optional) core local stop.
+ * Call to the global EO stop is asynchronous and only done, when all cores
+ * have completed processing of the receive function and/or core local stop.
+ * This guarantees no core is accessing EO data during EO global stop function.
+ *
+ * This function returns immediately.
+ *
+ * If the caller needs to know when the EO stop was actually completed,
+ * the num_notif and notif_tbl can be used. The given notification event(s)
+ * will be sent to given queue(s), when the stop actually completes.
+ * If such notification is not needed, use 0 as num_notif.
+ *
+ * @param eo            EO id
+ * @param num_notif     How many notification events given, 0 for no notification
+ * @param notif_tbl     Array of pairs of event and queue identifiers
+ *
+ * @return EM_OK if successful.
+ *
+ * @see em_stop_func_t(), em_stop_local_func_t(), em_eo_start()
+ *
+ * @todo Method for the application to get the final stop status
+ */
+em_status_t em_eo_stop(em_eo_t eo, int num_notif, const em_notif_t* notif_tbl);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Logical core id.
+ *
+ * Returns the logical id of the current core.
+ * EM enumerates cores (or HW threads) to always start from 0 and be contiguous,
+ * i.e. valid core identifiers are 0...em_core_count()-1
+ *
+ * @return Current logical core id
+ *
+ * @see em_core_count()
+ */
+int em_core_id(void);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * The number of cores running within the same EM instance (sharing the EM state).
+ *
+ * @return Number of EM cores (or HW threads)
+ *
+ * @see em_core_id()
+ *
+ * @todo CPU hot plugging support
+ */
+int em_core_count(void);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Allocate an event.
+ *
+ * Memory address of the allocated event is system specific and
+ * can depend on given pool id, event size and type. Returned 
+ * event (handle) may refer to a memory buffer or a HW specific 
+ * descriptor, i.e. the event structure is system specific. 
+ *
+ * Use em_event_pointer() to convert an event (handle) to a pointer to 
+ * the event structure. 
+ *
+ * EM_EVENT_TYPE_SW with minor type 0 is reserved for direct portability.
+ * It is always guaranteed to return a 64-bit aligned contiguous 
+ * data buffer, that can directly be used by the application up to
+ * the given size (no HW specific descriptors etc are visible).
+ *
+ * EM_POOL_DEFAULT can be used as pool id if there's no need to 
+ * use any specific memory pool.
+ *
+ * Additionally it is guaranteed, that two separate buffers
+ * never share a cache line to avoid false sharing.
+ *
+ * @param size          Event size in octets
+ * @param type          Event type to allocate
+ * @param pool_id       Event pool id 
+ *
+ * @return the allocated event or EM_EVENT_UNDEF on an error
+ *
+ * @see em_free(), em_send(), em_event_pointer(), em_receive_func_t()
+ */
+em_event_t em_alloc(size_t size, em_event_type_t type, em_pool_id_t pool_id);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Free an event.
+ *
+ * It is assumed the implementation can detect from which
+ * memory area/pool the event was originally allocated from.
+ *
+ * Free transfers the ownership of the event to the system and
+ * application must not touch the event (or related memory buffers)
+ * after calling it.
+ *
+ * Application must only free events it owns. For example, sender must
+ * not free an event after sending it. 
+ * 
+ * @param event         Event to be freed
+ *
+ * @see em_alloc(), em_receive_func_t()
+ *
+ * @todo OK or not to free EM_EVENT_UNDEF?
+ */
+void em_free(em_event_t event); 
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Send an event to a queue.
+ *
+ * Event must have been allocated with em_alloc(), or
+ * received via receive-function. Sender must not touch the
+ * event after calling em_send as the ownership is moved to system
+ * and then to the receiver. If return status is *not* EM_OK, the ownership
+ * has not moved and the application is still responsible for the event (e.g. 
+ * may free it).
+ *
+ * EM does not define guaranteed event delivery, i.e. EM_OK return value only
+ * means the event was accepted for delivery. It could still be lost during
+ * the delivery (e.g. due to disabled/removed queue, queue or system 
+ * congestion, etc).
+ *
+ * @param event         Event to be sent
+ * @param queue         Destination queue
+ *
+ * @return EM_OK if successful (accepted for delivery).
+ * 
+ * @see em_alloc()
+ */
+em_status_t em_send(em_event_t event, em_queue_t queue) ;
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Get pointer to event structure
+ *
+ * Returns pointer to the event structure or NULL. Event structure is
+ * implementation and event type specific. It may be a directly 
+ * accessible buffer of memory, a descriptor containing a list of 
+ * buffer pointers, a descriptor of a packet buffer, etc.
+ *
+ * @param event         Event from receive/alloc
+ *
+ * @return              Event pointer or NULL
+ * 
+ */
+void* em_event_pointer(const em_event_t event);
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Release atomic processing context.
+ *
+ * When an event was received from an atomic queue, the function can be used to 
+ * release the atomic context before receive function return. After the call,
+ * scheduler is allowed to schedule another event from the same queue
+ * to another core. This increases parallelism and may improve performance - 
+ * however the exclusive processing and ordering (!) might be lost after the call.
+ *
+ * Can only be called from within the event receive function!
+ *
+ * The call is ignored, if current event was not received from an atomic queue.
+ *
+ * Pseudo-code example:
+ * @code
+ *  receive_func(void* eo_ctx, em_event_t event, em_event_type_t type, em_queue_t queue, void* q_ctx);
+ *  {
+ *      if(is_my_atomic_queue(q_ctx))
+ *      {
+ *          update_sequence_number(event);  // this needs to be done atomically
+ *          em_atomic_processing_end();
+ *          ...                             // do other processing (potentially) in parallel
+ *      }
+ *   }
+ * @endcode
+ *
+ * @see em_receive_func_t()
+ */
+void em_atomic_processing_end(void);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Register the global error handler.
+ *
+ * The global error handler is called on errors (or em_error() calls)  
+ * outside of any EO context or if there's no EO specific error 
+ * handler registered. Note, the function will override any previously 
+ * registered global error handler.
+ *
+ * @param handler       Error handler.
+ *
+ * @return EM_OK if successful.
+ *
+ * @see em_eo_register_error_handler(), em_unregister_error_handler(), em_error_handler_t()
+ */
+em_status_t em_register_error_handler(em_error_handler_t handler);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Unregister the global error handler.
+ *
+ * Removes previously registered global error handler.
+ *
+ * @return EM_OK if successful.
+ *
+ * @see em_register_error_handler()
+ */
+em_status_t em_unregister_error_handler(void);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Report an error.
+ *
+ * Reported errors are handled by the appropriate (EO specific or the global) error handler.
+ *
+ * Depending on the error/scope/implementation, the function call may not return.
+ * 
+ * @param error         Error code
+ * @param escope        Error scope. Identifies the scope for interpreting the error code and variable arguments.
+ * @param ...           Variable number and type of arguments
+ * 
+ * @see em_register_error_handler(), em_error_handler_t()
+ */
+void em_error(em_status_t error, em_escope_t escope, ...);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* EVENT_MACHINE_FUNCTIONS_H */
+
+
diff --git a/platform/linux-keystone2/prebuilts/openem/include/event_machine_group.h b/platform/linux-keystone2/prebuilts/openem/include/event_machine_group.h
new file mode 100644
index 0000000..79796f3
--- /dev/null
+++ b/platform/linux-keystone2/prebuilts/openem/include/event_machine_group.h
@@ -0,0 +1,292 @@
+/*
+ *   Copyright (c) 2012, Nokia Siemens Networks
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *       * Redistributions of source code must retain the above copyright
+ *         notice, this list of conditions and the following disclaimer.
+ *       * Redistributions in binary form must reproduce the above copyright
+ *         notice, this list of conditions and the following disclaimer in the
+ *         documentation and/or other materials provided with the distribution.
+ *       * Neither the name of Nokia Siemens Networks nor the
+ *         names of its contributors may be used to endorse or promote products
+ *         derived from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ *   WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY
+ *   DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ *   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *   ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ 
+
+/**
+ *
+ * Contributors
+ *
+ * The initial developer of the original code is Nokia Siemens Networks.
+ *  The following contributors have made changes to 
+ *  the original code as described below.
+ * 
+ *----------------------------------------------------------------------------------------------
+ * Copyright (c) 2012, Texas Instruments Incorporated. All Rights Reserved. - http://www.ti.com/
+ * 
+ * Changes were done on the original NSN header files in order to avoid 
+ * circular dependencies when called in the TI implementation files.
+ *
+ * From the original event_machine_group.h, the list of changes are:
+ *   - Doxygen tags are added for API documentation generation.
+ *   - Comments have been added for EM_EVENT_GROUP_UNDEF, PRI_EGRP.
+ *   - The included file is now event_machine_types.h 
+ *----------------------------------------------------------------------------------------------
+ *
+ */
+
+
+/**
+ * @file : event_machine_group.h
+ *
+ * @brief
+ *     Open Event Machine public event group functions
+ */
+
+/**
+ * @page DOC_intro Introduction
+ * @section section_3 Open Event Machine optional fork-join helper.
+ *
+ * An event group can be used to trigger join of parallel operations.
+ * The number of parallel operations need to be known by the event group
+ * creator, but the separate events handlers don't need to know anything
+ * about the other related events.
+ *
+ * 1. a group is created with em_event_group_create()
+ *
+ * 2. the number of parallel events is set with em_event_group_apply()
+ *
+ * 3. the parallel events are sent normally, but using em_send_group() instead
+ *    of em_send()
+ *
+ * 4. as the receive function of the last event is completed, the given notification
+ *    event(s) are sent automatically and can trigger the next operation
+ *
+ * 5. the sequence continues from step 2. for new set of events (if the group is reused)
+ *
+ * So here the original initiator only needs to know how the task is split into
+ * parallel events, the event handlers and the one continuing the work (join)
+ * are not involved (assuming the task itself can be separately processed)
+ *
+ * Note, that this only works with events targeted to an EO, i.e. SW events
+ *
+ *
+ *
+ * @todo specify exact operation to cancel an aborted fork-join
+ *       em_status_t em_event_group_cancel(em_event_group_t group, ...);
+ *
+ */
+#ifndef EVENT_MACHINE_GROUP_H
+#define EVENT_MACHINE_GROUP_H
+
+#include <inttypes.h>
+#include <event_machine_types.h>
+#include <event_machine_hw_macros.h>
+#include <event_machine_hw_types.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*
+ * Optimize EM for 64 bit architecture
+ * =====================================
+ */
+#ifdef EM_64_BIT
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Event group id. This is used for fork-join event handling.
+ *
+ * @see em_event_group_create()
+ */
+typedef uint64_t               em_event_group_t;
+
+/**
+ * @ingroup DOC_api_generic
+ * 
+ */
+#define EM_EVENT_GROUP_UNDEF   EM_UNDEF_U64      /**< Invalid event group */
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ */
+#define PRI_EGRP               PRIu64            /**< em_event_group_t printf format */
+
+
+/*
+ * Optimize EM for 32 bit architecture
+ * =====================================
+ */
+#elif defined(EM_32_BIT)
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Event group id. This is used for fork-join event handling.
+ *
+ * @see em_event_group_create()
+ */
+typedef uint32_t               em_event_group_t;
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ */
+#define EM_EVENT_GROUP_UNDEF   EM_UNDEF_U32      /**< Invalid event group id */
+
+/**
+ * @ingroup DOC_api_generic
+ * 
+ */
+#define PRI_EGRP               PRIu32            /**< em_event_group_t printf format */
+
+#else
+  #error Missing architecture definition. Define EM_64_BIT or EM_32_BIT!   
+
+   /* @page page_version 64/32 bit version not selected */
+
+  /**
+   *
+   * @page DOC_intro Introduction
+   * @section page_version 64/32 bit version not selected
+   * This is documentation has not selected between 64/32 bit version of Event Machine API.
+   * Some types might be missing. Define EM_64_BIT or EM_32_BIT to select between 64 and 32 bit versions.
+   *
+   */
+   
+#endif
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Create new event group id for fork-join.
+ *
+ * @return New event group id or EM_EVENT_GROUP_UNDEF
+ *
+ * @see em_event_group_delete(), em_event_group_apply()
+ */
+em_event_group_t em_event_group_create(void);
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Delete (unallocate) an event group id
+ *
+ * An event group must not be deleted before it has been
+ * completed (notifications sent) or canceled.
+ *
+ * @param event_group  Event group to delete
+ *
+ * @return EM_OK if successful.
+ *
+ * @see em_event_group_create()
+ */
+em_status_t em_event_group_delete(em_event_group_t event_group);
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Apply event group configuration.
+ *
+ * The function sets (or resets) the event count and notification parameters
+ * for the event group. After it returns events sent to the group are counted
+ * against the (updated) count. Notification events are sent when all (counted)
+ * events have been processed. A new apply call is needed to reset the event
+ * group (counting).
+ *
+ * @param group        Group id
+ * @param count        Number of events in the group
+ * @param num_notif    Number of noticifation events to send
+ * @param notif_tbl    Table of notifications (events and target queues)
+ *
+ * @return EM_OK if successful.
+ *
+ * @see em_event_group_create(), em_send_group()
+ */
+em_status_t em_event_group_apply(em_event_group_t group, int count, int num_notif, const em_notif_t* notif_tbl);
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Increment event group count
+ * 
+ * Increments event count of the current event group. Enables sending new events into 
+ * the current group. Must be called before sending. Note that event count cannot be decremented.
+ *
+ * @param count        Number of events to add in the group
+ *
+ * @return EM_OK if successful.
+ *
+ * @see em_send_group()
+ */
+em_status_t em_event_group_increment(int count);
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Current event group
+ *
+ * Returns the event group of the currently received event or EM_EVENT_GROUP_UNDEF 
+ * if the current event does not belong into any event group. Current group is needed 
+ * when sending new events into the group.
+ *
+ * @return Current event group id or EM_EVENT_GROUP_UNDEF
+ *
+ * @see em_event_group_create()
+ */
+em_event_group_t em_event_group_current(void);
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Send event with group number.
+ *
+ * Any valid event and destination queue parameters can be used. Event group id
+ * indicates which event group the event belongs to. Event group has to be first
+ * created and applied.
+ *
+ * @param event    Event to send
+ * @param queue    Destination queue
+ * @param group    Event group
+ *
+ * @return EM_OK if successful.
+ *
+ * @see em_send(), em_event_group_create(), em_event_group_apply(), em_event_group_increment()
+ */
+em_status_t em_send_group(em_event_t event, em_queue_t queue, em_event_group_t group);
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif
+
+
diff --git a/platform/linux-keystone2/prebuilts/openem/include/event_machine_helper.h b/platform/linux-keystone2/prebuilts/openem/include/event_machine_helper.h
new file mode 100644
index 0000000..bb40fd4
--- /dev/null
+++ b/platform/linux-keystone2/prebuilts/openem/include/event_machine_helper.h
@@ -0,0 +1,142 @@
+/*
+ *   Copyright (c) 2012, Nokia Siemens Networks
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *       * Redistributions of source code must retain the above copyright
+ *         notice, this list of conditions and the following disclaimer.
+ *       * Redistributions in binary form must reproduce the above copyright
+ *         notice, this list of conditions and the following disclaimer in the
+ *         documentation and/or other materials provided with the distribution.
+ *       * Neither the name of Nokia Siemens Networks nor the
+ *         names of its contributors may be used to endorse or promote products
+ *         derived from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ *   WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY
+ *   DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ *   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *   ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ 
+
+/**
+ *
+ * Contributors
+ *
+ * The initial developer of the original code is Nokia Siemens Networks.
+ *  The following contributors have made changes to 
+ *  the original code as described below.
+ * 
+ *----------------------------------------------------------------------------------------------
+ * Copyright (c) 2012, Texas Instruments Incorporated. All Rights Reserved. - http://www.ti.com/
+ * 
+ * Changes were done on the original NSN header files in order to avoid 
+ * circular dependencies when called in the TI implementation files.
+ *
+ * From the original event_machine_helper.h, the list of changes are:
+ *   - The included files are now event_machine_types.h, event_machine_core_mask.h and event_machine_macros.h
+ *   - em_get_type_major and em_get_type_minor implementation has been changed.
+ *   - Doxygen tags are added for API documentation generation.
+ *       - Doxygen comments were copied from the 64-BIT implementation to the 32-BIT section
+ *         since the TI implementation only support 32-BIT section.
+ *----------------------------------------------------------------------------------------------
+ *
+ */
+
+
+/**
+ * @file: event_machine_helper.h
+ *
+ * @brief
+ *    Open Event Machine helper functions and macros
+ *
+ */
+
+#ifndef EVENT_MACHINE_HELPER_H_
+#define EVENT_MACHINE_HELPER_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdlib.h>
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Format error string
+ *
+ * Creates an implementation dependent error report string from EM 
+ * internal errors.
+ *
+ * @param str       Output string pointer
+ * @param size      Maximum string lenght in characters
+ * @param eo        EO id
+ * @param error     Error code (EM internal)
+ * @param escope    Error scope (EM internal)
+ * @param args      Variable arguments
+ *
+ * @return Output string length
+ */
+int em_error_format_string(char* str, size_t size, em_eo_t eo, em_status_t error, em_escope_t escope, va_list args);
+
+
+
+
+/*
+ *
+ * Physical core ids
+ ***************************************
+ *
+ *
+ */
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Converts a logical core id to a physical core id
+ *
+ * Mainly needed when interfacing HW specific APIs
+ *
+ * @param core     logical (Event Machine) core id
+ *
+ * @return Physical core id
+ *
+ */
+int em_core_id_get_physical(int core);
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Converts a logical core mask to a physical core mask
+ *
+ * Mainly needed when interfacing HW specific APIs
+ *
+ * @param phys     Core mask of physical core ids
+ * @param logic    Core mask of logical (Event Machine) core ids
+ *
+ */
+void em_core_mask_get_physical(em_core_mask_t* phys, const em_core_mask_t* logic);
+
+
+
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* EVENT_MACHINE_HELPER_H_ */
diff --git a/platform/linux-keystone2/prebuilts/openem/include/event_machine_hw.h b/platform/linux-keystone2/prebuilts/openem/include/event_machine_hw.h
new file mode 100644
index 0000000..6c5f274
--- /dev/null
+++ b/platform/linux-keystone2/prebuilts/openem/include/event_machine_hw.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2012, Texas Instruments Incorporated - http://www.ti.com/
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *       * Redistributions of source code must retain the above copyright
+ *         notice, this list of conditions and the following disclaimer.
+ *       * Redistributions in binary form must reproduce the above copyright
+ *         notice, this list of conditions and the following disclaimer in the
+ *         documentation and/or other materials provided with the distribution.
+ *       * Neither the name of Texas Instruments Incorporated nor the
+ *         names of its contributors may be used to endorse or promote products
+ *         derived from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ *   WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY
+ *   DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ *   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *   ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/**
+ * @file: event_machine_hw.h
+ *
+ * @brief
+ *    Open Event Machine HW public include file
+ *
+ */
+
+#ifndef EVENT_MACHINE_HW_H
+#define EVENT_MACHINE_HW_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <event_machine_hw_config.h>
+#include <event_machine_hw_functions.h>
+#include <event_machine_hw_macros.h>
+#include <event_machine_hw_types.h>
+
+#include <event_machine_hw_ti.h>
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* EVENT_MACHINE_HW_H */
+
+
diff --git a/platform/linux-keystone2/prebuilts/openem/include/event_machine_hw_config.h b/platform/linux-keystone2/prebuilts/openem/include/event_machine_hw_config.h
new file mode 100644
index 0000000..d9d3e3d
--- /dev/null
+++ b/platform/linux-keystone2/prebuilts/openem/include/event_machine_hw_config.h
@@ -0,0 +1,104 @@
+/*
+ *   Copyright (c) 2012, Nokia Siemens Networks
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *       * Redistributions of source code must retain the above copyright
+ *         notice, this list of conditions and the following disclaimer.
+ *       * Redistributions in binary form must reproduce the above copyright
+ *         notice, this list of conditions and the following disclaimer in the
+ *         documentation and/or other materials provided with the distribution.
+ *       * Neither the name of Nokia Siemens Networks nor the
+ *         names of its contributors may be used to endorse or promote products
+ *         derived from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ *   WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY
+ *   DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ *   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *   ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/**
+ *
+ * Contributors
+ *
+ * The initial developer of the original code is Nokia Siemens Networks.
+ *  The following contributors have made changes to 
+ *  the original code as described below.
+ * 
+ *----------------------------------------------------------------------------------------------
+ * Copyright (c) 2012, Texas Instruments Incorporated. All Rights Reserved. - http://www.ti.com/
+ * 
+ * From the original event_machine_hw_config.h.template , openem/event_machine_hw_config.h was
+ * created with:
+ *   - Compilation symbols check
+ *----------------------------------------------------------------------------------------------
+ *
+ */
+
+
+/**
+ * @file: event_machine_hw_config.h
+ *
+ * @brief
+ *    Open Event Machine HW TI specific configuration
+ *
+ */
+
+#ifndef EVENT_MACHINE_HW_CONFIG_H
+#define EVENT_MACHINE_HW_CONFIG_H
+
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef EM_64_BIT
+  #error TI implementation only supports EM_32_BIT!
+#endif
+
+#if defined(TI_EM_C6670)
+#if defined(TI_EM_C6678)
+  #error Conflicting platform definition. Define TI_EM_C6670 or TI_EM_C6678!
+#endif
+#endif
+
+#if defined(TI_EM_C6670)
+#if defined(TI_EM_C6634)
+  #error Conflicting platform definition. Define TI_EM_C6670 or TI_EM_C6634!
+#endif
+#endif
+
+#if defined(TI_EM_C6634)
+#if defined(TI_EM_C6678)
+  #error Conflicting platform definition. Define TI_EM_C6634 or TI_EM_C6678!
+#endif
+#endif
+
+#if defined(TI_EM_C6670)
+#if defined(TI_EM_C6678)
+#if defined(TI_EM_C6634)
+  #error Missing platform definition. Define TI_EM_C6670 or TI_EM_C6678 or TI_EM_C6634!
+#endif
+#endif
+#endif
+
+#include <event_machine_sw_config.h>
+#include <event_machine_hw_macros.h>
+#include <event_machine_hw_types.h>
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif
diff --git a/platform/linux-keystone2/prebuilts/openem/include/event_machine_hw_functions.h b/platform/linux-keystone2/prebuilts/openem/include/event_machine_hw_functions.h
new file mode 100644
index 0000000..65e001f
--- /dev/null
+++ b/platform/linux-keystone2/prebuilts/openem/include/event_machine_hw_functions.h
@@ -0,0 +1,94 @@
+/*
+ *   Copyright (c) 2012, Nokia Siemens Networks
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *       * Redistributions of source code must retain the above copyright
+ *         notice, this list of conditions and the following disclaimer.
+ *       * Redistributions in binary form must reproduce the above copyright
+ *         notice, this list of conditions and the following disclaimer in the
+ *         documentation and/or other materials provided with the distribution.
+ *       * Neither the name of Nokia Siemens Networks nor the
+ *         names of its contributors may be used to endorse or promote products
+ *         derived from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ *   WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY
+ *   DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ *   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *   ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/**
+ *
+ * Contributors
+ *
+ * The initial developer of the original code is Nokia Siemens Networks.
+ *  The following contributors have made changes to 
+ *  the original code as described below.
+ * 
+ *----------------------------------------------------------------------------------------------
+ * Copyright (c) 2012, Texas Instruments Incorporated. All Rights Reserved. - http://www.ti.com/
+ * 
+ * From the original event_machine_hw_config.h.template , openem/event_machine_hw_functions.h was
+ * created with:
+ *   - A modified returned value for em_get_type_minor() function 
+ *   - Doxygen tags are added for API documentation generation.
+ *----------------------------------------------------------------------------------------------
+ *
+ */
+
+
+/**
+ * @file: event_machine_hw_functions.h
+ *
+ * @brief
+ *    Open Event Machine HW functions declarations
+ *
+ */
+
+#ifndef EVENT_MACHINE_HW_FUNCTIONS_H_
+#define EVENT_MACHINE_HW_FUNCTIONS_H_
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Get major event type.
+ * 
+ * Event type includes major and minor part. This function
+ * returns the major part. It can be compared against 
+ * enumeration em_event_type_major_e.
+ * 
+ * @param type          Event type
+ *
+ * @return Major event type
+ */
+em_event_type_t em_get_type_major(em_event_type_t type);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Get minor event type.
+ * 
+ * Event type includes major and minor part. This function
+ * returns the minor part. It can be compared against 
+ * the enumeration specified by the major part.
+ * 
+ * EM_EVENT_TYPE_SW_DEFAULT is reserved for (SW) events that are
+ * generic and directly accessible buffers of memory. 
+ * 
+ * @param type          Event type
+ *
+ * @return Minor event type
+ */
+em_event_type_t em_get_type_minor(em_event_type_t type);
+
+#endif /* EVENT_MACHINE_HW_FUNCTIONS_H_ */
+
diff --git a/platform/linux-keystone2/prebuilts/openem/include/event_machine_hw_macros.h b/platform/linux-keystone2/prebuilts/openem/include/event_machine_hw_macros.h
new file mode 100644
index 0000000..39d4467
--- /dev/null
+++ b/platform/linux-keystone2/prebuilts/openem/include/event_machine_hw_macros.h
@@ -0,0 +1,212 @@
+/*
+ *   Copyright (c) 2012, Nokia Siemens Networks
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *       * Redistributions of source code must retain the above copyright
+ *         notice, this list of conditions and the following disclaimer.
+ *       * Redistributions in binary form must reproduce the above copyright
+ *         notice, this list of conditions and the following disclaimer in the
+ *         documentation and/or other materials provided with the distribution.
+ *       * Neither the name of Nokia Siemens Networks nor the
+ *         names of its contributors may be used to endorse or promote products
+ *         derived from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ *   WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY
+ *   DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ *   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *   ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/**
+ *
+ * Contributors
+ *
+ * The initial developer of the original code is Nokia Siemens Networks.
+ *  The following contributors have made changes to 
+ *  the original code as described below.
+ * 
+ *----------------------------------------------------------------------------------------------
+ * Copyright (c) 2012, Texas Instruments Incorporated. All Rights Reserved. - http://www.ti.com/
+ * 
+ * From the original event_machine_hw_config.h.template , openem/event_machine_hw_macros.h was
+ * created with:
+ *   - Static HW macro definitions with the TI optimized implementation values
+ *   - Doxygen tags are added for API documentation generation.
+ *----------------------------------------------------------------------------------------------
+ *
+ */
+
+
+/**
+ * @file: event_machine_hw_macros.h
+ *
+ * @brief
+ *    Open Event Machine HW TI specific macros
+ *
+ */
+
+#ifndef EVENT_MACHINE_HW_MACROS_H
+#define EVENT_MACHINE_HW_MACROS_H
+
+#include <event_machine_hw_ti_macros.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ *
+ * HW specific constants
+ ***************************************
+ */
+
+
+/** 
+ * @ingroup DOC_api_generic
+ *
+ * Invalid identifier (64-bit)
+ *
+ */
+#define EM_UNDEF_U64       (0x0000000000000000u)
+
+/** 
+ * @ingroup DOC_api_generic
+ *
+ * Invalid identifier (32-bit)
+ */
+#define EM_UNDEF_U32       (0x00000000u)
+
+/** 
+ * @ingroup DOC_api_generic
+ *
+ * Invalid identifier (16-bit)
+ */
+#define EM_UNDEF_U16       (0x0000u)
+
+/** 
+ * @ingroup DOC_api_generic
+ *
+ * Invalid identifier (8-bit)
+ */
+#define EM_UNDEF_U8        (0x00u)
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Undefined event
+ */
+#define EM_EVENT_UNDEF     (0x00000000u)
+
+/**
+ * @ingroup DOC_api_generic
+ * 
+ * Default queue group for EM
+ */
+#define EM_QUEUE_GROUP_DEFAULT    (1u)
+
+/**
+ * @ingroup DOC_api_generic
+ * 
+ * Maximum number of queue groups supported by the event machine.
+ *
+ * @note This value can be modified by an application. But the event machine library needs to be recompiled.
+ *
+ */
+#define EM_MAX_QUEUE_GROUPS       (16u)
+
+/**
+ * @ingroup DOC_api_generic
+ * 
+ * Define default memory pool
+ */
+#define EM_POOL_DEFAULT           (0u)
+
+/**
+ * @ingroup DOC_api_generic
+ * 
+ * Fatal error mask
+ */
+#define EM_ERROR_FATAL_MASK       (0x80000000u)
+
+/**
+ * @ingroup DOC_api_generic
+ * 
+ * Test if error is fatal
+ */
+#define EM_ERROR_IS_FATAL(error)  (EM_ERROR_FATAL_MASK & (error))
+
+/**
+ * @ingroup DOC_api_generic
+ * 
+ * Set a fatal error code
+ */
+#define EM_ERROR_SET_FATAL(error) (EM_ERROR_FATAL_MASK | (error))
+
+/**
+ * @ingroup DOC_api_generic
+ * 
+ * EM internal error scope mask
+ */
+#define EM_ESCOPE_INTERNAL_TYPE       (0x00u)
+
+/**
+ * @ingroup DOC_api_generic
+ * 
+ * EM internal error scope type
+ */
+#define EM_ESCOPE_INTERNAL_MASK             (EM_ESCOPE_BIT | (EM_ESCOPE_INTERNAL_TYPE << 24))
+
+/**
+ * @ingroup DOC_api_generic
+ * 
+ * Test if the error scope identifies an EM Internal function
+ */
+#define EM_ESCOPE_INTERNAL(escope) (((escope) & EM_ESCOPE_MASK) == EM_ESCOPE_INTERNAL_MASK)
+
+/*
+ *
+ * EM scaling
+ ***************************************
+ */
+
+
+
+/**
+ * @ingroup DOC_api_generic
+ * 
+ * Static queues: minimal value
+ *
+ */
+#define EM_QUEUE_STATIC_MIN         (1)
+/**
+ * @ingroup DOC_api_generic
+ * 
+ * Static queues: maximal value
+ *
+ */
+#define EM_QUEUE_STATIC_MAX         ((TI_EM_QUEUE_SET_NUM * TI_EM_STATIC_QUEUE_NUM_IN_SET) - 1)
+/**
+ * @ingroup DOC_api_generic
+ * 
+ * Static queues: number of status queues
+ *
+ */
+#define EM_QUEUE_STATIC_NUM         (EM_QUEUE_STATIC_MAX - EM_QUEUE_STATIC_MIN + 1)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif
+
diff --git a/platform/linux-keystone2/prebuilts/openem/include/event_machine_hw_ti.h b/platform/linux-keystone2/prebuilts/openem/include/event_machine_hw_ti.h
new file mode 100644
index 0000000..6ec0242
--- /dev/null
+++ b/platform/linux-keystone2/prebuilts/openem/include/event_machine_hw_ti.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2012, Texas Instruments Incorporated - http://www.ti.com/
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *       * Redistributions of source code must retain the above copyright
+ *         notice, this list of conditions and the following disclaimer.
+ *       * Redistributions in binary form must reproduce the above copyright
+ *         notice, this list of conditions and the following disclaimer in the
+ *         documentation and/or other materials provided with the distribution.
+ *       * Neither the name of Texas Instruments Incorporated nor the
+ *         names of its contributors may be used to endorse or promote products
+ *         derived from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ *   WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY
+ *   DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ *   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *   ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/**
+ * @file: event_machine_hw_ti.h
+ *
+ * @brief
+ *    Open Event Machine HW TI specific public include file
+ *
+ */
+ 
+#ifndef EVENT_MACHINE_HW_TI_H
+#define EVENT_MACHINE_HW_TI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <event_machine_hw_ti_types.h>
+#include <event_machine_hw_ti_macros.h>
+#include <event_machine_hw_ti_functions.h>
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* EVENT_MACHINE_HW_TI_H */
+
+
diff --git a/platform/linux-keystone2/prebuilts/openem/include/event_machine_hw_ti_functions.h b/platform/linux-keystone2/prebuilts/openem/include/event_machine_hw_ti_functions.h
new file mode 100644
index 0000000..9537033
--- /dev/null
+++ b/platform/linux-keystone2/prebuilts/openem/include/event_machine_hw_ti_functions.h
@@ -0,0 +1,1467 @@
+/*
+ * Copyright (c) 2012, Texas Instruments Incorporated - http://www.ti.com/
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *       * Redistributions of source code must retain the above copyright
+ *         notice, this list of conditions and the following disclaimer.
+ *       * Redistributions in binary form must reproduce the above copyright
+ *         notice, this list of conditions and the following disclaimer in the
+ *         documentation and/or other materials provided with the distribution.
+ *       * Neither the name of Texas Instruments Incorporated nor the
+ *         names of its contributors may be used to endorse or promote products
+ *         derived from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ *   WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY
+ *   DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ *   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *   ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/**
+ * @file: event_machine_hw_ti_functions.h
+ *
+ * @brief
+ *    Open Event Machine HW TI specific functions declarations
+ *
+ */
+
+#ifndef EVENT_MACHINE_HW_TI_FUNCTIONS_H_
+#define EVENT_MACHINE_HW_TI_FUNCTIONS_H_
+
+#include <event_machine_group.h>
+#include <event_machine_hw_ti_types.h>
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Returns the buffer size.
+ *
+ * Returns the size of the event attached data buffer.
+ *
+ * @param event         Event handle.
+ *
+ * @return              Size of the attached buffer.
+ *
+ */
+size_t ti_em_buffer_size(em_event_t event);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Returns the event payload size.
+ *
+ * Returns the size of the event attached data buffers.
+ *
+ * @param event         Event handle.
+ *
+ * @return              Size of the attached buffers.
+ *
+ */
+size_t ti_em_event_size(em_event_t event);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Indicates that the scheduler can pre-schedule events to this core.
+ *
+ */
+void ti_em_preschedule(void);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Indicates that the atomic processing locality has been achieved by the scheduler.
+ *
+ * @return              Hint if the atomic processing locality has been achieved.
+ *
+ */
+uint32_t ti_em_atomic_processing_locality(void);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * The function returns the needed size for the dispatcher control block in bytes. It is stored in the .tiEmLobal memory section.
+ *
+ * @return    size for the Dispatcher Control Block structure
+ */
+size_t ti_em_get_tcb_size (void);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * The function returns the needed size for the master control block plus the runtime master control block in bytes. It is stored in the .tiEmGlobalFast memory section.
+ *
+ * @return    size for the Master Control Block structure
+ */
+size_t ti_em_get_pcb_size (void);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * The function returns the needed size for the slow part of the EO descriptor in bytes. It is stored in the .tiEmGlobalSlow memory section preferably located in non cached MSMC RAM or DDR3 RAM.
+ *
+ * @return    size for the slow part of a EO structure
+ */
+size_t ti_em_get_eo_size_slow (void);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * The function returns the needed size for the fast part of the EO descriptor in bytes. It is stored in the .tiEmGlobalFast memory section preferably located in non cached MSMC RAM or DDR3 RAM.
+ *
+ * @return    size for the fast part of a EO structure
+ */
+size_t ti_em_get_eo_size_fast (void);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * The function returns the needed size for the slow part of the event group descriptor in bytes. It is stored in the .tiEmGlobalSlow memory section preferably located in non cached MSMC RAM or DDR3 RAM.
+ *
+ * @return    size for the slow part of a event group structure
+ *
+ */
+size_t ti_em_get_event_group_size_slow (void);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * The function returns the needed size for the fast part of the event group descriptor in bytes. It is stored in the .tiEmGlobalFast memory section preferably located in non cached MSMC RAM or DDR3 RAM.
+ *
+ * @return    size for the fast part of a event group structure
+ *
+ */
+size_t ti_em_get_event_group_size_fast (void);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * The function returns the needed size for the slow part of the queue group descriptor in bytes. It is stored in the .tiEmGlobalSlow memory section preferably located in non cached MSMC RAM or DDR3 RAM. 
+ *
+ * @return    size for the slow part of a queue group structure
+ *
+ */
+size_t ti_em_get_queue_group_size_slow (void);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * The function returns the needed size for the fast part of the queue group descriptor in bytes. It is stored in the .tiEmGlobalFast memory section preferably located in non cached MSMC RAM or DDR3 RAM. 
+ *
+ * @return    size for the fast part of a queue group structure
+ *
+ */
+size_t ti_em_get_queue_group_size_fast (void);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * The function returns the needed size for the slow part of the queue descriptor in bytes. It is stored in the .tiEmGlobalSlow memory section preferably located in non cached MSMC RAM or DDR3 RAM.
+ *
+ * @return    size for the slow part of a queue structure
+ *
+ */
+size_t ti_em_get_queue_size_slow (void);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * The function returns the needed size for the fast part of the queue descriptor in bytes. It is stored in the .tiEmGlobalFast memory section preferably located in non cached MSMC RAM or DDR3 RAM.
+ *
+ * @return    size for the fast part of a queue structure
+ *
+ */
+size_t ti_em_get_queue_size_fast (void);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Global initialization of EM internals.
+ *
+ * Only one core does this and this must be called before any other call.
+ *
+ * @param config_ptr   Pointer to the hardware configuration structure.
+ *
+ * @return status, EM_OK on success
+ */
+em_status_t ti_em_init_global(const ti_em_config_t* config_ptr);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Local initialization of EM internals.
+ *
+ * All cores call this and it must be called after em_init_global(), but before any other call.
+ * Implementation may be actually empty, but this might be needed later for some
+ * core specific initializations, so application startup should call this always.
+ *
+ * @return status, EM_OK on success
+ */
+em_status_t ti_em_init_local(void);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Global shutdown of EM internals.
+ *
+ * Only one core does this and after this call, no other call is allowed.
+ *
+ * @return status, EM_OK on success
+ */
+em_status_t ti_em_exit_global (void);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * The function runs the dispatcher once.
+ *
+ * The dispatcher code is responsible for calling a execution object receive API.
+ * It checks once if a event has been scheduled to its core and calls the receive function.
+ *
+ * @return returns EM_ERR_NOT_FOUND if no receive function was executed.
+ *         returns EM_OK when a public event was executed.
+ */
+em_status_t ti_em_dispatch_once (void);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * The function returns the local event buffer pointer for a local event or 
+ * NULL if there is no local event.
+ *
+ * @return        Pointer to the event buffer.
+ *
+ */
+void* ti_em_claim_local (void);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Allocate a local event (for post-storing feature).
+ *
+ * Memory address of the allocated event is system specific and
+ * can depend on given pool id, event size and type. Returned 
+ * event (handle) may refer to a memory buffer or a HW specific 
+ * descriptor, i.e. the event structure is system specific. 
+ *
+ * Use em_event_pointer() to convert an event (handle) to a pointer to 
+ * the event structure. 
+ *
+ * EM_EVENT_TYPE_SW with minor type 0 is reserved for direct portability.
+ * It is always guaranteed to return a 64-bit aligned contiguous 
+ * data buffer, that can directly be used by the application up to
+ * the given size (no HW specific descriptors etc are visible).
+ *
+ * @param size          Event size in octets
+ * @param type          Event type to allocate
+ *
+ * @return the allocated event or EM_EVENT_UNDEF on an error
+ *
+ * @see em_free(), em_send(), em_event_pointer(), em_receive_func_t()
+ */
+em_event_t ti_em_alloc_local(size_t size, em_event_type_t type);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Helper function that converts an event handle into a packet.
+ *
+ * @param    event    Event handle.
+ *
+ * @return            Pointer to the packet.
+ *
+ */
+ti_em_packet_t* ti_em_to_packet(em_event_t event);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Helper function that converts into an event handle from a packet.
+ *
+ * @param    packet_ptr      Pointer to the packet.
+ *
+ * @return                   Event handle.
+ *
+ */
+em_event_t ti_em_from_packet(ti_em_packet_t* packet_ptr);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Helper function which sets the 12 first words of an event to their default values.
+ *
+ * The CPPI type is set to Host, The EPIB flag is ON and the PS location flag is ON.
+ *
+ * @param packet_ptr      Pointer to the packet.
+ *
+ */
+void ti_em_packet_set_default(ti_em_packet_t* packet_ptr);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Helper function which sets the event pool information in the packet.
+ *
+ * @param packet_ptr    Pointer to the packet.
+ * @param pool_config   Structure containing the pool info.
+ *
+ */
+void ti_em_packet_set_pool_info(ti_em_packet_t* packet_ptr, ti_em_pool_config_t pool_config);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Helper function which sets the buffer information in the packet.
+ *
+ * @param packet_ptr    Pointer to the packet.
+ * @param buffer_config Structure containing the buffer info.
+ *
+ */
+void ti_em_packet_set_buffer_info(ti_em_packet_t* packet_ptr, ti_em_buffer_config_t buffer_config);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Helper function which restores the free information in the packet.
+ *
+ * @param packet_ptr     Pointer to the packet.
+ *
+ */
+void ti_em_packet_restore_free_info(ti_em_packet_t * packet_ptr);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Helper function which sets the event type in the packet.
+ *
+ * @param     packet_ptr    Pointer to the packet.
+ * @param     event_type    Event type of the packet.
+ *
+ */
+void ti_em_packet_set_type(ti_em_packet_t* packet_ptr, em_event_type_t event_type);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Helper function which sets the queue information in the packet.
+ *
+ * @param packet_ptr    Pointer to the packet.
+ * @param queue_hdl     Queue handle to set.
+ *
+ */
+void ti_em_packet_set_queue(ti_em_packet_t* packet_ptr, em_queue_t queue_hdl);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Helper function which sets the event group information in the packet.
+ *
+ * @param packet_ptr         Pointer to the packet.
+ * @param event_group_hdl    Event group handle to set.
+ *
+ */
+void ti_em_packet_set_event_group(ti_em_packet_t* packet_ptr, em_event_group_t event_group_hdl);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Helper function which sets the event type in the event.
+ *
+ * @param event         Event handle.
+ * @param event_type    Event type to set.
+ *
+ */
+void ti_em_set_type(em_event_t event, em_event_type_t event_type);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Helper function which returns the event type.
+ *
+ * @param     event    Event handle.
+ *
+ * @return             Event type of the descriptor.
+ *
+ */
+em_event_type_t ti_em_get_type(const em_event_t event);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Helper function which extracts the preload policy from the event type.
+ *
+ * @param     type     Event type.
+ *
+ * @return             Preload policy.
+ *
+ */
+em_event_type_t ti_em_get_type_preload(em_event_type_t type);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Helper function which returns the buffer mode.
+ *
+ * @param     event    Event handle.
+ *
+ * @return             Buffer mode of the event.
+ *
+ */
+ti_em_buf_mode_t ti_em_get_buf_mode(const em_event_t event);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Helper function which returns the cache coherency mode.
+ *
+ * @param     event    Event handle.
+ *
+ * @return             Cache coherency mode of the event.
+ *
+ */
+ti_em_coh_mode_t ti_em_get_coh_mode(const em_event_t event);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Helper function which sets the queue and event group information in the event.
+ *
+ * @param event              Event handle.
+ * @param queue_hdl          Queue handle to set.
+ * @param event_group_hdl    Event group handle to set.
+ *
+ */
+void ti_em_set_queue(em_event_t event, em_queue_t queue_hdl, em_event_group_t event_group_hdl);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Helper function which sets the queue information in the event tag location.
+ *
+ * @param tag_ptr            Pointer to tag location.
+ * @param queue_hdl          Queue handle to set.
+ *
+ */
+void ti_em_tag_set_queue(uint32_t* tag_ptr, em_queue_t queue_hdl);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Helper function which sets the event type in the tag location.
+ *
+ * @param tag_ptr            Pointer to tag location.
+ * @param event_type         Event type to set.
+ *
+ */
+void ti_em_tag_set_type(uint32_t* tag_ptr, em_event_type_t event_type);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Helper function which generates a global queue handle.
+ *
+ * @param     queue_hdl     Local queue handle.
+ * @param     device_idx    Device index.
+ * @param     process_idx   Process index.
+ *
+ * @return                  Global queue handle.
+ *
+ */
+em_queue_t ti_em_queue_make_global(em_queue_t queue_hdl, ti_em_device_id_t device_idx, ti_em_process_id_t process_idx);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Helper function which extracts the device index from the queue handle.
+ *
+ * @param     queue_hdl     Queue handle.
+ *
+ * @return                  Device index.
+ *
+ */
+ti_em_device_id_t ti_em_queue_get_device_id(em_queue_t queue_hdl);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Helper function which extracts the process index from the queue handle.
+ *
+ * @param     queue_hdl     Queue handle.
+ *
+ * @return                  Process index.
+ *
+ */
+ti_em_process_id_t ti_em_queue_get_process_id(em_queue_t queue_hdl);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Helper function which extracts the queue mode (HW or SD) from the queue handle.
+ *
+ * @param     queue_hdl     Queue handle.
+ *
+ * @return                  Queue mode.
+ *
+ */
+ti_em_queue_mode_t ti_em_queue_get_mode(em_queue_t queue_hdl);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Helper function which returns the index of the associated Multicore Navigator queue.
+ *
+ * @param     queue_hdl     Queue handle.
+ *
+ * @return                  Device index.
+ *
+ */
+ti_em_queue_id_t ti_em_queue_get_queue_id(em_queue_t queue_hdl);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Registers the trace handler.
+ *
+ * @param handler   Trace handler.
+ *
+ * @return Success code.
+ */
+em_status_t ti_em_register_trace_handler(ti_em_trace_handler_t handler);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Unregisters the trace handler.
+ *
+ * @return Success code is 0,
+ */
+em_status_t ti_em_unregister_trace_handler(void);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Allocates an event while providing buffer(s) to attach.
+ *
+ * It allocates a primary event from pools with zero-buffer descriptors.\n
+ * It attaches one or more buffers to the event.\n
+ * The event comes with optional free function and coherency mode for each buffer.
+ *
+ * @param event_type         Event type to allocate
+ * @param pool_id            Event pool id
+ * @param buffer_num         Event buffers number
+ * @param buffer_config_tbl  Data buffers configuration table
+ *
+ * @return                   Event handle
+ *
+ * @see ti_em_free_with_buffers()
+ *
+ */
+em_event_t ti_em_alloc_with_buffers(em_event_type_t event_type, em_pool_id_t pool_id, int32_t buffer_num, ti_em_buffer_config_t* buffer_config_tbl);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Frees an event with buffers.
+ *
+ * It returns an event to its free pool(s).\n
+ * It doesn't call free function, even if provided.\n
+ * It fills out the configuration for each buffer that has been attached with ti_em_alloc_with_buffers().\n
+ * It returns the number of such buffers - error if too many buffer pointers to return (wrt to buffer_num).\n
+ *
+ * @param event              Event to be freed
+ * @param buffer_num         Event buffers number
+ * @param buffer_config_tbl  Data buffers configuration table
+ *
+ * @return                   Event handle.
+ *
+ * @see ti_em_alloc_with_buffers()
+ *
+ */
+em_event_t ti_em_free_with_buffers(em_event_t event, int32_t buffer_num, ti_em_buffer_config_t* buffer_config_tbl);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Combines two (2) event handles into one scattered event handle.\n
+ * When returned, the iterator buffer points to last descriptor of the old pair.head_event.\n
+ *
+ * @param          event_pair   pair to combine.
+ *
+ * @param          iterator_ptr Pointer to iterator.
+ *
+ * @return         event handle.
+ */
+em_event_t ti_em_combine(ti_em_pair_t event_pair, ti_em_iterator_t * iterator_ptr);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Splits one scattered event into two events.\n
+ * when returned, the iterator buffer points to the last buffer of pair.head_event (can be recombined right away).\n
+ * Second and following buffers of pair.tail_event are cache coherent.\n
+ *
+ * @param   event           Event to split.
+ * @param   iterator_ptr    Pointer to iterator where the split starts.
+ *
+ * @return                  Events pair.
+ */
+ti_em_pair_t ti_em_split(em_event_t event, ti_em_iterator_t* iterator_ptr);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Returns the size of the iterator attached data buffer.
+ *
+ * @param iterator_ptr      Pointer to iterator.
+ *
+ * @return                  Size of the attached buffer.
+ *
+ */
+size_t ti_em_iterator_size(ti_em_iterator_t* iterator_ptr);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Initializes the iterator to the first buffer. Two iterators may not be started at the same time for a single event.
+ *
+ * @param event             Event handle to start.
+ * @param iterator_ptr      Pointer to iterator.
+ *
+ * @return                  returns EM_OK.
+ *
+ */
+em_status_t ti_em_iterator_start(em_event_t event, ti_em_iterator_t* iterator_ptr);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * It registers all the touched buffers.\n
+ * It is mandatory to perform ti_em_iterator_stop() before em_free(), em_send() or em_event_group_apply().\n
+ * It is forbidden to use the iterator or any iterator content from this point onwards.
+ *
+ * @param iterator_ptr      Pointer to iterator.
+ *
+ * @return                  returns EM_OK when successfull, EM_ERR_BAD_STATE when iterator is in a wrong state.
+ *
+ */
+em_status_t ti_em_iterator_stop(ti_em_iterator_t* iterator_ptr);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Moves the iterator to the next buffer.
+ *
+ * @param iterator_ptr      Pointer to iterator.
+ *
+ * @return                  returns EM_OK when successfull, EM_ERR_BAD_STATE when iterator is in a wrong state. EM_ERR_NOT_FOUND when the iterator points to the last buffer.
+ *
+ */
+em_status_t ti_em_iterator_next(ti_em_iterator_t* iterator_ptr);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Moves the iterator to the previous buffer.
+ *
+ * @param iterator_ptr      Pointer to iterator.
+ *
+ * @return                  returns EM_OK when successfull, EM_ERR_BAD_STATE when iterator is in a wrong state. EM_ERR_NOT_FOUND when the iterator points to the first buffer.
+ *
+ */
+em_status_t ti_em_iterator_previous(ti_em_iterator_t* iterator_ptr);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Returns a pointer to the iterator attached data buffer.
+ *
+ * @param iterator_ptr      Pointer to iterator.
+ *
+ * @return                  Pointer to the buffer.
+ *
+ */
+void* ti_em_iterator_pointer(ti_em_iterator_t* iterator_ptr);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Opens an hard-ware queue on the data-base.
+ *
+ * @pre   The hard-ware queue shall not be used by another
+ *        part of the application on the device.\n
+ *        If the hard-ware queue is already used, the function
+ *        is not successful.
+ *
+ * @remark The implementation is left to the user. An
+ *         example is provided in em_pdk_hal.c file
+ *         using the Qmss_queueOpen PDK function.
+ *
+ * @param queue_idx   Index of the queue to be open.\n
+ *                    It ranges from 0 to the maximum queue index
+ *                    supported by the Multicore Navigator.
+ *
+ * @post  None.
+ *
+ * @return status, EM_OK on success.
+ */
+extern em_status_t ti_em_hw_queue_open(int queue_idx);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Closes an hard-ware queue on the data-base.
+ *
+ * @pre   The hard-ware queue shall already be used by the
+ *        Open-Em process.\n
+ *        If the hard-ware queue is not used, the function
+ *        is not successful.
+ *
+ * @remark The implementation is left to the user. An
+ *         example is provided in em_pdk_hal.c file
+ *         using the Qmss_queueClose PDK function.
+ *
+ * @param queue_idx   Index of the queue to be open.\n
+ *                    It ranges from 0 to the maximum queue index
+ *                    supported by the Multicore Navigator.
+ *
+ * @post  None.
+ *
+ * @return status, EM_OK on success.
+ */
+extern em_status_t ti_em_hw_queue_close(int queue_idx);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Opens an hard-ware receive flow on the data-base and configure the hard-ware registers of this receive flow.
+ *
+ * @pre   The hard-ware receive flow shall not be used by another
+ *        part of the application on the device.\n
+ *        If the hard-ware receive flow is already used, the function
+ *        is not successful.
+ *
+ * @remark The implementation is left to the user. An
+ *         example is provided in em_pdk_hal.c file
+ *         using the Cppi_configureRxFlow PDK function.
+ *
+ * @param dma_idx         Index of the dma instance.\n
+ *                        This refers to the Multicore Navigator PktDMA instance.
+ * @param flow_idx        Index of the receive flow to be open.\n
+ *                        It ranges from 0 to the maximum Rx Flow index
+ *                        supported by the Multicore Navigator instance.
+ * @param dst_queue_idx   Index of the destination queue.
+ * @param free_queue_idx  Index of the destination free queue.\n
+ *                        Queue indexes range from 0 to the maximum queue index
+ *                        supported by the Multicore Navigator instance.
+ * @param error_handling  Receive flow error handling mode when starvation occurs.\n
+ *                        0 = Starvation errors result in dropping packet.\n
+ *                        1 = Starvation errors result in subsequent re-try.
+ *
+ * @post  On success, the RX_FLOW_CONFIG registers shall be correctly configured.
+ *
+ * @return status, EM_OK on success
+ */
+extern em_status_t ti_em_rx_flow_open(int dma_idx, int flow_idx, int dst_queue_idx, int free_queue_idx, int error_handling);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Closes an hard-ware receive flow on the data-base.
+ *
+ * @pre   The hard-ware receive flow shall be used by the Open-EM process.\n
+ *        If the hard-ware receive flow is not used, the function
+ *        is not successful.
+ *
+ * @remark The implementation is left to the user. An
+ *         example is provided in em_pdk_hal.c file
+ *         using the Cppi_closeRxFlow PDK function.
+ *
+ * @param dma_idx         Index of the dma instance.\n
+ *                        This refers to the Multicore Navigator PktDMA instance.
+ * @param flow_idx        Index of the receive flow to be closed.\n
+ *                        It ranges from 0 to the maximum Rx Flow index
+ *                        supported by the Multicore Navigator instance.
+ *
+ * @return status, EM_OK on success
+ */
+extern em_status_t ti_em_rx_flow_close(int dma_idx, int flow_idx);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Opens an hard-ware xge receive flow on the data-base and configure the hard-ware registers of this receive flow.
+ *
+ * @pre   The hard-ware receive flow shall not be used by another
+ *        part of the application on the device.\n
+ *        If the hard-ware receive flow is already used, the function
+ *        is not successful.
+ *
+ * @remark The implementation is left to the user. An
+ *         example is provided in em_pdk_hal.c file
+ *         using the Cppi_configureRxFlow PDK function.
+ *
+ * @param dma_idx         Index of the dma instance.\n
+ *                        This refers to the Multicore Navigator PktDMA instance.
+ * @param flow_idx        Index of the receive flow to be open.\n
+ *                        It ranges from 0 to the maximum Rx Flow index
+ *                        supported by the Multicore Navigator instance.
+ * @param dst_queue_idx   Index of the destination queue.
+ * @param free_queue_idx0 Index of the destination free queue.\n
+ *                        Queue indexes range from 0 to the maximum queue index
+ *                        supported by the Multicore Navigator instance.
+ * @param free_queue_idx1 Index of the destination free queue.\n
+ *                        Queue indexes range from 0 to the maximum queue index
+ *                        supported by the Multicore Navigator instance.
+ * @param error_handling  Receive flow error handling mode when starvation occurs.\n
+ *                        0 = Starvation errors result in dropping packet.\n
+ *                        1 = Starvation errors result in subsequent re-try.
+ *
+ * @post  On success, the RX_FLOW_CONFIG registers shall be correctly configured.
+ *
+ * @return status, EM_OK on success
+ */
+extern em_status_t ti_em_xge_rx_flow_open(int dma_idx, int flow_idx, int dst_queue_idx, int free_queue_idx0, int free_queue_idx1, int error_handling);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Closes an hard-ware XGE receive flow on the data-base.
+ *
+ * @pre   The hard-ware receive flow shall be used by the Open-EM process.\n
+ *        If the hard-ware receive flow is not used, the function
+ *        is not successful.
+ *
+ * @remark The implementation is left to the user. An
+ *         example is provided in em_pdk_hal.c file
+ *         using the Cppi_closeRxFlow PDK function.
+ *
+ * @param dma_idx         Index of the dma instance.\n
+ *                        This refers to the Multicore Navigator PktDMA instance.
+ * @param flow_idx        Index of the receive flow to be closed.\n
+ *                        It ranges from 0 to the maximum Rx Flow index
+ *                        supported by the Multicore Navigator instance.
+ *
+ * @return status, EM_OK on success
+ */
+extern em_status_t ti_em_xge_rx_flow_close (int dma_idx, int flow_idx);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Opens an hard-ware process RIO receive flow on the data-base and configure the hard-ware registers of this receive flow.
+ * It also creates the mapping between the Type9 message parameters and the opened flow.
+ *
+ * @pre   The hard-ware receive flow shall not be used by another
+ *        part of the application on the device.\n
+ *        If the hard-ware receive flow is already used, the function
+ *        is not successful.
+ *
+ * @remark The implementation is left to the user. An
+ *         example is provided in em_pdk_hal.c file
+ *         using the Cppi_configureRxFlow PDK function and the CSL_SRIO_MapType9MessageToQueue CSL API.
+ *
+ * @param dma_idx                Index of the dma instance.\n
+ *                               This refers to the Multicore Navigator PktDMA instance.
+ * @param flow_idx               Index of the receive flow to be open.\n
+ *                               It ranges from 0 to the maximum Rx Flow index
+ *                               supported by the Multicore Navigator instance.
+ * @param dst_queue_idx          Index of the destination queue.
+ * @param free_queue_idxSizeA    Index of the destination free queue for packet length\n 
+ *                               smaller than sizeA. Queue indexes range from 0 to the 
+ *                               maximum queue index supported by the Multicore Navigator 
+ *                               instance.
+ * @param sizeA                  Maximal size in bytes of the packet length for free queue A
+ * @param free_queue_idxSizeB    Index of the destination free queue for packet length\n 
+ *                               smaller than sizeB. Queue indexes range from 0 to the 
+ *                               maximum queue index supported by the Multicore Navigator 
+ *                               instance.
+ * @param sizeB                  Maximal size in bytes of the packet length for free queue B
+ * @param free_queue_idxSizeC    Index of the destination free queue for packet length\n 
+ *                               smaller than sizeC. Queue indexes range from 0 to the 
+ *                               maximum queue index supported by the Multicore Navigator 
+ *                               instance.
+ * @param sizeC                  Maximal size in bytes of the packet length for free queue C
+ * @param free_queue_idxSizeD    Index of the destination free queue for packet length\n 
+ *                               smaller than sizeD. Queue indexes range from 0 to the 
+ *                               maximum queue index supported by the Multicore Navigator 
+ *                               instance.
+ * @param sizeD                  Maximal size in bytes of the packet length for free queue D
+ * @param free_queue_idxOverflow Index of the destination free queue for packet length\n 
+ *                               with overflow. Queue indexes range from 0 to the 
+ *                               maximum queue index supported by the Multicore Navigator 
+ *                               instance.
+ * @param deviceIdx              Index of the current device
+ * @param processIdx             Index of the current process
+ * @param error_handling         Receive flow error handling mode when starvation occurs.\n
+ *                               0 = Starvation errors result in dropping packet.\n
+ *                               1 = Starvation errors result in subsequent re-try.
+ *
+ * @post  On success, the RX_FLOW_CONFIG registers shall be correctly configured.
+ *
+ * @return status, EM_OK on success
+ */
+extern em_status_t ti_em_rio_rx_flow_open(int dma_idx,
+					  int flow_idx,
+					  int dst_queue_idx,
+					  int free_queue_idxSizeA,
+					  int sizeA,
+					  int free_queue_idxSizeB,
+					  int sizeB,
+					  int free_queue_idxSizeC,
+					  int sizeC,
+					  int free_queue_idxSizeD,
+					  int sizeD,
+					  int free_queue_idxOverflow,
+					  int deviceIdx,
+					  int processIdx,
+					  int error_handling);
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Opens an hard-ware process chaining receive flow on the data-base and configure the hard-ware registers of this receive flow.
+ *
+ * @pre   The hard-ware receive flow shall not be used by another
+ *        part of the application on the device.\n
+ *        If the hard-ware receive flow is already used, the function
+ *        is not successful.
+ *
+ * @remark The implementation is left to the user. An
+ *         example is provided in em_pdk_hal.c file
+ *         using the Cppi_configureRxFlow PDK function.
+ *
+ * @param dma_idx                Index of the dma instance.\n
+ *                               This refers to the Multicore Navigator PktDMA instance.
+ * @param flow_idx               Index of the receive flow to be open.\n
+ *                               It ranges from 0 to the maximum Rx Flow index
+ *                               supported by the Multicore Navigator instance.
+ * @param dst_queue_idx          Index of the destination queue.
+ * @param free_queue_idxSizeA    Index of the destination free queue for packet length\n 
+ *                               smaller than sizeA. Queue indexes range from 0 to the 
+ *                               maximum queue index supported by the Multicore Navigator 
+ *                               instance.
+ * @param sizeA                  Maximal size in bytes of the packet length for free queue A
+ * @param free_queue_idxSizeB    Index of the destination free queue for packet length\n 
+ *                               smaller than sizeB. Queue indexes range from 0 to the 
+ *                               maximum queue index supported by the Multicore Navigator 
+ *                               instance.
+ * @param sizeB                  Maximal size in bytes of the packet length for free queue B
+ * @param free_queue_idxSizeC    Index of the destination free queue for packet length\n 
+ *                               smaller than sizeC. Queue indexes range from 0 to the 
+ *                               maximum queue index supported by the Multicore Navigator 
+ *                               instance.
+ * @param sizeC                  Maximal size in bytes of the packet length for free queue C
+ * @param free_queue_idxSizeD    Index of the destination free queue for packet length\n 
+ *                               smaller than sizeD. Queue indexes range from 0 to the 
+ *                               maximum queue index supported by the Multicore Navigator 
+ *                               instance.
+ * @param sizeD                  Maximal size in bytes of the packet length for free queue D
+ * @param free_queue_idxOverflow Index of the destination free queue for packet length\n 
+ *                               with overflow. Queue indexes range from 0 to the 
+ *                               maximum queue index supported by the Multicore Navigator 
+ *                               instance.
+ * @param error_handling         Receive flow error handling mode when starvation occurs.\n
+ *                               0 = Starvation errors result in dropping packet.\n
+ *                               1 = Starvation errors result in subsequent re-try.
+ *
+ * @post  On success, the RX_FLOW_CONFIG registers shall be correctly configured.
+ *
+ * @return status, EM_OK on success
+ */
+extern em_status_t ti_em_chain_rx_flow_open(int dma_idx,
+					    int flow_idx,
+					    int dst_queue_idx,
+					    int free_queue_idxSizeA,
+					    int sizeA,
+					    int free_queue_idxSizeB,
+					    int sizeB,
+					    int free_queue_idxSizeC,
+					    int sizeC,
+					    int free_queue_idxSizeD,
+					    int sizeD,
+					    int free_queue_idxOverflow,
+					    int error_handling);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Opens an hard-ware transmit channel on the data-base and configure the hard-ware registers of this transmit channel.
+ *
+ * @pre   The hard-ware transmit channel shall not be used by another
+ *        part of the application on the device.\n
+ *        If the hard-ware transmit channel is already used, the function
+ *        is not successful.
+ *
+ * @remark The implementation is left to the user. An
+ *         example is provided in em_pdk_hal.c file
+ *         using the Cppi_txChannelOpen PDK function.
+ *
+ * @param dma_idx         Index of the dma instance.\n
+ *                        This refers to the Multicore Navigator PktDMA instance.
+ * @param channel_idx     Index of the transmit channel to be open.\n
+ *                        It ranges from 0 to the maximum Tx Channel index
+ *                        supported by the Multicore Navigator instance.
+ *
+ * @post  On success, the TX_CHANNEL_GLOBAL_CONFIG_REG_A register shall be enabled.\n
+ *        The TX_CHANNEL_SCHEDULER_CONFIG_REG_PRIORITY register shall be configured to the desired value.
+ *
+ * @return status, EM_OK on success
+ */
+extern em_status_t ti_em_tx_channel_open(int dma_idx, int channel_idx);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Closes an hard-ware transmit channel on the data-base.
+ *
+ * @pre   The hard-ware transmit channel shall be used by the Open-EM
+ *        process.\n
+ *        If the hard-ware transmit channel is not used, the function
+ *        is not successful.
+ *
+ * @remark The implementation is left to the user. An
+ *         example is provided in em_pdk_hal.c file
+ *         using the Cppi_channelClose PDK function.
+ *
+ * @param dma_idx         Index of the dma instance.\n
+ *                        This refers to the Multicore Navigator PktDMA instance.
+ * @param channel_idx     Index of the transmit channel to be closed.\n
+ *                        It ranges from 0 to the maximum Tx Channel index
+ *                        supported by the Multicore Navigator instance.
+ *
+ * @return status, EM_OK on success
+ */
+extern em_status_t ti_em_tx_channel_close(int dma_idx, int channel_idx);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Opens an hard-ware xge transmit channel on the data-base and configure the hard-ware registers of this transmit channel.
+ *
+ * @pre   The hard-ware transmit channel shall not be used by another
+ *        part of the application on the device.\n
+ *        If the hard-ware transmit channel is already used, the function
+ *        is not successful.
+ *
+ * @remark The implementation is left to the user. An
+ *         example is provided in em_pdk_hal.c file
+ *         using the Cppi_txChannelOpen PDK function.
+ *
+ * @param dma_idx         Index of the dma instance.\n
+ *                        This refers to the Multicore Navigator PktDMA instance.
+ * @param channel_idx     Index of the transmit channel to be open.\n
+ *                        It ranges from 0 to the maximum Tx Channel index
+ *                        supported by the Multicore Navigator instance.
+ *
+ * @post  On success, the TX_CHANNEL_GLOBAL_CONFIG_REG_A register shall be enabled.\n
+ *        The TX_CHANNEL_SCHEDULER_CONFIG_REG_PRIORITY register shall be configured to the desired value.
+ *
+ * @return status, EM_OK on success
+ */
+extern em_status_t ti_em_xge_tx_channel_open(int dma_idx, int channel_idx);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Closes an hard-ware XGE transmit channel on the data-base.
+ *
+ * @pre   The hard-ware transmit channel shall be used by the Open-EM
+ *        process.\n
+ *        If the hard-ware transmit channel is not used, the function
+ *        is not successful.
+ *
+ * @remark The implementation is left to the user. An
+ *         example is provided in em_pdk_hal.c file
+ *         using the Cppi_channelClose PDK function.
+ *
+ * @param dma_idx         Index of the dma instance.\n
+ *                        This refers to the Multicore Navigator PktDMA instance.
+ * @param channel_idx     Index of the transmit channel to be closed.\n
+ *                        It ranges from 0 to the maximum Tx Channel index
+ *                        supported by the Multicore Navigator instance.
+ *
+ * @return status, EM_OK on success
+ */
+extern em_status_t ti_em_xge_tx_channel_close (int dma_idx, int channel_idx);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Opens an hard-ware SRIO transmit channel on the data-base and configure the hard-ware registers of this transmit channel.
+ *
+ * @pre   The hard-ware transmit channel shall not be used by another
+ *        part of the application on the device.\n
+ *        If the hard-ware transmit channel is already used, the function
+ *        is not successful.
+ *
+ * @remark The implementation is left to the user. An
+ *         example is provided in em_pdk_hal.c file
+ *         using the Cppi_txChannelOpen PDK function.
+ *
+ * @param dma_idx         Index of the dma instance.\n
+ *                        This refers to the Multicore Navigator PktDMA instance.
+ *
+ * @post  On success, the TX_CHANNEL_GLOBAL_CONFIG_REG_A register shall be enabled.\n
+ *        The TX_CHANNEL_SCHEDULER_CONFIG_REG_PRIORITY register shall be configured to the desired value.
+ *
+ * @return status, EM_OK on success
+ */
+extern em_status_t ti_em_rio_tx_channel_open(int dma_idx);
+
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Opens an hard-ware receive channel on the data-base and configure the hard-ware registers of this receive channel.
+ *
+ * @pre   The hard-ware receive channel shall not be used by another
+ *        part of the application on the device.\n
+ *        If the hard-ware receive channel is already used, the function
+ *        is not successful.
+ *
+ * @remark The implementation is left to the user. An
+ *         example is provided in em_pdk_hal.c file
+ *         using the Cppi_rxChannelOpen PDK function.
+ *
+ * @param dma_idx         Index of the dma instance.\n
+ *                        This refers to the Multicore Navigator PktDMA instance.
+ * @param channel_idx     Index of the receive channel to be open.\n
+ *                        It ranges from 0 to the maximum Rx Channel index
+ *                        supported by the Multicore Navigator instance.
+ *
+ * @post  On success, the RX_CHANNEL_GLOBAL_CONFIG_REG register shall be enabled.
+ *
+ * @return status, EM_OK on success
+ */
+extern em_status_t ti_em_rx_channel_open(int dma_idx, int channel_idx);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Closes an hard-ware receive channel on the data-base.
+ *
+ * @pre   The hard-ware receive channel shall be used by the
+ *        Open-EM process.\n
+ *        If the hard-ware receive channel is not used, the function
+ *        is not successful.
+ *
+ * @remark The implementation is left to the user. An
+ *         example is provided in em_pdk_hal.c file
+ *         using the Cppi_channelClose PDK function.
+ *
+ * @param dma_idx         Index of the dma instance.\n
+ *                        This refers to the Multicore Navigator PktDMA instance.
+ * @param channel_idx     Index of the receive channel to be closed.\n
+ *                        It ranges from 0 to the maximum Rx Channel index
+ *                        supported by the Multicore Navigator instance.
+ *
+ * @return status, EM_OK on success
+ */
+extern em_status_t ti_em_rx_channel_close(int dma_idx, int channel_idx);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Opens an hard-ware xge receive channel on the data-base and configure the hard-ware registers of this receive channel.
+ *
+ * @pre   The hard-ware receive channel shall not be used by another
+ *        part of the application on the device.\n
+ *        If the hard-ware receive channel is already used, the function
+ *        is not successful.
+ *
+ * @remark The implementation is left to the user. An
+ *         example is provided in em_pdk_hal.c file
+ *         using the Cppi_rxChannelOpen PDK function.
+ *
+ * @param dma_idx         Index of the dma instance.\n
+ *                        This refers to the Multicore Navigator PktDMA instance.
+ * @param channel_idx     Index of the receive channel to be open.\n
+ *                        It ranges from 0 to the maximum Rx Channel index
+ *                        supported by the Multicore Navigator instance.
+ *
+ * @post  On success, the RX_CHANNEL_GLOBAL_CONFIG_REG register shall be enabled.
+ *
+ * @return status, EM_OK on success
+ */
+extern em_status_t ti_em_xge_rx_channel_open(int dma_idx, int channel_idx);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Closes an hard-ware XGE receive channel on the data-base.
+ *
+ * @pre   The hard-ware receive channel shall be used by the
+ *        Open-EM process.\n
+ *        If the hard-ware receive channel is not used, the function
+ *        is not successful.
+ *
+ * @remark The implementation is left to the user. An
+ *         example is provided in em_pdk_hal.c file
+ *         using the Cppi_channelClose PDK function.
+ *
+ * @param dma_idx         Index of the dma instance.\n
+ *                        This refers to the Multicore Navigator PktDMA instance.
+ * @param channel_idx     Index of the receive channel to be closed.\n
+ *                        It ranges from 0 to the maximum Rx Channel index
+ *                        supported by the Multicore Navigator instance.
+ *
+ * @return status, EM_OK on success
+ */
+extern em_status_t ti_em_xge_rx_channel_close (int dma_idx, int channel_idx);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Opens an hard-ware xge transmit queue on the data-base and configure the hard-ware registers of this transmit queue.
+ *
+ * @pre   The hard-ware transmit queue shall not be used by another
+ *        part of the application on the device.\n
+ *        If the hard-ware transmit queue is already used, the function
+ *        is not successful.
+ *
+ * @remark The implementation is left to the user. An
+ *         example is provided in em_pdk_hal.c file
+ *         using the ti_em_hw_queue_open function.
+ *
+ * @param queue_base_idx          Index of the 1st XGE tx queue
+ * @param vlan_priority           VLAN priority.
+ *
+ * @return index of the XGE transmit queue
+ */
+extern ti_em_queue_id_t ti_em_xge_tx_queue_open(ti_em_queue_id_t queue_base_idx, int    vlan_priority);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Returns the first hard-ware xge transmit queue among TI_EM_XGE_VLAN_PRIO_NUM (8).
+ *
+ * @pre   The hard-ware transmit queue shall not be used by another
+ *        part of the application on the device.\n
+ *        If the hard-ware transmit queue is already used, the function
+ *        is not successful.
+ *
+ * @remark The implementation is left to the user. An
+ *         example is provided in em_pdk_hal.c file
+ *         using the ti_em_xge_tx_queue_base_idx_get function.
+ *
+ * @param .
+ *
+ * @return index of the first XGE transmit queue
+ */
+extern ti_em_queue_id_t ti_em_xge_tx_queue_base_idx_get (void);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Opens an hard-ware SRIO transmit queue on the data-base and configure the hard-ware registers of this transmit queue.
+ *
+ * @pre   The hard-ware transmit queue shall not be used by another
+ *        part of the application on the device.\n
+ *        If the hard-ware transmit queue is already used, the function
+ *        is not successful.
+ *
+ * @remark The implementation is left to the user. An
+ *         example is provided in em_pdk_hal.c file
+ *         using the ti_em_hw_queue_open function.
+ *
+ * @param rio_tx_queue_idx           RIO queue index
+ *
+ * @return index of the RIO transmit queue or error
+ */
+extern ti_em_queue_id_t ti_em_rio_tx_queue_open(int rio_tx_queue_idx);
+
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Retrieves the absolute queue index from the associated Multicore Navigator PkDMA engine index
+ * and the relative TX queue index.
+ *
+ * @remark The implementation is left to the user. An
+ *         example is provided in em_pdk_hal.c file
+ *         using the CPPI LLD.
+ *
+ * @param dma_idx         Index of the dma instance.\n
+ *                        This refers to the Multicore Navigator PktDMA instance.
+ *
+ * @param queue_idx       Relative index of the queue.
+ *
+ * @return Absolute index of the queue.
+ */
+extern ti_em_queue_id_t ti_em_get_absolute_queue_id(ti_em_dma_id_t dma_idx, ti_em_queue_id_t queue_idx);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Loops over all data buffers of the event and perform a cache write back invalidate if the data buffer is dirty.
+ *
+ * @param event           Event handle.
+ *
+ */
+void ti_em_flush(em_event_t event);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Helper function which sets the ps words in the event.
+ *
+ * @param event         Event handle.
+ * @param ps_word_ptr   Pointer to ps words.
+ * @param ps_wsize      Number of ps words.
+ *
+ * @return status, EM_OK on success
+ */
+em_status_t ti_em_set_ps_words(em_event_t event, uint32_t* ps_word_ptr, size_t ps_wsize);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Helper function which gets the ps words from the event.
+ *
+ * @param event         Event handle.
+ * @param ps_word_ptr   Pointer to ps words.
+ * @param ps_wsize      Number of ps words.
+ *
+ * @return status, EM_OK on success
+ */
+em_status_t ti_em_get_ps_words(em_event_t event, uint32_t* ps_word_ptr, size_t ps_wsize);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Helper function which sets the number of ps words in the event.
+ *
+ * @param event         Event handle.
+ * @param ps_wsize      Number of ps words.
+ *
+ * @return status, EM_OK on success
+ */
+em_status_t ti_em_set_ps_wsize(em_event_t event, size_t ps_wsize);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Helper function which gets the number of ps words from the event.
+ *
+ * @param event         Event handle.
+ *
+ * @return Number of ps words
+ */
+size_t ti_em_get_ps_wsize(em_event_t event);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Adds a process route to the device router.
+ *
+ * @param process_route  Parameters of the process route.
+ *
+ * @param process_idx  Process index.
+ *
+ * @return status, EM_OK on success
+ */
+em_status_t ti_em_process_add_route(ti_em_process_route_t process_route, ti_em_process_id_t process_idx);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Adds an XGE route to the device router.
+ *
+ * @param device_idx  Device index.
+ *
+ * @param device_route  Device route.
+ *
+ * @return status, EM_OK on success
+ */
+em_status_t ti_em_device_add_xge_route(ti_em_device_id_t device_idx, ti_em_device_xge_route_t device_route);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Adds an SRIO route to the device router.
+ *
+ * @param device_idx  Device index.
+ *
+ * @param device_route  Device route.
+ *
+ * @return status, EM_OK on success
+ */
+em_status_t ti_em_device_add_rio_route(ti_em_device_id_t device_idx, ti_em_device_rio_route_t device_route);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Creates a static HW queue.
+ *
+ * @param name          Queue name for debugging purposes (optional, NULL ok)
+ *
+ * @param hw_queue_idx  Hw queue index
+ *
+ * @param queue         Requested queue id from the static range
+ *
+ * @return  EM_OK on success or EM_QUEUE_UNDEF on an error
+ */
+em_status_t ti_em_queue_create_hw_static(const char* name, ti_em_queue_id_t hw_queue_idx, em_queue_t queue);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Creates a HW queue.
+ *
+ * @param name          Queue name for debugging purposes (optional, NULL ok)
+ *
+ * @param hw_queue_idx  Hw queue index
+ *
+ * @return new queue id or EM_QUEUE_UNDEF on an error
+ */
+em_queue_t ti_em_queue_create_hw(const char* name, ti_em_queue_id_t hw_queue_idx);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Receives an event from a queue.
+ *
+ * Event must have been allocated with em_alloc().
+ *
+ * @param queue         Receiving queue
+ *
+ * @return the received event or EM_EVENT_UNDEF if the queue is empty.
+ * 
+ * @see em_alloc()
+ */
+em_event_t ti_em_receive(em_queue_t queue);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Enables the interrupt generation for the attached dispatcher.
+ * The interrupt channel index used is based on the configuration
+ * hw_queue_base_idx and the physical core index.
+ * If the interrupt channel index is inferior to 32, it is mapped to
+ * one of the 32 HI channels in the associated INTD register.
+ * Otherwise it is mapped to one of the 16 LOW channels.
+ * By default, the interrupt are not enabled.
+ *
+ * @return status, EM_OK on success
+ */
+em_status_t ti_em_interrupt_enable(void);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Disables the interrupt generation for the attached dispatcher.
+ *
+ * @return status, EM_OK on success
+ */
+em_status_t ti_em_interrupt_disable(void);
+
+#endif /* EVENT_MACHINE_HW_TI_FUNCTIONS_H_ */
+
diff --git a/platform/linux-keystone2/prebuilts/openem/include/event_machine_hw_ti_macros.h b/platform/linux-keystone2/prebuilts/openem/include/event_machine_hw_ti_macros.h
new file mode 100644
index 0000000..51830df
--- /dev/null
+++ b/platform/linux-keystone2/prebuilts/openem/include/event_machine_hw_ti_macros.h
@@ -0,0 +1,570 @@
+/*
+ * Copyright (c) 2012, Texas Instruments Incorporated - http://www.ti.com/
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *       * Redistributions of source code must retain the above copyright
+ *         notice, this list of conditions and the following disclaimer.
+ *       * Redistributions in binary form must reproduce the above copyright
+ *         notice, this list of conditions and the following disclaimer in the
+ *         documentation and/or other materials provided with the distribution.
+ *       * Neither the name of Texas Instruments Incorporated nor the
+ *         names of its contributors may be used to endorse or promote products
+ *         derived from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ *   WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY
+ *   DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ *   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *   ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/**
+ * @file: event_machine_hw_ti_macros.h
+ *
+ * @brief
+ *    Open Event Machine HW TI specific constant definitions
+ *
+ */
+
+#ifndef EVENT_MACHINE_HW_TI_MACROS_H_
+#define EVENT_MACHINE_HW_TI_MACROS_H_
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Number of 32 bits words in an ti_em_iterator_t array.
+ */
+#define TI_EM_ITERATOR_WSIZE (8u)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Number of PF events per core.
+ */
+#define TI_EM_PF_LEN (1u)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Maximum number of cores on a device on which the Event Machine can be executed.
+ */
+#define TI_EM_CORE_NUM (8u)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Maximum number of Navigator PDSP instances on which this process scheduler can be executed.
+ * Only relevant on a Keystone II target.
+ */
+#define TI_EM_SCHEDULER_THREAD_NUM (4u)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Maximum number of Open-EM processes on a device on which the Event Machine can be executed.
+ */
+#define TI_EM_PROCESS_NUM (2u)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Chaining disabled on Open-EM process.
+ */
+#define TI_EM_CHAIN_DISABLED (0u)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Chaining enabled on Open-EM process.
+ */
+#define TI_EM_CHAIN_ENABLED (1u)
+
+/** 
+ * @ingroup DOC_api_specific
+ *
+ * Maximum number of TX queues for chaining and poststoring. Must be a power of 2: 1, 2, 4 or 8.
+ */
+#ifdef TI_EM_LINUX
+#define TI_EM_CHAIN_TX_QUEUE_NUM (1u)
+#else /* TI_EM_LINUX */
+#define TI_EM_CHAIN_TX_QUEUE_NUM (4u)
+#endif /* TI_EM_LINUX */
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Preload disabled.
+ */
+#define TI_EM_PRELOAD_DISABLED (0u)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Preload enabled.
+ */
+#define TI_EM_PRELOAD_ENABLED (1u)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Maximum number of devices on which the Open-EM can be executed.
+ */
+#define TI_EM_DEVICE_NUM (4096u)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Maximum number of queue sets. Must be a power of 2.
+ */
+#define TI_EM_QUEUE_SET_NUM (256u)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Maximum number of queues in a set. TI_EM_QUEUE_SET_NUM * TI_EM_QUEUE_NUM_IN_SET <= TI_EM_QUEUE_NUM_MAX.
+ */
+#define TI_EM_QUEUE_NUM_IN_SET (8u)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Maximum number of queues.
+ */
+#define TI_EM_QUEUE_NUM_MAX (16384u)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Number of static queues in a set. TI_EM_QUEUE_SET_NUM*TI_EM_STATIC_QUEUE_NUM_IN_SET <= TI_EM_STATIC_QUEUE_NUM_MAX
+ */
+#define TI_EM_STATIC_QUEUE_NUM_IN_SET (2u)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Maximum number of static queues. TI_EM_STATIC_QUEUE_NUM_MAX <= TI_EM_QUEUE_NUM_MAX.
+ */
+#define TI_EM_STATIC_QUEUE_NUM_MAX (256u)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Maximum number of execution objects.
+ */
+#define TI_EM_EO_NUM_MAX (TI_EM_QUEUE_NUM_MAX)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Maximum number of event groups.
+ */
+#define TI_EM_EVENT_GROUP_NUM_MAX (16384u)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Maximum number of queue groups.
+ */
+#define TI_EM_QUEUE_GROUP_NUM_MAX (TI_EM_PRIO_NUM * TI_EM_CORE_NUM)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Alignment of QM queue base index
+ */
+#define TI_EM_HW_QUEUE_STEP (32u)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Maximum number of XGE streams.
+ */
+#define TI_EM_STREAM_NUM (256u)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Size (in bytes) of the XGE header.
+ */
+#define TI_EM_XGE_ENET_HEADER_SIZE (18u)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Size (in bytes) of the XGE header.
+ */
+#define TI_EM_XGE_CHAIN_HEADER_SIZE (8u)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Size (in bytes) of the XGE header (18+8=26).
+ */
+#define TI_EM_XGE_HEADER_SIZE (TI_EM_XGE_ENET_HEADER_SIZE + TI_EM_XGE_CHAIN_HEADER_SIZE)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Minimal size (in bytes) of the XGE frame.
+ */
+#define TI_EM_XGE_FRAME_SIZE_MIN (64u)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Size (in bytes) of the CRC added by XGE.
+ */
+#define TI_EM_XGE_CRC_SIZE (4)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Minimum size (in bytes) of the fragment size (64 - 26 - 4 = 34 Bytes).
+ */
+#define TI_EM_XGE_PAYLOAD_SIZE_MIN (TI_EM_XGE_FRAME_SIZE_MIN - TI_EM_XGE_HEADER_SIZE - TI_EM_XGE_CRC_SIZE )
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Minimal size (in bytes) to be allocated for the XGE RX fragment buffer (34 + 4 = 38).
+ */
+#define TI_EM_XGE_RX_FRAGMENT_SIZE_MIN (TI_EM_XGE_PAYLOAD_SIZE_MIN + TI_EM_XGE_CRC_SIZE)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Size (in bytes) to be allocated for the XGE TX header buffer (26 + 34 = 60).
+ */
+#define TI_EM_XGE_TX_HEADER_SIZE (TI_EM_XGE_HEADER_SIZE + TI_EM_XGE_PAYLOAD_SIZE_MIN)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Size (in bytes) to be allocated for the XGE RX header buffer (26).
+ */
+#define TI_EM_XGE_RX_HEADER_SIZE (TI_EM_XGE_HEADER_SIZE)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Size (in bytes) to be allocated for the XGE TX fragment buffer
+ */
+#define TI_EM_XGE_TX_FRAGMENT_SIZE 0
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Maximum number of contiguous XGE TX queues
+ */
+#define TI_EM_XGE_TX_QUEUE_NUM (1u)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Number of VLAN priorities that need to be reserved for chaining over XGE
+ */
+#define TI_EM_XGE_VLAN_PRIO_NUM (8u)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Number of contiguous RX miss queues that need to be reserved for chaining over XGE
+ */
+#define TI_EM_XGE_RX_MISS_QUEUE_NUM (TI_EM_XGE_VLAN_PRIO_NUM)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Number of contiguous TX divert queues that need to be reserved for chaining over XGE
+ */
+#define TI_EM_XGE_TX_DIVERT_QUEUE_NUM (32u)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Total number of PKTDMA queues used by the EM
+ */
+#define TI_EM_DMA_QUEUE_NUM (TI_EM_CORE_NUM + 2)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Highest Priority
+ */
+#define TI_EM_PRIO_NUM (EM_QUEUE_PRIO_HIGHEST + 1)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Total number of queues used by the EM
+ */
+#define TI_EM_HW_QUEUE_NUM (11                        \
+                + TI_EM_PRIO_NUM                \
+                + (3 * TI_EM_CORE_NUM)            \
+                + (3 * TI_EM_CORE_NUM * TI_EM_PRIO_NUM)    \
+                + (TI_EM_CORE_NUM * TI_EM_PRIO_NUM * TI_EM_PF_LEN) \
+                + TI_EM_XGE_VLAN_PRIO_NUM)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Size for all the private token used by the EM
+ */
+#define TI_EM_PRIVATE_EVENT_DSC_SIZE (16u)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Multi-core Navigator PDSP memory size to allocated for
+ * private events and private firmware data.
+ */
+#define TI_EM_PDSP_GLOBAL_DATA_SIZE (8192u)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Maximum number of AP private tokens used by the EM
+ */
+#define TI_EM_AP_PRIVATE_EVENT_NUM (256u)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Maximum number of CD private tokens used by the EM
+ */
+#define TI_EM_CD_PRIVATE_EVENT_NUM (64u)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Trace scope for the em_alloc API.
+ *
+ */
+#define TI_EM_TSCOPE_ALLOC (1)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Trace scope for the em_send API.
+ *
+ */
+#define TI_EM_TSCOPE_SEND (2)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Trace scope for the ti_em_dispatch_once API.
+ *
+ */
+#define TI_EM_TSCOPE_DISPATCH (3)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Trace scope for the ti_em_preschedule API.
+ *
+ */
+#define TI_EM_TSCOPE_PRESCHEDULE (4)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Trace scope for the ti_em_claim_local API.
+ *
+ */
+#define TI_EM_TSCOPE_CLAIM_LOCAL (5)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Trace scope for the em_atomic_processing_end API.
+ *
+ */
+#define TI_EM_TSCOPE_ATOMIC_PROCESSING_END (6)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Trace scope for the em_free API.
+ *
+ */
+#define TI_EM_TSCOPE_FREE (7)
+
+/**
+ * @ingroup DOC_api_specific
+ * 
+ * Major event types (portable) : Data Preloading Off
+ * @note Application should always ignore the actual values.
+ */
+#define TI_EM_EVENT_TYPE_PRELOAD_OFF (0u)
+
+/**
+ * @ingroup DOC_api_specific
+ * 
+ * Major event types (portable) : Data Preloading up to size A
+ * @note Application should always ignore the actual values.
+ */
+#define TI_EM_EVENT_TYPE_PRELOAD_ON_SIZE_A (1u<<6)
+
+/**
+ * @ingroup DOC_api_specific
+ * 
+ * Major event types (portable) : Data Preloading up to size B
+ * @note Application should always ignore the actual values.
+ */
+#define TI_EM_EVENT_TYPE_PRELOAD_ON_SIZE_B (2u<<6)
+
+/**
+ * @ingroup DOC_api_specific
+ * 
+ * Major event types (portable) : Data Preloading up to size C
+ * @note Application should always ignore the actual values.
+ */
+#define TI_EM_EVENT_TYPE_PRELOAD_ON_SIZE_C (3u<<6)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Event type preload mask.
+ *
+ */
+#define TI_EM_EVENT_TYPE_PRELOAD_MSK (0xC0)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Buffer mode - Tight buffer
+ */
+#define TI_EM_BUF_MODE_GLOBAL_TIGHT (0)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Buffer mode - Loose buffer
+ */
+#define TI_EM_BUF_MODE_GLOBAL_LOOSE (1)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Buffer mode - Local buffer
+ */
+#define TI_EM_BUF_MODE_LOCAL (2)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Cache coherency mode - Off
+ */
+#define TI_EM_COH_MODE_OFF (0x0)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Cache coherency mode - On
+ */
+#define TI_EM_COH_MODE_ON (0x1)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Cache coherency mode - Reserved0
+ */
+#define TI_EM_COH_MODE_RESERVED0 (0x2)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Cache coherency mode - Reserved1
+ */
+#define TI_EM_COH_MODE_RESERVED1 (0x3)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Queue associated with a scheduling (SD) queue.
+ */
+#define TI_EM_QUEUE_MODE_SD (0u)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Queue associated with an hardware (HW) queue.
+ */
+#define TI_EM_QUEUE_MODE_HW (1u)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Push policy to tail
+ */
+#define TI_EM_PUSH_POLICY_TAIL (0x0)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Push policy to head
+ */
+#define TI_EM_PUSH_POLICY_HEAD (0x1)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * ID for the various chaining mechanisms (i.e. chaining modules)
+ */
+#define TI_EM_CHAINING_PKTDMA    (0)
+#define TI_EM_CHAINING_XGE       (1)
+#define TI_EM_CHAINING_RIO       (2)
+#define TI_EM_CHAINING_POSTSTORE (3)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Definitions of the various PDSP communication memory slots
+ */
+#define TI_EM_SLOT_SPCB        (0)
+#define TI_EM_SLOT_RPCB        (1)
+#define TI_EM_SLOT_SPSB        (2)
+#define TI_EM_SLOT_RPSB        (3)
+#define TI_EM_SLOT_RDCB        (4)
+#define TI_EM_SLOT_ESB         (5 + DNUM)
+
+/*
+ * @ingroup DOC_api_specific
+ * 
+ * These are the different memory mappings for I/O, descriptors or PDSP memory
+ */
+#define TI_EM_MEM_NONE         (0)
+#define TI_EM_MEM_QMSS_REGS    (1)
+#define TI_EM_MEM_PDSP_DRAM    (2)
+#define TI_EM_MEM_PUBLIC_DESC  (3)
+#define TI_EM_MEM_LOCAL_DESC   (4)
+#define TI_EM_MEM_PRIVATE_DESC (5)
+#define TI_EM_MEM_PDSP_COMM    (6)
+#define TI_EM_MEM_BUFFER       (7)
+#define TI_EM_MEM_NUM          (TI_EM_BUFFER_POOL_ID_NUM + TI_EM_MEM_BUFFER) /* total number of available mappings */
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Maximum number of pool Id that can be set in the event descriptor pool index field (8 bits)
+ */
+#define TI_EM_BUFFER_POOL_ID_NUM (256u)
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Enable/disable PDSP interrupt generation
+ */
+#define TI_EM_INTERRUPT_DISABLE (0)
+#define TI_EM_INTERRUPT_ENABLE  (1)
+
+#endif /*EVENT_MACHINE_HW_TI_MACROS_H_*/
diff --git a/platform/linux-keystone2/prebuilts/openem/include/event_machine_hw_ti_types.h b/platform/linux-keystone2/prebuilts/openem/include/event_machine_hw_ti_types.h
new file mode 100644
index 0000000..ebb2b7b
--- /dev/null
+++ b/platform/linux-keystone2/prebuilts/openem/include/event_machine_hw_ti_types.h
@@ -0,0 +1,792 @@
+/*
+ * Copyright (c) 2012, Texas Instruments Incorporated - http://www.ti.com/
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *       * Redistributions of source code must retain the above copyright
+ *         notice, this list of conditions and the following disclaimer.
+ *       * Redistributions in binary form must reproduce the above copyright
+ *         notice, this list of conditions and the following disclaimer in the
+ *         documentation and/or other materials provided with the distribution.
+ *       * Neither the name of Texas Instruments Incorporated nor the
+ *         names of its contributors may be used to endorse or promote products
+ *         derived from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ *   WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY
+ *   DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ *   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *   ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/**
+ * @file: event_machine_hw_ti_types.h
+ *
+ * @brief
+ *    Open Event Machine HW TI specific type definitions
+ *
+ */
+
+#ifndef EVENT_MACHINE_HW_TI_TYPES_H_
+#define EVENT_MACHINE_HW_TI_TYPES_H_
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * typedef associated with ti_em_config_t_
+ */
+typedef struct ti_em_config_t_ ti_em_config_t;
+typedef struct ti_em_chain_config_t_ ti_em_chain_config_t;
+typedef struct ti_em_chain_xge_config_t_ ti_em_chain_xge_config_t;
+typedef struct ti_em_chain_rio_config_t_ ti_em_chain_rio_config_t;
+typedef struct ti_em_preload_config_t_ ti_em_preload_config_t;
+typedef struct ti_em_poststore_config_t_ ti_em_poststore_config_t;
+typedef struct ti_em_device_xge_route_t_ ti_em_device_xge_route_t;
+typedef struct ti_em_device_rio_route_t_ ti_em_device_rio_route_t;
+typedef struct ti_em_buffer_config_t_ ti_em_buffer_config_t;
+typedef struct ti_em_pool_config_t_ ti_em_pool_config_t;
+typedef struct ti_em_pair_t_ ti_em_pair_t;
+typedef struct ti_em_iterator_t_ ti_em_iterator_t; 
+typedef struct ti_em_process_route_t_ ti_em_process_route_t; 
+
+#include <inttypes.h>
+#include <stdlib.h>
+#include <event_machine_hw_types.h>
+#include <event_machine_hw_ti_macros.h>
+#include <event_machine_sw_ti_config.h>
+#include <src/event_machine_hwpform.h>
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Packet.
+ * Identifies the packet of the event.
+ *
+ */
+typedef uint32_t ti_em_packet_t;
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Event queue id.
+ * Identifies the event queue.
+ *
+ */
+typedef uint16_t ti_em_queue_id_t;
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * DMA id.
+ * Identifies the DMA.
+ *
+ */
+typedef uint32_t ti_em_dma_id_t;
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * flow id.
+ * Identifies the flow.
+ *
+ */
+typedef uint32_t ti_em_flow_id_t;
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Hardware semaphore id.
+ * Identifies the hardware semaphore.
+ *
+ */
+typedef uint32_t ti_em_sem_id_t;
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Openem process id.
+ * Identifies the openem process.
+ *
+ */
+typedef uint8_t ti_em_process_id_t;
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Openem process type.
+ * Identifies the openem process type.
+ *
+ */
+typedef uint32_t ti_em_process_type_t;
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Pdsp id.
+ * Identifies the Pdsp.
+ *
+ */
+typedef uint8_t ti_em_pdsp_id_t;
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Device id.
+ * Identifies the device.
+ *
+ */
+typedef uint32_t ti_em_device_id_t;
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Destination id.
+ * Identifies the destination for a route. It may be a ti_em_process_id_t or
+ * a ti_em_device_id_t.
+ */
+typedef uint32_t ti_em_destination_id_t;
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Stream id.
+ * Identifies the stream.
+ *
+ */
+typedef uint32_t ti_em_stream_id_t;
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Trace scope.
+ * Identifies the scope for interpreting trace codes and variable arguments
+ *
+ */
+typedef uint32_t ti_em_tscope_t;
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Cache Coherency mode.
+ * Identifies the data buffer cache coherency mode.
+ *
+ */
+typedef uint32_t ti_em_coh_mode_t;
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ *
+ * Identifies the event buffer mode.
+ *
+ */
+typedef uint32_t ti_em_buf_mode_t;
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ *
+ * Identifies the push policy.
+ *
+ */
+typedef uint32_t ti_em_push_policy_t;
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Identifies the Interrupt index.
+ *
+ */
+typedef uint8_t ti_em_interrupt_id_t;
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Identifies the Queue Mode.
+ *
+ */
+typedef uint8_t ti_em_queue_mode_t;
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Free funtion handler.
+ * 
+ * @param buffer_ptr        buffer pointer
+ * @param buffer_size       buffer size
+ *
+ */
+typedef void (*ti_em_free_func_t)(void* buffer_ptr, size_t buffer_size);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Trace function handler.
+ * 
+ * @param tscope        Error scope. Identifies the scope for interpreting the error code and variable arguments
+ * @param args          Variable number and type of arguments
+ *
+ * @return The function may not return depending on implementation.
+ *
+ * @see em_register_trace_handler(), em_unregister_trace_handler()
+ */
+typedef em_status_t (*ti_em_trace_handler_t)(ti_em_tscope_t tscope, ...);
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ *
+ * Identifies the iterator type.
+ *
+ * @details This describes the array of iterator fields.
+ *
+ */
+struct ti_em_iterator_t_ 
+{
+    /**
+      * array of iterator fields
+      */
+    uint32_t body[TI_EM_ITERATOR_WSIZE];
+}; 
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Data buffer pool configuration.
+ *
+ * @details This describes the data buffer pool configurable parameters which are required.
+ */
+struct ti_em_pool_config_t_
+{
+    /**
+      * Number of bytes used for storing a buffer
+      */
+    size_t buf_size;
+
+    /**
+      * Number of words used for storing a descriptor
+      */
+    size_t dsc_wsize;
+    
+    /**
+      * Event machine pool buffer mode
+      */
+    ti_em_buf_mode_t buf_mode;
+
+    /**
+      * Event machine pool free queues
+      */
+    uint16_t free_queue_idx;
+};
+
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Buffer parameters.
+ *
+ * @details This describes the buffer configurable parameters which are required.
+ */
+struct ti_em_buffer_config_t_
+{
+    /**
+      * Buffer pointer
+      */
+    void* buffer_ptr;
+
+    /**
+      * Buffer size
+      */
+    size_t buffer_size;
+
+    /**
+      * Original buffer pointer
+      */
+    void* orig_buffer_ptr;
+
+    /**
+      * Original buffer size
+      */
+    size_t orig_buffer_size;
+
+   /**
+      * Original buffer pool id 
+      */
+    uint32_t orig_buffer_pool;
+
+    /**
+      * Buffer coherency mode
+      */
+    ti_em_coh_mode_t coh_mode;
+
+    /**
+      * Buffer free function
+      */
+    ti_em_free_func_t free_func;
+
+    /**
+      * Event machine pool free push policy
+      */
+    ti_em_push_policy_t free_push_policy;
+};
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Event Machine hardware configuration.
+ *
+ * @details This describes the EM configurable parameters which are required.
+ */
+#ifndef TI_EM_GCC
+#pragma STRUCT_ALIGN (ti_em_config_t_, 64);
+#pragma STRUCT_ALIGN (ti_em_config_t_, 64)
+#endif
+struct ti_em_config_t_
+{
+    /**
+      * Pointer to the chaining configuration.
+      */
+    ti_em_chain_config_t* chain_config_ptr;
+
+    /**
+      * Pointer to the preload configuration.
+      */
+    ti_em_preload_config_t* preload_config_ptr;
+
+    /**
+      * Index for Packet DMA flows configuration. It has to map to a Multicore Navigator infrastructure Packet DMA.
+      */
+    ti_em_dma_id_t  dma_idx;
+
+    /**
+      * Index of the first DMA queue that will be used by the TI EM.
+      */
+    uint16_t dma_queue_base_idx;
+
+    /**
+      * Index of the 1st hardware queue that will be used by the TI EM.
+      */
+    uint16_t hw_queue_base_idx;
+
+    /**
+      * Hardware Semaphore used to protect internal data structures.
+      */
+    uint32_t hw_sem_idx;
+
+    /**
+     * @brief   Identifies the device on which this OpenEM instance is running.
+     */
+    ti_em_device_id_t my_device_idx;
+
+    /**
+     * @brief   Identifies the process in which this OpenEM instance is running.
+     */
+    ti_em_process_id_t my_process_idx;
+
+    /**
+      * Indexes of the pdsp threads running the FW scheduler.
+      */
+    ti_em_pdsp_id_t  pdsp_idx_tbl[TI_EM_SCHEDULER_THREAD_NUM];
+
+    /**
+      * pool configuration descriptors.
+      */
+    ti_em_pool_config_t pool_config_tbl[TI_EM_POOL_NUM];
+
+    /**
+     * Number of pools
+     */
+    uint32_t pool_num;
+
+    /**
+      * Hardware queue containing the private events used for Atomic Processing.
+      * This queue shall contain at least 256 private events.
+      */
+    ti_em_queue_id_t ap_region_queue_idx;
+
+    /**
+      * Hardware queue containing the private events used for Command Processing.
+      * This queue shall contain at least 32 private events.
+      * This queue may be the same as ap_region_queue_idx.
+      */
+    ti_em_queue_id_t cd_region_queue_idx;
+
+    /**
+      * Number of pdsp instances running the FW scheduler.
+      */
+    uint8_t pdsp_num;
+
+    /**
+      * Identifies the interrupt base index on which the scheduler will notify dispatching.
+      */
+    ti_em_interrupt_id_t hw_interrupt_base_idx;
+
+#ifdef TI_EM_GCC
+} __attribute__ ((aligned(CACHE_L1D_LINESIZE)));
+#else /* TI_EM_GCC */
+};
+#endif /* TI_EM_GCC */
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Event machine chaining configuration.
+ *
+ * @details This describes the EM configurable parameters which are required for the chaining.
+ */
+#ifndef TI_EM_GCC
+#pragma STRUCT_ALIGN (ti_em_chain_config_t_, 64);
+#pragma STRUCT_ALIGN (ti_em_chain_config_t_, 64)
+#endif
+struct ti_em_chain_config_t_
+{
+    /**
+      * Identifies the pool used for allocating very small events (event size <= size A).
+      * Size A corresponds to the buffer size of the pool.
+      * The received event uses one buffer from the pool.
+      */
+    em_pool_id_t pool_idx_size_a;
+
+    /**
+      * Identifies the pool used for allocating small events (size A <= event size <= size B).
+      * Size B corresponds to the buffer size of the pool.
+      * The received event uses one buffer from the pool.
+      */
+    em_pool_id_t pool_idx_size_b;
+
+    /**
+      * Identifies the pool used for allocating big events (size B <= event size <= size C).
+      * Size C corresponds to the buffer size of the pool.
+      * The received event uses one buffer from the pool.
+      */
+    em_pool_id_t pool_idx_size_c;
+
+    /**
+      * Identifies the pool used for allocating very big events (size C <= event size <= size D).
+      * Size D corresponds to the buffer size of the pool.
+      * The received event uses one buffer from the pool.
+      */
+    em_pool_id_t pool_idx_size_d;
+
+    /**
+      * Identifies the pool used for allocating even bigger events (size D <= event size).
+      * The received event uses one buffer (first) from the pool 'pool_idx_size_d'.
+      * The received event uses one or more buffers (second and next) from the pool 'pool_idx_overflow'.
+      */
+    em_pool_id_t pool_idx_overflow;
+
+    /**
+      * Pointer to the SRIO Configuration.
+      */
+    ti_em_chain_rio_config_t* rio_config_ptr;
+
+    /**
+      * Pointer to the 10 Gigabit Configuration.
+      */
+    ti_em_chain_xge_config_t* xge_config_ptr;
+
+    /**
+      * Pointer to the post-storing configuration.
+      */
+    ti_em_poststore_config_t* poststore_config_ptr;
+
+    /**
+      * Index for Packet DMA flows configuration. It has to map to a Multicore Navigator infrastructure Packet DMA.
+      */
+    ti_em_dma_id_t dma_idx;
+
+    /**
+      * Identifies the first relative DMA TX queue index used for the chaining flows.
+      */
+    ti_em_queue_id_t dma_tx_queue_base_idx;
+
+#ifdef TI_EM_GCC
+} __attribute__ ((aligned(CACHE_L1D_LINESIZE)));
+#else /* TI_EM_GCC */
+};
+#endif /* TI_EM_GCC */
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Event machine chaining configuration for xge.
+ *
+ * @details This describes the EM configurable parameters which are required for the chaining over xge.
+ */
+#ifndef TI_EM_GCC
+#pragma STRUCT_ALIGN (ti_em_chain_xge_config_t_, 64);
+#pragma STRUCT_ALIGN (ti_em_chain_xge_config_t_, 64)
+#endif
+struct ti_em_chain_xge_config_t_
+{
+    /**
+      * Index for Packet DMA flows configuration. It has to map to a Multicore Navigator infrastructure Packet DMA.
+      */
+    ti_em_dma_id_t dma_idx;
+
+    /**
+      * Specifies the Ethernet type.
+      */
+    uint8_t ether_type[2];
+
+    /**
+      * Specifies the MAC address of the device on which this OpenEM instance is running.
+      */
+    uint8_t my_mac_address[6];
+
+    /**
+      * Identifies the free queue for RX fragments.
+      */
+    ti_em_queue_id_t rx_fragment_free_queue_idx;
+
+    /**
+      * Identifies the free queue for RX headers.
+      */
+    ti_em_queue_id_t rx_header_free_queue_idx;
+
+    /**
+     * Identifies the first of TI_EM_XGE_VLAN_PRIO_NUM XGE RX miss queues
+     */
+     ti_em_queue_id_t rx_miss_queue_base_idx;
+    
+    
+    /**
+      * Identifies the free queue for TX fragments (without buffers).
+      */
+    ti_em_queue_id_t tx_fragment_free_queue_idx;
+
+    /**
+      * Identifies the free queue for TX headers
+      */
+    ti_em_queue_id_t tx_header_free_queue_idx;
+
+    /**
+      * Identifies the base index for the OpenEM instance to allocate the XGE TX divert queue.
+      */
+    ti_em_queue_id_t tx_divert_queue_base_idx;
+
+    /**
+      * Identifies a PDSP running the chaining firmware.
+      */
+    ti_em_pdsp_id_t pdsp_idx;
+
+    /**
+      * Specifies the VLAN priority Mask.
+      */
+    uint8_t vlan_prio_mask;
+#ifdef TI_EM_GCC
+} __attribute__ ((aligned(CACHE_L1D_LINESIZE)));
+#else /* TI_EM_GCC */
+};
+#endif /* TI_EM_GCC */
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Event machine chaining configuration for SRIO.
+ *
+ * @details This describes the EM configurable parameters which are required for the chaining over SRIO.
+ */
+#ifndef TI_EM_GCC
+#pragma STRUCT_ALIGN (ti_em_chain_rio_config_t_, 64);
+#pragma STRUCT_ALIGN (ti_em_chain_rio_config_t_, 64)
+#endif
+struct ti_em_chain_rio_config_t_
+{
+    /**
+      * Index for Packet DMA flows configuration. It has to map to a Multicore Navigator infrastructure Packet DMA.
+      */
+    ti_em_dma_id_t dma_idx;
+
+    /**
+      * Index for SRIO tx queue.
+      */
+    ti_em_queue_id_t dma_tx_queue_idx;
+    
+    /**
+      * Specifies the SRIO node index
+      */
+    uint8_t my_node_idx[2];
+    
+    /**
+      * Specifies the Service Class
+      */
+    uint8_t service_class;
+#ifdef TI_EM_GCC
+} __attribute__ ((aligned(CACHE_L1D_LINESIZE)));
+#else /* TI_EM_GCC */
+};
+#endif /* TI_EM_GCC */
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Event machine preload configuration.
+ *
+ * @details This describes the EM configurable parameters which are required for the preload.
+ */
+#ifndef TI_EM_GCC
+#pragma STRUCT_ALIGN (ti_em_preload_config_t_, 64);
+#pragma STRUCT_ALIGN (ti_em_preload_config_t_, 64)
+#endif
+struct ti_em_preload_config_t_
+{
+    /**
+      * Identifies the preload free queues.
+      */
+    ti_em_queue_id_t local_free_queue_idx_tbl[TI_EM_CORE_NUM];
+
+    /**
+      * Specifies the maximum number of bytes to preload if event type matches TI_EM_EVENT_TYPE_PRELOAD_ON_SIZE_A.
+      * Must be more than 0 and less than or equal to 8Kbytes.
+      */
+    size_t preload_size_a;
+
+    /**
+      * Specifies the maximum number of bytes to preload if event type matches TI_EM_EVENT_TYPE_PRELOAD_ON_SIZE_B.
+      * Must be more than 0 and less than or equal to 8Kbytes.
+      */
+    size_t preload_size_b;
+
+    /**
+      * Specifies the maximum number of bytes to preload if event type matches TI_EM_EVENT_TYPE_PRELOAD_ON_SIZE_B.
+      * Must be more than 0 and less than or equal to 1Mbytes.
+      */
+    size_t preload_size_c;
+#ifdef TI_EM_GCC
+} __attribute__ ((aligned(CACHE_L1D_LINESIZE)));
+#else /* TI_EM_GCC */
+};
+#endif /* TI_EM_GCC */
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Event machine post-storing configuration.
+ *
+ * @details This describes the EM configurable parameters which are required for the post-storing.
+ */
+#ifndef TI_EM_GCC
+#pragma STRUCT_ALIGN (ti_em_poststore_config_t_, 64);
+#pragma STRUCT_ALIGN (ti_em_poststore_config_t_, 64)
+#endif
+struct ti_em_poststore_config_t_
+{
+    /**
+      * Identifies the post-storing free queues. Array entry allocations per core are (core index * 2) + 0 and (core index * 2) + 1.
+      */
+    ti_em_queue_id_t local_free_queue_idx_tbl[2 * TI_EM_CORE_NUM];
+
+    /**
+      * Identifies the post-storing heap pointers. Array entry allocations per core are (core index * 2) + 0 and (core index * 2) + 1.
+      */
+    void * local_heap_ptr_tbl[2 * TI_EM_CORE_NUM];
+
+    /**
+      * Specifies the maximum number of bytes to post-store.
+      */
+    size_t poststore_size_max;
+
+#ifdef TI_EM_GCC
+} __attribute__ ((aligned(CACHE_L1D_LINESIZE)));
+#else /* TI_EM_GCC */
+};
+#endif /* TI_EM_GCC */
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * ...
+ *
+ * @details This describes the parameters required to configure a route over the 10 Gigabit Ethernet (XGE).
+ */
+struct ti_em_device_xge_route_t_
+{
+    /**
+      * Specifies the size of an event fragment.
+      */
+    size_t fragmentSize;
+
+    /**
+      * Specifies the MAC address.
+      */
+    uint8_t mac_address[6];
+
+    /**
+      * Specifies the stream.
+      */
+    uint8_t stream_idx[2];
+
+    /**
+      * Specifies the VLAN tag.
+      * Must match the VLAN priority .
+      */
+    uint8_t vlan_tag[4];
+};
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * ...
+ *
+ * @details This describes the parameters required to configure a route over the Serial Rapid IO.
+ */
+struct ti_em_device_rio_route_t_
+{
+    /**
+      * Specifies the node index.
+      */
+    uint8_t node_idx[2];
+
+};
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Event handle pair.
+ *
+ * @details This describes the event handle pair when combining/splitting events.
+ *
+ */
+struct ti_em_pair_t_
+{
+    /**
+      * Event machine head event in the pair.
+      */
+    em_event_t head_event_hdl;
+    /**
+      * Event machine tail event in the pair.
+      */
+    em_event_t tail_event_hdl;
+};
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Event handle pair.
+ *
+ * @details This describes the parameters required to configure a route to another process.
+ *
+ */
+struct ti_em_process_route_t_
+{
+    /**
+      * Index for Packet DMA flows configuration. It has to map to infrastructure Packet DMA.
+      */
+    ti_em_dma_id_t dma_idx;
+    /**
+      * Identifies the relative DMA TX queue index used for the chaining flow.
+      */
+    ti_em_queue_id_t dma_tx_queue_idx;
+};
+
+#endif /*EVENT_MACHINE_HW_TI_TYPES_H_*/
+
+
diff --git a/platform/linux-keystone2/prebuilts/openem/include/event_machine_hw_types.h b/platform/linux-keystone2/prebuilts/openem/include/event_machine_hw_types.h
new file mode 100644
index 0000000..b12b319
--- /dev/null
+++ b/platform/linux-keystone2/prebuilts/openem/include/event_machine_hw_types.h
@@ -0,0 +1,338 @@
+/*
+ *   Copyright (c) 2012, Nokia Siemens Networks
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *       * Redistributions of source code must retain the above copyright
+ *         notice, this list of conditions and the following disclaimer.
+ *       * Redistributions in binary form must reproduce the above copyright
+ *         notice, this list of conditions and the following disclaimer in the
+ *         documentation and/or other materials provided with the distribution.
+ *       * Neither the name of Nokia Siemens Networks nor the
+ *         names of its contributors may be used to endorse or promote products
+ *         derived from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ *   WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY
+ *   DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ *   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *   ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/**
+ *
+ * Contributors
+ *
+ * The initial developer of the original code is Nokia Siemens Networks.
+ *  The following contributors have made changes to 
+ *  the original code as described below.
+ * 
+ *----------------------------------------------------------------------------------------------
+ * Copyright (c) 2012, Texas Instruments Incorporated. All Rights Reserved. - http://www.ti.com/
+ * 
+ * From the original event_machine_hw_config.h.template , openem/event_machine_hw_types.h was
+ * created with:
+ *   - HW types definitions 
+ *   - Doxygen tags are added for API documentation generation.
+ *----------------------------------------------------------------------------------------------
+ *
+ */
+
+
+/*
+ *   Copyright (c) 2012, Nokia Siemens Networks
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *       * Redistributions of source code must retain the above copyright
+ *         notice, this list of conditions and the following disclaimer.
+ *       * Redistributions in binary form must reproduce the above copyright
+ *         notice, this list of conditions and the following disclaimer in the
+ *         documentation and/or other materials provided with the distribution.
+ *       * Neither the name of Nokia Siemens Networks nor the
+ *         names of its contributors may be used to endorse or promote products
+ *         derived from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ *   WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY
+ *   DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ *   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *   ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/**
+ *
+ * Contributors
+ *
+ * The initial developer of the original code is Nokia Siemens Networks.
+ *  The following contributors have made changes to 
+ *  the original code as described below.
+ * 
+ *----------------------------------------------------------------------------------------------
+ * Copyright (c) 2012, Texas Instruments Incorporated. All Rights Reserved. - http://www.ti.com/
+ *
+ * Elements of the Nokia Siemens Networks template files have been concatenated in this file and 
+ * configured to match TI implementation.
+ *----------------------------------------------------------------------------------------------
+ */
+
+ /**
+ * @file: event_machine_hw_types.h
+ *
+ * @brief
+ *    Open Event Machine HW specific types
+ *
+ */
+
+#ifndef EVENT_MACHINE_HW_TYPES_H
+#define EVENT_MACHINE_HW_TYPES_H
+
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/*
+ *
+ * HW specific types
+ ***************************************
+ */
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * The structure describes the queue types
+ *
+ */
+typedef enum em_queue_type_e
+{
+
+    /**
+     * @brief Application receives events one by one, non-concurrently to guarantee exclusive processing and ordering
+     */
+    EM_QUEUE_TYPE_UNDEF            = 0,
+
+    /**
+     * @brief Application receives events one by one, non-concurrently to guarantee exclusive processing and ordering
+     */
+    EM_QUEUE_TYPE_ATOMIC           = 1,  
+
+    /**
+     * @brief Application may receive events fully concurrently, egress event ordering (when processed in parallel) not guaranteed
+     */
+    EM_QUEUE_TYPE_PARALLEL         = 2,  
+
+    /**
+     * @brief Application may receive events concurrently, but system takes care of egress order (between two queues)
+     */
+    EM_QUEUE_TYPE_PARALLEL_ORDERED = 3   
+
+} em_queue_type_e;
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * The structure describes the portable queue priorities
+ *
+ */
+typedef enum em_queue_prio_e
+{
+    /**
+     * @brief Undefined
+     */
+    
+    EM_QUEUE_PRIO_UNDEF    = 0xFF, 
+    /**
+     * @brief lowest priority
+     */
+    EM_QUEUE_PRIO_LOWEST   =  0,    
+    
+    /**
+     * @brief low priority
+     */
+     EM_QUEUE_PRIO_LOW     =  12,
+
+     /**
+     * @brief normal priority
+     */
+    EM_QUEUE_PRIO_NORMAL   =  13,
+    
+    /**
+     * @brief high priority
+     */
+    EM_QUEUE_PRIO_HIGH     =  14,
+    
+    /**
+     * @brief highest priority
+     */
+    EM_QUEUE_PRIO_HIGHEST  =  15
+
+} em_queue_prio_e;
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * The structure lists the error codes
+ *
+ */
+typedef enum em_status_e
+{
+
+    /**
+     * @brief Illegal context for this function call
+     */
+    EM_ERR_BAD_CONTEXT      = 1, 
+
+    /**
+     * @brief Illegal (eo, queue, ...) state for this function call
+     */
+    EM_ERR_BAD_STATE        = 2,   
+
+    /**
+     * @brief ID not from a valid range
+     */
+    EM_ERR_BAD_ID           = 3,   
+
+    /**
+     * @brief Resource allocation failed
+     */
+    EM_ERR_ALLOC_FAILED     = 4, 
+
+    /**
+     * @brief Resource already reserved by someone else
+     */
+    EM_ERR_NOT_FREE         = 5,   
+
+    /**
+     * @brief Resource not found
+     */
+    EM_ERR_NOT_FOUND        = 6,   
+
+    /**
+     * @brief Value over the limit
+     */
+    EM_ERR_TOO_LARGE        = 7, 
+
+    /**
+     * @brief Failure in a library function
+     */
+    EM_ERR_LIB_FAILED       = 8,
+
+    /**
+     * @brief Implementation missing (placeholder)
+     */
+    EM_ERR_NOT_IMPLEMENTED  = 9,
+
+    /**
+     * @brief Pointer from bad memory area (e.g. NULL)
+     */
+    EM_ERR_BAD_POINTER      = 10,
+
+
+    /**
+     * @brief Other error. This is the last error code (for bounds checking).
+     */
+    EM_ERR        
+
+} em_status_e;
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * The structure describes the major event types
+ *
+ */
+typedef enum em_event_type_major_e
+{
+
+    /**
+     * @brief
+     */
+    EM_EVENT_TYPE_UNDEF  = 0,
+
+    /**
+     * @brief event from SW (EO)
+     */
+    EM_EVENT_TYPE_SW     = 1 << 24,
+
+    /**
+     * @brief event from packet HW
+     */
+    EM_EVENT_TYPE_PACKET = 2 << 24, 
+
+    /**
+     * @brief event from timer HW
+     */
+    EM_EVENT_TYPE_TIMER  = 3 << 24, 
+
+    /**
+     * @brief event from crypto HW
+     */
+    EM_EVENT_TYPE_CRYPTO = 4 << 24 
+
+} em_event_type_major_e;
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * The structure describes the Minor event types for the major EM_EVENT_TYPE_SW type
+ *
+ */
+typedef enum em_event_type_sw_minor_e
+{
+
+    /**
+     * @brief
+     */
+    EM_EVENT_TYPE_SW_DEFAULT  = 1
+
+} em_event_type_sw_minor_e;
+
+/**
+ * @ingroup DOC_api_generic
+ * 
+ * Event type
+ *
+ * In Event Machine application processing is driven by events. An event 
+ * describes a piece of work. Structure of an event is implementation and
+ * event type specific. It may be a directly accessible buffer of memory, 
+ * a descriptor containing a list of buffer pointers, a descriptor of 
+ * a packet buffer, etc.
+ *
+ * Applications use event type to interpret the event structure.
+ *
+ * Since em_event_t may not carry a direct pointer value to the event
+ * structure, em_event_pointer() must be used to translate an event to
+ * an event structure pointer (for maintaining portability).
+ *
+ * @see em_event_pointer()
+
+ */
+typedef uint32_t em_event_t;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif
+
diff --git a/platform/linux-keystone2/prebuilts/openem/include/event_machine_macros.h b/platform/linux-keystone2/prebuilts/openem/include/event_machine_macros.h
new file mode 100644
index 0000000..fe7117f
--- /dev/null
+++ b/platform/linux-keystone2/prebuilts/openem/include/event_machine_macros.h
@@ -0,0 +1,514 @@
+/*
+ *   Copyright (c) 2012, Nokia Siemens Networks
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *       * Redistributions of source code must retain the above copyright
+ *         notice, this list of conditions and the following disclaimer.
+ *       * Redistributions in binary form must reproduce the above copyright
+ *         notice, this list of conditions and the following disclaimer in the
+ *         documentation and/or other materials provided with the distribution.
+ *       * Neither the name of Nokia Siemens Networks nor the
+ *         names of its contributors may be used to endorse or promote products
+ *         derived from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ *   WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY
+ *   DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ *   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *   ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/**
+ *
+ * Contributors
+ *
+ * The initial developer of the original code is Nokia Siemens Networks.
+ *  The following contributors have made changes to 
+ *  the original code as described below.
+ * 
+ *----------------------------------------------------------------------------------------------
+ * Copyright (c) 2012, Texas Instruments Incorporated. All Rights Reserved. - http://www.ti.com/
+ * 
+ * Changes were done on the original NSN header files in order to avoid 
+ * circular dependencies when called in the TI implementation files.
+ *
+ * From the original event_machine_types.h, openem/ti/event_machine_macros.h was
+ * created with:
+ *   - Constants definitions
+ *   - Doxygen tags are added for API documentation generation.
+ *----------------------------------------------------------------------------------------------
+ *
+ */
+
+
+/**
+ * @file: event_machine_macros.h
+ *
+ * @brief
+ *    Open Event Machine public constant definitions
+ */
+
+#ifndef EVENT_MACHINE_MACROS_H_
+#define EVENT_MACHINE_MACROS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <event_machine_hw_macros.h>
+
+#ifdef EM_64_BIT
+
+/*
+ * Printf formats
+ */
+/**
+ * @ingroup DOC_api_generic
+ *
+ * em_eo_t printf format 
+ */
+#define PRI_EO      PRIu64       
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * em_queue_t printf format 
+ */
+#define PRI_QUEUE   PRIu64
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * em_queue_group_t printf format 
+ */
+#define PRI_QGRP    PRIu64        
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Invalid EO id 
+ */
+#define EM_EO_UNDEF             EM_UNDEF_U64    
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Invalid queue 
+ */
+#define EM_QUEUE_UNDEF          EM_UNDEF_U64    
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Invalid queue group 
+ */
+#define EM_QUEUE_GROUP_UNDEF    EM_UNDEF_U64    
+
+
+#elif defined(EM_32_BIT)
+
+/*
+ * Printf formats
+ */
+/**
+ * @ingroup DOC_api_generic
+ *
+ * em_eo_t printf format          
+ */
+#define PRI_EO       PRIu32                     
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * em_queue_t printf format       
+ */
+#define PRI_QUEUE    PRIu32                     
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * em_queue_group_t printf format 
+ */
+#define PRI_QGRP     PRIu32                     
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Invalid EO id 
+ */
+#define EM_EO_UNDEF      EM_UNDEF_U32           
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Invalid queue 
+ */
+#define EM_QUEUE_UNDEF   EM_UNDEF_U32           
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Invalid queue group id 
+ */
+#define EM_QUEUE_GROUP_UNDEF     EM_UNDEF_U32   
+
+
+#else
+
+  #error Missing architecture definition. Define EM_64_BIT or EM_32_BIT!
+
+#endif
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Operation successful 
+ */
+#define EM_OK   0      
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Operation not successful 
+ */
+#define EM_ERROR 0xffffffff
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * All EM internal error scopes should have bit 31 set
+ * NOTE: High bit is RESERVED for EM internal escopes and should not be
+ * used by the application.
+ */
+#define EM_ESCOPE_BIT                  (0x80000000u)
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Test if the error scope identifies an EM function (API or other internal)
+ */
+#define EM_ESCOPE(escope)              (EM_ESCOPE_BIT & (escope))
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Mask selects the high byte of the 32-bit escope
+ */
+#define EM_ESCOPE_MASK                 (0xFF000000)
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * EM API functions error scope type
+ */
+#define EM_ESCOPE_API_TYPE             (0xFFu)
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * EM API functions error scope mask
+ */
+#define EM_ESCOPE_API_MASK             (EM_ESCOPE_BIT | (EM_ESCOPE_API_TYPE << 24))
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Test if the error scope identifies an API function
+ */
+#define EM_ESCOPE_API(escope)          (((escope) & EM_ESCOPE_MASK) == EM_ESCOPE_API_MASK)
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Error scope for the em_queue_create API.
+ *
+ */
+#define EM_ESCOPE_QUEUE_CREATE                    (EM_ESCOPE_API_MASK | 0x0001)
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Error scope for the em_queue_create_static API.
+ *
+ */
+#define EM_ESCOPE_QUEUE_CREATE_STATIC             (EM_ESCOPE_API_MASK | 0x0002)
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Error scope for the em_queue_delete API.
+ *
+ */
+#define EM_ESCOPE_QUEUE_DELETE                    (EM_ESCOPE_API_MASK | 0x0003)
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Error scope for the em_queue_enable API.
+ *
+ */
+#define EM_ESCOPE_QUEUE_ENABLE                    (EM_ESCOPE_API_MASK | 0x0004)
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Error scope for the em_queue_enable_all API.
+ *
+ */
+#define EM_ESCOPE_QUEUE_ENABLE_ALL                (EM_ESCOPE_API_MASK | 0x0005)
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Error scope for the em_queue_disable API.
+ *
+ */
+#define EM_ESCOPE_QUEUE_DISABLE                   (EM_ESCOPE_API_MASK | 0x0006)
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Error scope for the em_queue_disable_all API.
+ *
+ */
+#define EM_ESCOPE_QUEUE_DISABLE_ALL               (EM_ESCOPE_API_MASK | 0x0007)
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Error scope for the em_queue_set_context API.
+ *
+ */
+#define EM_ESCOPE_QUEUE_SET_CONTEXT               (EM_ESCOPE_API_MASK | 0x0008)
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Error scope for the em_queue_get_context API.
+ *
+ */
+#define EM_ESCOPE_QUEUE_GET_CONTEXT               (EM_ESCOPE_API_MASK | 0x0009)
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Error scope for the em_queue_get_name API.
+ *
+ */
+#define EM_ESCOPE_QUEUE_GET_NAME                  (EM_ESCOPE_API_MASK | 0x000A)
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Error scope for the em_queue_get_priority API.
+ *
+ */
+#define EM_ESCOPE_QUEUE_GET_PRIORITY              (EM_ESCOPE_API_MASK | 0x000B)
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Error scope for the em_queue_get_type API.
+ *
+ */
+#define EM_ESCOPE_QUEUE_GET_TYPE                  (EM_ESCOPE_API_MASK | 0x000C)
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Error scope for the em_queue_group_create API.
+ *
+ */
+#define EM_ESCOPE_QUEUE_GET_GROUP                 (EM_ESCOPE_API_MASK | 0x000D)
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Error scope for the em_queue_group_create API.
+ *
+ */
+#define EM_ESCOPE_QUEUE_GROUP_CREATE              (EM_ESCOPE_API_MASK | 0x0101)
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Error scope for the em_queue_group_delete API.
+ *
+ */
+#define EM_ESCOPE_QUEUE_GROUP_DELETE              (EM_ESCOPE_API_MASK | 0x0102)
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Error scope for the em_queue_group_modify API.
+ *
+ */
+#define EM_ESCOPE_QUEUE_GROUP_MODIFY              (EM_ESCOPE_API_MASK | 0x0103)
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Error scope for the em_queue_group_find API.
+ *
+ */
+#define EM_ESCOPE_QUEUE_GROUP_FIND                (EM_ESCOPE_API_MASK | 0x0104)
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Error scope for the em_queue_group_mask API.
+ *
+ */
+#define EM_ESCOPE_QUEUE_GROUP_MASK                (EM_ESCOPE_API_MASK | 0x0105)
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Error scope for the em_eo_create API.
+ *
+ */
+#define EM_ESCOPE_EO_CREATE                       (EM_ESCOPE_API_MASK | 0x0201)
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Error scope for the em_eo_delete API.
+ *
+ */
+#define EM_ESCOPE_EO_DELETE                       (EM_ESCOPE_API_MASK | 0x0202)
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Error scope for the em_eo_get_name API.
+ *
+ */
+#define EM_ESCOPE_EO_GET_NAME                     (EM_ESCOPE_API_MASK | 0x0203)
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Error scope for the em_eo_add_queue API.
+ *
+ */
+#define EM_ESCOPE_EO_ADD_QUEUE                    (EM_ESCOPE_API_MASK | 0x0204)
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Error scope for the em_eo_remove_queue API.
+ *
+ */
+#define EM_ESCOPE_EO_REMOVE_QUEUE                 (EM_ESCOPE_API_MASK | 0x0205)
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Error scope for the em_eo_register_error_handler API.
+ *
+ */
+#define EM_ESCOPE_EO_REGISTER_ERROR_HANDLER       (EM_ESCOPE_API_MASK | 0x0206)
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Error scope for the em_eo_unregister_error_handler API.
+ *
+ */
+#define EM_ESCOPE_EO_UNREGISTER_ERROR_HANDLER     (EM_ESCOPE_API_MASK | 0x0207)
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Error scope for the em_eo_start API.
+ *
+ */
+#define EM_ESCOPE_EO_START                        (EM_ESCOPE_API_MASK | 0x0208)
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Error scope for the em_eo_stop API.
+ *
+ */
+#define EM_ESCOPE_EO_STOP                         (EM_ESCOPE_API_MASK | 0x0209)
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Error scope for the em_core_id API.
+ *
+ */
+#define EM_ESCOPE_CORE_ID                         (EM_ESCOPE_API_MASK | 0x0301)
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Error scope for the em_core_count API.
+ *
+ */
+#define EM_ESCOPE_CORE_COUNT                      (EM_ESCOPE_API_MASK | 0x0302)
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Error scope for the em_alloc API.
+ *
+ */
+#define EM_ESCOPE_ALLOC                           (EM_ESCOPE_API_MASK | 0x0401)
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Error scope for the em_free API.
+ *
+ */
+#define EM_ESCOPE_FREE                            (EM_ESCOPE_API_MASK | 0x0402)
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Error scope for the em_send API.
+ *
+ */
+#define EM_ESCOPE_SEND                            (EM_ESCOPE_API_MASK | 0x0403)
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Error scope for the em_atomic_processing_end API.
+ *
+ */
+#define EM_ESCOPE_ATOMIC_PROCESSING_END           (EM_ESCOPE_API_MASK | 0x0404)
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Error scope for the em_register_error_handler API.
+ *
+ */
+#define EM_ESCOPE_REGISTER_ERROR_HANDLER          (EM_ESCOPE_API_MASK | 0x0501)
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Error scope for the em_unregister_error_handler API.
+ *
+ */
+#define EM_ESCOPE_UNREGISTER_ERROR_HANDLER        (EM_ESCOPE_API_MASK | 0x0502)
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Error scope for the em_error API.
+ *
+ */
+#define EM_ESCOPE_ERROR                           (EM_ESCOPE_API_MASK | 0x0503)
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Size of the core mask in bits
+ */
+#define EM_CORE_MASK_SIZE  64
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* EVENT_MACHINE_MACROS_H_ */
+
diff --git a/platform/linux-keystone2/prebuilts/openem/include/event_machine_sw.h b/platform/linux-keystone2/prebuilts/openem/include/event_machine_sw.h
new file mode 100644
index 0000000..4c284ac
--- /dev/null
+++ b/platform/linux-keystone2/prebuilts/openem/include/event_machine_sw.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2012, Texas Instruments Incorporated - http://www.ti.com/
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *       * Redistributions of source code must retain the above copyright
+ *         notice, this list of conditions and the following disclaimer.
+ *       * Redistributions in binary form must reproduce the above copyright
+ *         notice, this list of conditions and the following disclaimer in the
+ *         documentation and/or other materials provided with the distribution.
+ *       * Neither the name of Texas Instruments Incorporated nor the
+ *         names of its contributors may be used to endorse or promote products
+ *         derived from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ *   WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY
+ *   DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ *   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *   ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/**
+ * @file: event_machine_sw.h
+ *
+ * @brief
+ *    Open Event Machine SW public include file
+ *
+ */
+
+#ifndef EVENT_MACHINE_SW_H
+#define EVENT_MACHINE_SW_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <event_machine_sw_config.h>
+
+#include <event_machine_sw_ti.h>
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* EVENT_MACHINE_SW_H */
+
+
diff --git a/platform/linux-keystone2/prebuilts/openem/include/event_machine_sw_config.h b/platform/linux-keystone2/prebuilts/openem/include/event_machine_sw_config.h
new file mode 100644
index 0000000..1cf5913
--- /dev/null
+++ b/platform/linux-keystone2/prebuilts/openem/include/event_machine_sw_config.h
@@ -0,0 +1,155 @@
+/*
+ *   Copyright (c) 2012, Nokia Siemens Networks
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *       * Redistributions of source code must retain the above copyright
+ *         notice, this list of conditions and the following disclaimer.
+ *       * Redistributions in binary form must reproduce the above copyright
+ *         notice, this list of conditions and the following disclaimer in the
+ *         documentation and/or other materials provided with the distribution.
+ *       * Neither the name of Nokia Siemens Networks nor the
+ *         names of its contributors may be used to endorse or promote products
+ *         derived from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ *   WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY
+ *   DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ *   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *   ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/**
+ *
+ * Contributors
+ *
+ * The initial developer of the original code is Nokia Siemens Networks.
+ *  The following contributors have made changes to 
+ *  the original code as described below.
+ * 
+ *----------------------------------------------------------------------------------------------
+ * Copyright (c) 2012, Texas Instruments Incorporated. All Rights Reserved. - http://www.ti.com/
+ * 
+ * From the original event_machine_hw_config.h.template , openem/event_machine_sw_config.h was
+ * created with:
+ *   - SW macro definitions with the TI optimized implementation values
+ *   - Doxygen tags are added for API documentation generation.
+ *----------------------------------------------------------------------------------------------
+ *
+ */
+
+
+/**
+ * @file: event_machine_sw_config.h
+ *
+ * @brief
+ *    Open Event Machine SW specific configuration
+ *
+ */
+
+#ifndef EVENT_MACHINE_SW_CONFIG_H
+#define EVENT_MACHINE_SW_CONFIG_H
+
+#include <event_machine_hw_ti_macros.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ *
+ * EM scaling
+ ***************************************
+ */
+
+
+
+/**
+ * @ingroup DOC_api_generic
+ * 
+ * Maximum number of queues supported by the event machine.
+ *
+ * @note This value can be modified by an application. But the event machine library needs to be recompiled.
+ *
+ */
+#define EM_MAX_QUEUES               (TI_EM_QUEUE_SET_NUM * TI_EM_QUEUE_NUM_IN_SET)
+
+/**
+ * @ingroup DOC_api_generic
+ * 
+ * Max queue name string length.
+ *
+ * @note This value can be modified by an application. But the event machine library needs to be recompiled.
+ *
+ */
+#define EM_QUEUE_NAME_LEN           (32)
+
+
+/**
+ * @ingroup DOC_api_generic
+ * 
+ * Maximum number of execution objects supported by the event machine. EM_MAX_EOS <= TI_EM_EO_NUM_MAX.
+ *
+ * @note This value can be modified by an application. But the event machine library needs to be recompiled.
+ *
+ */
+#define EM_MAX_EOS                  (256)
+
+
+/**
+ * @ingroup DOC_api_generic
+ * 
+ * Max EO name string lenght.
+ *
+ * @note This value can be modified by an application. But the event machine library needs to be recompiled.
+ */
+#define EM_EO_NAME_LEN              (32)
+
+
+/**
+ * @ingroup DOC_api_generic
+ * 
+ * Maximum number of event groups supported by the event machine. EM_MAX_EVENT_GROUPS <= TI_EM_EVENT_GROUP_NUM_MAX.
+ *
+ * @note This value can be modified by an application. But the event machine library needs to be recompiled.
+ *
+ */
+#define EM_MAX_EVENT_GROUPS         (1024)
+
+
+/**
+ * @ingroup DOC_api_generic
+ * 
+ * Maximum number of event notifications supported by one event group.
+ *
+ */
+#define EM_EVENT_GROUP_MAX_NOTIF    (8)
+
+
+/**
+ * @ingroup DOC_api_generic
+ * 
+ * Max queue group name string lenght.
+ *
+ * @note This value can be modified by an application. But the event machine library needs to be recompiled.
+ */
+#define EM_QUEUE_GROUP_NAME_LEN    (8u)
+
+
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif
diff --git a/platform/linux-keystone2/prebuilts/openem/include/event_machine_sw_ti.h b/platform/linux-keystone2/prebuilts/openem/include/event_machine_sw_ti.h
new file mode 100644
index 0000000..9d81ddc
--- /dev/null
+++ b/platform/linux-keystone2/prebuilts/openem/include/event_machine_sw_ti.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2012, Texas Instruments Incorporated - http://www.ti.com/
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *       * Redistributions of source code must retain the above copyright
+ *         notice, this list of conditions and the following disclaimer.
+ *       * Redistributions in binary form must reproduce the above copyright
+ *         notice, this list of conditions and the following disclaimer in the
+ *         documentation and/or other materials provided with the distribution.
+ *       * Neither the name of Texas Instruments Incorporated nor the
+ *         names of its contributors may be used to endorse or promote products
+ *         derived from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ *   WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY
+ *   DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ *   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *   ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/**
+ * @file: event_machine_sw_ti.h
+ *
+ * @brief
+ *    Open Event Machine SW TI specific public include file
+ *
+ */
+
+#ifndef EVENT_MACHINE_SW_TI_H
+#define EVENT_MACHINE_SW_TI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <event_machine_sw_ti_config.h>
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* EVENT_MACHINE_SW_TI_H */
+
+
diff --git a/platform/linux-keystone2/prebuilts/openem/include/event_machine_sw_ti_config.h b/platform/linux-keystone2/prebuilts/openem/include/event_machine_sw_ti_config.h
new file mode 100644
index 0000000..c5cc296
--- /dev/null
+++ b/platform/linux-keystone2/prebuilts/openem/include/event_machine_sw_ti_config.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2012, Texas Instruments Incorporated - http://www.ti.com/
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *       * Redistributions of source code must retain the above copyright
+ *         notice, this list of conditions and the following disclaimer.
+ *       * Redistributions in binary form must reproduce the above copyright
+ *         notice, this list of conditions and the following disclaimer in the
+ *         documentation and/or other materials provided with the distribution.
+ *       * Neither the name of Texas Instruments Incorporated nor the
+ *         names of its contributors may be used to endorse or promote products
+ *         derived from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ *   WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY
+ *   DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ *   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *   ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/**
+ * @file: event_machine_sw_ti_config.h
+ *
+ * @brief
+ *    Open Event Machine SW TI specific constant definitions
+ *
+ */
+
+#ifndef EVENT_MACHINE_SW_TI_CONFIG_H_
+#define EVENT_MACHINE_SW_TI_CONFIG_H_
+
+/**
+ * @ingroup DOC_api_specific
+ *
+ * Maximum number of buffer pools that can be specified.
+ *
+ * @note This value can be modified by an application. But the event machine library needs to be recompiled.
+ */
+#define TI_EM_POOL_NUM                  (32u)
+
+#endif /*EVENT_MACHINE_SW_TI_CONFIG_H_*/
diff --git a/platform/linux-keystone2/prebuilts/openem/include/event_machine_types.h b/platform/linux-keystone2/prebuilts/openem/include/event_machine_types.h
new file mode 100644
index 0000000..5584c6c
--- /dev/null
+++ b/platform/linux-keystone2/prebuilts/openem/include/event_machine_types.h
@@ -0,0 +1,549 @@
+/*
+ *   Copyright (c) 2012, Nokia Siemens Networks
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *       * Redistributions of source code must retain the above copyright
+ *         notice, this list of conditions and the following disclaimer.
+ *       * Redistributions in binary form must reproduce the above copyright
+ *         notice, this list of conditions and the following disclaimer in the
+ *         documentation and/or other materials provided with the distribution.
+ *       * Neither the name of Nokia Siemens Networks nor the
+ *         names of its contributors may be used to endorse or promote products
+ *         derived from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ *   WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY
+ *   DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ *   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *   ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/**
+ *
+ * Contributors
+ *
+ * The initial developer of the original code is Nokia Siemens Networks.
+ *  The following contributors have made changes to 
+ *  the original code as described below.
+ * 
+ *----------------------------------------------------------------------------------------------
+ * Copyright (c) 2012, Texas Instruments Incorporated. All Rights Reserved. - http://www.ti.com/
+ * 
+ * Changes were done on the original NSN header files in order to avoid 
+ * circular dependencies when called in the TI implementation files.
+ *
+ * This file is a merge of the type definitions from the original
+ * event_machine.h and event_machine_types.h files.
+ * The list of changes are:
+ *   - Doxygen tags are added for API documentation generation.
+ *----------------------------------------------------------------------------------------------
+ *
+ */
+
+
+/**
+ * @file: event_machine_types.h
+ *
+ * @brief
+ *    Open Event Machine basic types
+ */
+
+#ifndef EVENT_MACHINE_TYPES_H_
+#define EVENT_MACHINE_TYPES_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#include <inttypes.h>
+#include <stdarg.h>
+#include <stdlib.h>
+#include <event_machine_macros.h>
+#include <event_machine_hw_types.h>
+
+#ifdef EM_64_BIT
+
+/*
+ * Optimize EM for 64 bit architecture
+ * =====================================
+ */
+
+ /* page  64 bit version */
+/**
+ *
+ * @page DOC_intro Introduction
+ * @section page_version 64 bit version
+ * This is documentation represent the 64 bit version of Event Machine API.
+ * Define EM_64_BIT or EM_32_BIT to select between 64 and 32 bit versions.
+ *
+ */
+
+
+/*
+ * Printf formats
+ */
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ *  Execution Object identifier
+ *
+ * @see em_eo_create() 
+ */
+typedef uint64_t em_eo_t;
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Queue identifier
+ *
+ * @see em_queue_create(), em_receive_func_t(), em_send()
+ */
+typedef uint64_t em_queue_t;
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Queue group identifier
+ *
+ * Each queue belongs to one queue group, that defines a core mask for scheduling
+ * events, i.e. define which cores participate in the load balancing. Group can
+ * also allow only a single core for no load balancing.
+ *
+ * Groups needs to be created as needed. One default group (EM_QUEUE_GROUP_DEFAULT)
+ * always exists, and that allows scheduling to all the cores running this execution
+ * binary instance.
+ *
+ * @see em_queue_group_create()
+ */
+typedef uint64_t em_queue_group_t;
+
+
+
+
+#elif defined(EM_32_BIT)
+/*
+ * Optimize EM for 32 bit architecture
+ * =====================================
+ */
+
+ /* @page page_version 32 bit version */
+
+/**
+ *
+ * @page DOC_intro Introduction
+ * @section page_version 32 bit version
+ * This is documentation represent the 32 bit version of Event Machine API.
+ * Define EM_64_BIT or EM_32_BIT to select between 64 and 32 bit versions.
+ *
+ */
+
+
+/* ************* 32 bit ************************ */
+
+
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Execution Object identifier
+ *
+ * @see em_eo_create() 
+ */
+typedef uint32_t em_eo_t;
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Queue identifier
+ *
+ * @see em_queue_create(), em_receive_func_t(), em_send()
+ */
+typedef uint32_t em_queue_t;
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Queue group identifier
+ *
+ * Each queue belongs to one queue group, that defines a core mask for scheduling
+ * events, i.e. define which cores participate in the load balancing. Group can
+ * also allow only a single core for no load balancing.
+ *
+ * Groups needs to be created as needed. One default group (EM_QUEUE_GROUP_DEFAULT)
+ * always exists, and that allows scheduling to all the cores running this execution
+ * binary instance.
+ *
+ * @see em_queue_group_create()
+ */
+typedef uint32_t em_queue_group_t;
+
+
+
+#else
+
+  #error Missing architecture definition. Define EM_64_BIT or EM_32_BIT!
+
+  /**
+   *
+   * @page page_version 64/32 bit version not selected
+   * This is documentation has not selected between 64/32 bit version of Event Machine API.
+   * Some types might be missing. Define EM_64_BIT or EM_32_BIT to select between 64 and 32 bit versions.
+   *
+   */
+   
+#endif
+
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Error/Status code.
+ * EM_OK (0) is the general code for success, other values
+ * describe failed operation.
+ * 
+ * @see event_machine_hw_config.h, em_error_handler_t(), em_error()
+ */
+typedef uint32_t em_status_t;
+
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Error scope.
+ *
+ * Identifies the error scope for interpreting error codes and variable arguments.
+ * 
+ * @see em_error_handler_t(), em_error()
+ */
+typedef uint32_t em_escope_t;
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Queue type.
+ *
+ * Affects the scheduling principle
+ *
+ * @see em_queue_create(), event_machine_hw_config.h
+ */
+typedef uint32_t em_queue_type_t;
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Queue priority class
+ *
+ * Queue priority defines a system dependent QoS class, not just an absolute
+ * priority. EM gives freedom to implement the actual scheduling disciplines
+ * and the corresponding numeric values as needed, i.e. the actual values are
+ * system dependent and thus not portable, but the 5 pre-defined enums
+ * (em_queue_prio_e) are always valid.
+ * Application platform or middleware needs to define and distribute the
+ * other available values.
+ *
+ * @see em_queue_create(), event_machine_hw_config.h
+ */
+typedef uint32_t em_queue_prio_t;
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Event type. This is given to application for each received
+ * event and also needed for event allocation.
+ * It's an integer, but split into major and minor part.
+ * major-field categorizes the event and minor is
+ * more detailed system specific description.
+ * Major-part will not change by HW, but minor can be HW/SW platform
+ * specific and thus could be split into more sub-fields as needed.
+ * Application should use the access functions for reading major 
+ * and minor part.
+ *
+ * The only event type with defined content is EM_EVENT_TYPE_SW with
+ * minor type 0, which needs to be portable (direct pointer to data).
+ *
+ * @see em_get_type_major(), em_get_type_minor(), em_receive_func_t()
+ */
+typedef uint32_t em_event_type_t;
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Memory pool id.
+ *
+ * Defines memory pool in em_alloc(). Default pool id is defined by
+ * EM_POOL_DEFAULT.
+ *
+ * @see em_alloc(), event_machine_hw_config.h
+ */
+typedef uint32_t em_pool_id_t;
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Type for queue group core mask.
+ * Each bit represents one core, core 0 is the lsb (1 << em_core_id())
+ * Note, that EM will enumerate the core identifiers to always start from 0 and
+ * be contiguous meaning the core numbers are not necessarily physical.
+ * This type can handle up to 64 cores.
+ * 
+ * @see em_queue_group_create()
+ */
+typedef union em_core_mask_t em_core_mask_t;
+
+union em_core_mask_t
+{
+  uint8_t   u8[EM_CORE_MASK_SIZE / 8];
+  uint16_t u16[EM_CORE_MASK_SIZE / 16];
+  uint32_t u32[EM_CORE_MASK_SIZE / 32];
+  uint64_t u64[EM_CORE_MASK_SIZE / 64];
+};
+
+
+
+
+
+/**
+ * \internal
+ *--------------------------------------------------------------------------
+ * Copyright (c) 2012, Texas Instruments Incorporated - http://www.ti.com/
+ * This part of file is a copy from the original event_machine.h 
+ *--------------------------------------------------------------------------
+ * \endinternal
+ */
+
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Notification structure allows user to define a notification event and
+ * destination queue pair. EM will notify user by sending the event into
+ * the queue.
+ */
+typedef struct em_notif_t
+{
+  em_event_t  event;  /**< User defined notification event */
+  em_queue_t  queue;  /**< Destination queue */
+
+} em_notif_t;
+
+
+
+/*
+ *
+ * From Event Machine to application interface (call-back functions)
+ * ----------------------------------------------------------------------------
+ * 
+ */
+
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Receive event
+ *
+ * Application receives events through the EO receive function. It implements main part of
+ * the application logic. EM calls the receive function when it has dequeued an event from one
+ * of the EO's queues. Application processes the event and returns immediately (in 
+ * run-to-completion fashion).
+ *
+ * On multicore systems several events (from the same or different queues) may be dequeued
+ * in parallel and thus same receive function may be executed concurrently on several cores.
+ * Parallel execution may be limited by queue group setup or using queues with atomic
+ * scheduling mode.
+ *
+ * EO and queue context pointers are user defined (in EO and queue creation time) and 
+ * may be used any way needed. For example, EO context may be used to store global EO state
+ * information, which is common to all queues and events. In addition, queue context may be
+ * used to store queue (or user data flow) specific state data. EM never touches the data, 
+ * just passes the pointers. 
+ *
+ * Event (handle) must be converted to an event structure pointer with em_event_pointer().
+ * Event type specifies the event structure, which is implementation or application specific.
+ * Queue id specifies the queue which the event was dequeued from.
+ *
+ * @param eo_ctx        EO context data. The pointer is passed in em_eo_create(), EM does not touch the data.
+ * @param event         Event handle
+ * @param type          Event type
+ * @param queue         Queue from which this event came from
+ * @param q_ctx         Queue context data. The pointer is passed in em_queue_set_context(), EM does not touch the data.
+ *
+ * @see em_event_pointer(), em_free(), em_alloc(), em_send(), em_queue_set_context(), em_eo_create()
+ */
+typedef void (*em_receive_func_t)(void* eo_ctx, em_event_t event, em_event_type_t type, em_queue_t queue, void* q_ctx);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Execution object start, global.
+ * 
+ * If load balancing/several cores share the EO, this function is called
+ * once on one core only (any). Purpose of this global start is to provide
+ * a placeholder for first level initialization, like allocating memory and
+ * initializing shared data. After this global start returns, the core local
+ * version (if defined), is called (see em_start_local_func_t below). If there
+ * is no core local start, then event dispatching is immediately enabled.
+ *
+ * If Execution object does not return EM_OK,
+ * the system will not call the core local init and will not enable event
+ * dispatching.
+ *
+ * This function should never be called directly from the application,
+ * but using the, which maintains state information!
+ *
+ * @param eo_ctx        Execution object internal state/instance data
+ * @param eo            Execution object id
+ *
+ * @return EM_OK if successful.
+ *
+ * @see em_eo_start(), em_eo_create()
+ */
+typedef em_status_t (*em_start_func_t)(void* eo_ctx, em_eo_t eo);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Execution object start, core local.
+ * 
+ * This is similar to the global start above, but this one is called after the
+ * global start has completed and is called on all cores.
+ *
+ * Purpose of this optional local start is to work as a placeholder for
+ * core local initialization, e.g. allocating core local memory for example.
+ * The global start is only called on one core. The use of local start is
+ * optional.
+ * Note, that application should never directly call this function, this
+ * will be called via em_eo_start().
+ *
+ * If this does not return EM_OK on all involved cores, the event dispatching
+ * is not enabled.
+ *
+ * @param eo_ctx        Execution object internal state/instance data
+ * @param eo            Execution object id
+ *
+ * @return EM_OK if successful.
+ *
+ * @see em_eo_start(), em_eo_create()
+ */
+typedef em_status_t (*em_start_local_func_t)(void* eo_ctx, em_eo_t eo);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Execution object stop, core local.
+ *
+ * If load balancing/several cores share the EO, this function is
+ * called once on each core before the global stop (reverse order of start).
+ * System disables event dispatching before calling this
+ * and also makes sure this does not get called before the core
+ * has been notified the stop condition for this EO (won't dispatch new events)
+ * Return value is only for logging purposes, EM does not use it currently.
+ *
+ * Note, that application should never directly call this stop function,
+ * em_eo_stop() will trigger this.
+ *
+ * @param eo_ctx        Execution object internal state data
+ * @param eo            Execution object id
+ *
+ * @return EM_OK if successful.
+ *
+ * @see em_eo_stop(), em_eo_create()
+ */
+typedef em_status_t (*em_stop_local_func_t)(void* eo_ctx, em_eo_t eo);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Execution object stop, global.
+ *
+ * If load balancing/several cores share the EO, this function is
+ * called once on one core (any) after the (optional) core local
+ * stop return on all cores.
+ * System disables event dispatching before calling this and also
+ * makes sure this does not get called before all cores have
+ * been notified the stop condition for this EO (can't dispatch new events)
+ * event if there is no core local stop defined.
+ * Return value is only for logging purposes, EM does not use it currently.
+ *
+ * Note, that application should never directly call this stop function,
+ * but use the em_eo_stop() instead, which maintains state information and
+ * guarantees synchronized operation.
+ *
+ * @param eo_ctx        Execution object internal state data
+ * @param eo            Execution object id
+ *
+ * @return EM_OK if successful.
+ *
+ * @see em_eo_stop(), em_eo_create()
+ */
+typedef em_status_t (*em_stop_func_t)(void* eo_ctx, em_eo_t eo);
+
+/**
+ * @ingroup DOC_api_generic
+ *
+ * Error handler.
+ *
+ * Error handler maybe called after EM notices an error or user have called em_error().
+ * 
+ * User can register EO specific and/or EM global error handlers. When an error is noticed, 
+ * EM calls EO specific error handler, if registered. If there's no EO specific handler registered 
+ * (for the EO) or the error is noticed outside of an EO context, EM calls the global error 
+ * handler (if registered). If no error handlers are found, EM just returns an error code depending on 
+ * the API function.
+ *
+ * Error handler is called with the original error code from the API call or em_error(). Error 
+ * scope identifies the source of the error and how the error code and variable arguments 
+ * should be interpreted (number of arguments and types).
+ *
+ * @param eo            Execution object id
+ * @param error         The error code
+ * @param escope        Error scope. Identifies the scope for interpreting the error code and variable arguments.
+ * @param args          Variable number and type of arguments
+ *
+ * @return The function may not return depending on implementation/error code/error scope. If it
+ * returns, it can return the original or modified error code or even EM_OK, if it could fix the problem.
+ *
+ * @see em_register_error_handler(), em_eo_register_error_handler()
+ */
+#ifndef TI_EM_GCC
+typedef em_status_t (*em_error_handler_t)(em_eo_t eo, em_status_t error, em_escope_t escope, va_list args);
+#else /* TI_EM_GCC */
+typedef em_status_t (*em_error_handler_t)(em_eo_t eo, em_status_t error, em_escope_t escope, ...);
+#endif /* TI_EM_GCC */
+
+
+/**
+ * \internal
+ *--------------------------------------------------------------------------
+ * Copyright (c) 2012, Texas Instruments Incorporated - http://www.ti.com/
+ * End of the copy from the original event_machine.h 
+ *--------------------------------------------------------------------------
+ * \endinternal
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* EVENT_MACHINE_TYPES_H_ */
+
diff --git a/platform/linux-keystone2/prebuilts/openem/include/linux/keystone2/ti_em_hw_cppi.h b/platform/linux-keystone2/prebuilts/openem/include/linux/keystone2/ti_em_hw_cppi.h
new file mode 100644
index 0000000..13df8a7
--- /dev/null
+++ b/platform/linux-keystone2/prebuilts/openem/include/linux/keystone2/ti_em_hw_cppi.h
@@ -0,0 +1,1288 @@
+/*
+ * Copyright (c) 2012, Texas Instruments Incorporated - http://www.ti.com/
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *       * Redistributions of source code must retain the above copyright
+ *         notice, this list of conditions and the following disclaimer.
+ *       * Redistributions in binary form must reproduce the above copyright
+ *         notice, this list of conditions and the following disclaimer in the
+ *         documentation and/or other materials provided with the distribution.
+ *       * Neither the name of Texas Instruments Incorporated nor the
+ *         names of its contributors may be used to endorse or promote products
+ *         derived from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ *   WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY
+ *   DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ *   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *   ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/**
+ *   @file  ti_em_hw_cppi.h
+ *
+ *   @brief   
+ *      This is the CPPI Descriptor Management include file.
+ *
+ */
+
+#ifndef TI_EM_HW_CPPI_H_
+#define TI_EM_HW_CPPI_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <string.h> /* for memcpy() */
+
+/** CPPI maximum number of CPDMAs */
+#define CPPI_MAX_CPDMA                      13
+
+/** Used as input parameter when queue number is 
+ * not known and not specified */
+#define CPPI_PARAM_NOT_SPECIFIED            -1
+
+/** CPPI Low level Driver return and Error Codes */
+/** CPPI successful return code */
+#define CPPI_SOK                            0
+/** CPPI Error Base */       
+#define CPPI_LLD_EBASE                      (-128)
+/** CPPI CPDMA not yet initialized */
+#define CPPI_CPDMA_NOT_INITIALIZED          CPPI_LLD_EBASE-1
+/** CPPI invalid parameter */
+#define CPPI_INVALID_PARAM                  CPPI_LLD_EBASE-2
+/** CPPI Rx/Tx channel not yet enabled */
+#define CPPI_CHANNEL_NOT_OPEN               CPPI_LLD_EBASE-3
+/** CPPI Rx flow not yet enabled */
+#define CPPI_FLOW_NOT_OPEN                  CPPI_LLD_EBASE-4
+/** CPPI Tx channels are still open. 
+ * All Tx channels should be closed 
+ * before calling CPPI_close */
+#define CPPI_TX_CHANNELS_NOT_CLOSED         CPPI_LLD_EBASE-5
+/** CPPI Rx channels are still open. 
+ * All Rx channels should be closed 
+ * before calling CPPI_close */
+#define CPPI_RX_CHANNELS_NOT_CLOSED         CPPI_LLD_EBASE-6
+/** CPPI Rx flows are still open. 
+ * All Rx flows should be closed 
+ * before calling CPPI_close */
+#define CPPI_RX_FLOWS_NOT_CLOSED            CPPI_LLD_EBASE-7
+
+/** Queue Manager subsystem memory region not enabled */
+#define CPPI_QMSS_MEMREGION_NOT_INITIALIZED CPPI_LLD_EBASE-8
+/** Queue open error */
+#define CPPI_QUEUE_OPEN_ERROR               CPPI_LLD_EBASE-9
+/** CPPI extended packet information block not present in descriptor */
+#define CPPI_EPIB_NOT_PRESENT               CPPI_LLD_EBASE-10
+/** CPPI protocol specific data not present in descriptor */
+#define CPPI_PSDATA_NOT_PRESENT             CPPI_LLD_EBASE-11
+/** CPPI CPDMA instances are still open. 
+ * All CPDMA instances should be closed 
+ * before calling CPPI_exit */
+#define CPPI_CPDMA_NOT_CLOSED               CPPI_LLD_EBASE-12
+/** CPPI resource initialization permission denied */
+#define CPPI_RESOURCE_INIT_DENIED           CPPI_LLD_EBASE-13
+/** CPPI resource usage permission denied */
+#define CPPI_RESOURCE_USE_DENIED            CPPI_LLD_EBASE-14
+
+/**
+@}
+*/
+
+/** 
+ * @brief CPPI CPDMA types
+ */
+typedef enum
+{
+    /** SRIO */
+    Cppi_CpDma_SRIO_CPDMA = 0,
+    /** AIF */
+    Cppi_CpDma_AIF_CPDMA,
+    /** FFTC A */
+    Cppi_CpDma_FFTC_A_CPDMA,
+    /** FFTC B */
+    Cppi_CpDma_FFTC_B_CPDMA,
+    /** FFTC C */
+    Cppi_CpDma_FFTC_C_CPDMA,
+    /** FFTC D */
+    Cppi_CpDma_FFTC_D_CPDMA,
+    /** FFTC E */
+    Cppi_CpDma_FFTC_E_CPDMA,
+    /** FFTC F */
+    Cppi_CpDma_FFTC_F_CPDMA,
+    /** PASS */
+    Cppi_CpDma_PASS_CPDMA,
+    /** QMSS in first QM */
+    Cppi_CpDma_QMSS_CPDMA,
+    /** QMSS in second QM */
+    Cppi_CpDma_QMSS_QM2_CPDMA,
+    /** BCP */
+    Cppi_CpDma_BCP_CPDMA,
+    /** XGE */
+    Cppi_CpDma_XGE_CPDMA,
+}Cppi_CpDma;
+
+/** 
+ * @brief CPPI Channel type 
+ */
+typedef enum
+{
+    /** Receive Channel */
+    Cppi_ChType_RX_CHANNEL = 0,
+    /** Transmit Channel */
+    Cppi_ChType_TX_CHANNEL
+}Cppi_ChType;
+
+/** 
+ * @brief CPPI Channel Enable
+ */
+typedef enum
+{
+    /** Disable Channel */
+    Cppi_ChState_CHANNEL_DISABLE = 0,
+    /** Enable Channel */
+    Cppi_ChState_CHANNEL_ENABLE 
+}Cppi_ChState;
+
+/** 
+ * @brief CPPI Wait after Channel Teardown
+ */
+typedef enum
+{
+    /** No wait */
+    Cppi_Wait_NO_WAIT = 0,
+    /** Wait */
+    Cppi_Wait_WAIT
+}Cppi_Wait;
+
+/**
+@}
+*/
+
+/** @addtogroup CPPI_LLD_DATASTRUCT
+@{ 
+*/
+
+/** 
+ * @brief CPPI CPDMA configuration structure
+ */
+typedef struct
+{
+    /** CPDMA configuring control registers */
+    Cppi_CpDma                  dmaNum;
+
+    /** This field sets the depth of the write arbitration FIFO which stores write transaction information
+     * between the command arbiter and write data arbiters in the Bus Interface Unit. Setting this field to smaller 
+     * values will cause prevent the CDMAHP from having an excess of write transactions outstanding whose data is 
+     * still waiting to be transferred.
+     * System performance can suffer if write commands are allowed to be issued long before the corresponding 
+     * write data will be transferred.  This field allows the command count to be optimized based on system dynamics
+     *
+     * Valid range is 1 to 32. If writeFifoDepth field is set to 0, this field will not be configured. The reset/default value is 20.
+     */
+    uint8_t                     writeFifoDepth;
+    /** This field sets the timeout duration in clock cycles.  This field controls the minimum 
+     * amount of time that an Rx channel will be required to wait when it encounters a buffer starvation 
+     * condition and the Rx error handling bit is set to 1 (packet is to be preserved - no discard).  
+     * If the Rx error handling bit in the flow table is cleared, this field will have no effect on the Rx operation.  
+     * When this field is set to 0, the Rx engine will not force an Rx channel to wait after encountering a starvation 
+     * event (the feature is disabled).  When this field is set to a value other than 0, the Rx engine will force any 
+     * channel whose associated flow had the Rx error handling bit asserted and which encounters starvation to wait for 
+     * at least the specified # of clock cycles before coming into context again to retry the access to the QM
+     */ 
+    uint16_t                    timeoutCount;
+    /** The QM N Queues Region Base Address Register is used to provide a programmable 
+     * pointer to the base address of the queues region in Queue Manager N in the system 
+     */
+
+    /** Queue Manager 0 base address register - 0 means use default from Cppi_GlobalConfigParams */
+    uint32_t            qm0BaseAddress;
+    /** Queue Manager 1 base address register - 0 means use default from Cppi_GlobalConfigParams */
+    uint32_t            qm1BaseAddress;
+    /** Queue Manager 2 base address register - 0 means use default from Cppi_GlobalConfigParams */
+    uint32_t            qm2BaseAddress;
+    /** Queue Manager 3 base address register - 0 means use default from Cppi_GlobalConfigParams */
+    uint32_t            qm3BaseAddress;
+}Cppi_CpDmaInitCfg;
+
+/** 
+ * @brief CPPI transmit channel configuration structure
+ */
+typedef struct
+{
+    /** Channel number */
+    /** If channelNum is set to CPPI_PARAM_NOT_SPECIFIED then the next 
+     * available channel will be allocated */
+    int32_t           channelNum;
+    /** Enable Tx Channel on creation. If not set use CPPI_channelEnable() API to enable it later */
+    Cppi_ChState    txEnable;
+    /** Tx scheduling priority for channelNum */
+    uint8_t           priority;
+    /** Tx Filter Software Info.  This field controls whether or not the DMA controller will pass the 
+     * extended packet information fields (if present) from the descriptor to the back end application.
+     * 0 - DMA controller will pass extended packet info fields if they are present in the descriptor
+     * 1 - DMA controller will filter extended packet info fields
+     */
+    uint16_t             filterEPIB;
+    /** Filter Protocol Specific Words. This field controls whether or not the DMA controller will 
+     * pass the protocol specific words (if present) from the descriptor to the back end application.
+     * 0 - DMA controller will pass PS words if present in descriptor
+     * 1 - DMA controller will filter PS words
+     */
+    uint16_t             filterPS;
+    /**
+     * AIF Specific Monolithic Packet Mode. This field when set indicates that all monolithic packets 
+     * which will be transferred on this channel will be formatted in an optimal configuration as needed 
+     * by the Antenna Interface Peripheral.  The AIF configuration uses a fixed descriptor format which 
+     * includes the 3 mandatory descriptor info words, a single Protocol Specific Word and data 
+     * immediately following (data offset = 16).
+     */
+    uint16_t             aifMonoMode;
+}Cppi_TxChInitCfg;
+
+/** 
+ * @brief CPPI receive channel configuration structure
+ */
+typedef struct
+{
+    /** Channel number */
+    /** If channelNum is set to CPPI_PARAM_NOT_SPECIFIED then the next 
+     * available channel will be allocated */
+    int32_t           channelNum;
+    /** Enable Rx Channel on creation. If not set use CPPI_channelEnable() API to enable it later */
+    Cppi_ChState    rxEnable;
+}Cppi_RxChInitCfg;
+
+/** 
+ * @brief CPPI receive flow configuration structure
+ */
+typedef struct 
+{
+    /** Rx flow configuration register A */
+
+    /** flow ID number */
+    /** If flowIdNum is set to CPPI_PARAM_NOT_SPECIFIED then the next available flow ID will be allocated */
+    int16_t           flowIdNum;
+    /** This field indicates the default receive queue that this channel should use */
+    uint16_t          rx_dest_qnum;
+    /** This field indicates the default receive queue manager that this channel should use */
+    uint16_t          rx_dest_qmgr;
+    /** This field specifies the number of bytes that are to be skipped in the SOP buffer before beginning 
+     * to write the payload or protocol specific bytes(if they are in the sop buffer).  This value must
+     * be less than the minimum size of a buffer in the system */
+    uint16_t          rx_sop_offset;
+    /** This field controls where the Protocol Specific words will be placed in the Host Mode CPPI data structure 
+     * 0 - protocol specific information is located in descriptor 
+     * 1 - protocol specific information is located in SOP buffer */
+    uint16_t             rx_ps_location;
+    /** This field indicates the descriptor type to use 1 = Host, 2 = Monolithic */
+    uint8_t           rx_desc_type;
+    /** This field controls the error handling mode for the flow and is only used when channel errors occurs 
+     * 0 = Starvation errors result in dropping packet and reclaiming any used descriptor or buffer resources 
+     * back to the original queues/pools they were allocated to
+     * 1 = Starvation errors result in subsequent re-try of the descriptor allocation operation.  
+     */
+    uint16_t             rx_error_handling;
+    /** This field controls whether or not the Protocol Specific words will be present in the Rx Packet Descriptor 
+     * 0 - The port DMA will set the PS word count to 0 in the PD and will drop any PS words that are presented 
+     * from the back end application.
+     * 1 - The port DMA will set the PS word count to the value given by the back end application and will copy 
+     * the PS words from the back end application to the location 
+     */
+    uint16_t             rx_psinfo_present;
+    /** This field controls whether or not the Extended Packet Info Block will be present in the Rx Packet Descriptor.  
+     * 0 - The port DMA will clear the Extended Packet Info Block Present bit in the PD and will drop any extended 
+     * packet info words that are presented from the back end application. 
+     * 1 - The port DMA will set the Extended Packet Info Block Present bit in the PD and will copy any extended packet
+     * info words that are presented across the Rx streaming interface into the extended packet info words in the descriptor.
+     * If no extended packet info words are presented from the back end application, the port DMA will overwrite the fields with zeroes.
+     */
+    uint16_t             rx_einfo_present;
+
+    /** Rx flow configuration register B */
+
+    /** This is the value to insert into bits 7:0 of the destination tag if the rx_dest_tag_lo_sel is set to 1 */
+    uint8_t           rx_dest_tag_lo;
+    /** This is the value to insert into bits 15:8 of the destination tag if the rx_dest_tag_hi_sel is set to 1 */
+    uint8_t           rx_dest_tag_hi;
+    /** This is the value to insert into bits 7:0 of the source tag if the rx_src_tag_lo_sel is set to 1 */
+    uint8_t           rx_src_tag_lo;
+    /** This is the value to insert into bits 15:8 of the source tag if the rx_src_tag_hi_sel is set to 1 */
+    uint8_t           rx_src_tag_hi;    
+
+    /** Rx flow configuration register C */
+    /** This bits control whether or not the flow will compare the packet size received from the back end application 
+     * against the rx_size_thresh0 fields to determine which FDQ to allocate the SOP buffer from.  
+     * The bits in this field is encoded as follows:
+     * 0 = Do not use the threshold.
+     * 1 = Use the thresholds to select SOP FDQ rx_fdq0_sz0_qnum/rx_fdq0_sz0_qmgr.
+     */
+    uint8_t             rx_size_thresh0_en;
+    /** This bits control whether or not the flow will compare the packet size received from the back end application 
+     * against the rx_size_thresh1 fields to determine which FDQ to allocate the SOP buffer from.  
+     * The bits in this field is encoded as follows:
+     * 0 = Do not use the threshold.
+     * 1 = Use the thresholds to select SOP FDQ rx_fdq0_sz1_qnum/rx_fdq0_sz1_qmgr.
+     */
+    uint8_t             rx_size_thresh1_en;
+        /** This bits control whether or not the flow will compare the packet size received from the back end application 
+     * against the rx_size_thresh2 fields to determine which FDQ to allocate the SOP buffer from.  
+     * The bits in this field is encoded as follows:
+     * 0 = Do not use the threshold.
+     * 1 = Use the thresholds to select SOP FDQ rx_fdq0_sz2_qnum/rx_fdq0_sz2_qmgr.
+     */
+    uint8_t             rx_size_thresh2_en;
+
+    /** This field specifies the source for bits 7:0 of the source tag field in word 1 of the output PD.
+     * This field is encoded as follows:
+     * 0 = do not overwrite
+     * 1 = overwrite with value given in rx_dest_tag_lo
+     * 2 = overwrite with flow_id[7:0] from back end application
+     * 3 = RESERVED
+     * 4 = overwrite with dest_tag[7:0] from back end application
+     * 5 = overwrite with dest_tag[15:8] from back end application
+     * 6-7 = RESERVED
+     */    
+    uint8_t           rx_dest_tag_lo_sel;
+    /** This field specifies the source for bits 15:8 of the source tag field in the word 1 of the output PD.
+     * This field is encoded as follows:
+     * 0 = do not overwrite
+     * 1 = overwrite with value given in rx_dest_tag_hi
+     * 2 = overwrite with flow_id[7:0] from back end application
+     * 3 = RESERVED
+     * 4 = overwrite with dest_tag[7:0] from back end application
+     * 5 = overwrite with dest_tag[15:8] from back end application
+     * 6-7 = RESERVED
+     */
+    uint8_t           rx_dest_tag_hi_sel;
+    /** This field specifies the source for bits 7:0 of the source tag field in the output packet descriptor.
+     * This field is encoded as follows:
+     * 0 = do not overwrite
+     * 1 = overwrite with value given in rx_src_tag_lo
+     * 2 = overwrite with flow_id[7:0] from back end application
+     * 3 = RESERVED
+     * 4 = overwrite with src_tag[7:0] from back end application
+     * 5 = RESERVED
+     * 6-7 = RESERVED
+     */
+    uint8_t           rx_src_tag_lo_sel;
+    /** This field specifies the source for bits 15:8 of the source tag field in the output packet descriptor.
+     * This field is encoded as follows:
+     * 0 = do not overwrite
+     * 1 = overwrite with value given in rx_src_tag_hi
+     * 2 = overwrite with flow_id[7:0] from back end application
+     * 3 = RESERVED
+     * 4 = overwrite with src_tag[7:0] from back end application
+     * 5 = RESERVED
+     * 6-7 = RESERVED
+     */
+    uint8_t           rx_src_tag_hi_sel;    
+ 
+    /** Rx flow configuration register D */
+
+    /** This field specifies which Free Descriptor Queue should be used for the 2nd Rx buffer in a host type packet */
+    uint16_t          rx_fdq1_qnum;
+    /** This field specifies which Queue Manager should be used for the 2nd Rx buffer in a host type packet */
+    uint16_t          rx_fdq1_qmgr;
+    /** This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose 
+     * size is less than or equal to the rx_size0 value */
+    uint16_t          rx_fdq0_sz0_qnum;
+    /** This field specifies which Queue Manager should be used for the 1st Rx buffer in a packet whose size 
+     * is less than or equal to the rx_size0 value */
+    uint16_t          rx_fdq0_sz0_qmgr;
+
+    /** Rx flow configuration register E */
+
+    /** This field specifies which Free Descriptor Queue should be used for the 4th or later Rx
+     *  buffers in a host type packet */
+    uint16_t          rx_fdq3_qnum;
+    /** This field specifies which Queue Manager should be used for the 4th or later Rx buffers 
+     * in a host type packet */
+    uint16_t          rx_fdq3_qmgr;
+    /** This field specifies which Free Descriptor Queue should be used for the 3rd Rx buffer in a host type packet */
+    uint16_t          rx_fdq2_qnum;
+    /** This field specifies which Queue Manager should be used for the 3rd Rx buffer in a host type packet */
+    uint16_t          rx_fdq2_qmgr;
+
+    /** Rx flow configuration register F */
+
+    /** This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor 
+     * queue should be used for the SOP buffer in the packet.  If the  packet size is greater than the rx_size_thresh0 
+     * but is less than or equal to the value given in this threshold, the DMA controller in the port will allocate the 
+     * SOP buffer from the queue given by the rx_fdq0_sz1_qmgr and rx_fdq0_sz1_qnum fields. 
+     * If enabled, this value must be greater than the value given in the rx_size_thresh0 field. This field is optional.
+     */
+    uint16_t          rx_size_thresh1;
+    /** This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor 
+     * queue should be used for the SOP buffer in the packet.  If the packet size is less than or equal to the value 
+     * given in this threshold, the DMA controller in the port will allocate the SOP buffer from the queue given by 
+     * the rx_fdq0_sz0_qmgr and rx_fdq0_sz0_qnum fields. This field is optional.
+     */
+    uint16_t          rx_size_thresh0;
+    
+    /** Rx flow configuration register G */
+
+    /** This field specifies which Queue should be used for the 1st Rx buffer in a packet whose size is 
+     * less than or equal to the rx_size0 value */
+    uint16_t          rx_fdq0_sz1_qnum;
+    /** This field specifies which Queue Manager should be used for the 1st Rx buffer in a packet whose size 
+     * is less than or equal to the rx_size0 value */
+    uint16_t          rx_fdq0_sz1_qmgr;
+    /** This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor 
+     * queue should be used for the SOP buffer in the packet.  If the  packet size is less than or equal to the value
+     * given in this threshold, the DMA controller in the port will allocate the SOP buffer from the queue given by the 
+     * rx_fdq0_sz2_qmgr and rx_fdq0_sz2_qnum fields.
+     * If enabled, this value must be greater than the value given in the rx_size_thresh1 field. This field is optional.
+     */
+    uint16_t  		rx_size_thresh2;
+
+    /** Rx flow configuration register H */
+
+    /** This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a
+     * packet whose size is less than or equal to the rx_size3 value */
+    uint16_t          rx_fdq0_sz3_qnum;
+    /** This field specifies which Free Descriptor Queue Manager should be used for the 1st Rx buffer in a 
+     * packet whose size is less than or equal to the rx_size3 value */
+    uint16_t          rx_fdq0_sz3_qmgr;
+    /** This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet 
+     * whose size is less than or equal to the rx_size2 value */
+    uint16_t          rx_fdq0_sz2_qnum;
+    /** This field specifies which Free Descriptor Queue Manager should be used for the 1st Rx buffer in a packet 
+     * whose size is less than or equal to the rx_size2 value */
+    uint16_t          rx_fdq0_sz2_qmgr;
+}Cppi_RxFlowCfg;
+
+/** 
+ * @brief CPPI return result
+ */
+typedef int32_t   Cppi_Result;
+
+/** 
+ * @brief CPPI handle
+ */
+typedef uint32_t  *Cppi_Handle;
+
+/** 
+ * @brief CPPI channel handle
+ */
+typedef uint32_t  *Cppi_ChHnd;
+
+/** 
+ * @brief CPPI receive flow handle
+ */
+typedef uint32_t  *Cppi_FlowHnd;
+
+/** Monolithic descriptor extended packet information block size */
+#define CPPI_MONOLITHIC_DESC_EPIB_SIZE      20
+/** Host descriptor extended packet information block size */
+#define CPPI_HOST_DESC_EPIB_SIZE            16
+
+/** 
+ * @brief CPPI descriptor types
+ */
+typedef enum
+{
+    /** Host descriptor */
+    Cppi_DescType_HOST = 0,
+    /** Monolithic descriptor */
+    Cppi_DescType_MONOLITHIC = 2
+}Cppi_DescType;
+
+/** 
+ * @brief Packet return policy
+ */
+typedef enum
+{
+    /** Return entire packet */
+    Cppi_ReturnPolicy_RETURN_ENTIRE_PACKET = 0,
+    /** Return one buffer at a time */
+    Cppi_ReturnPolicy_RETURN_BUFFER 
+}Cppi_ReturnPolicy;
+
+/** 
+ * @brief protocol specific information location 
+ */
+typedef enum
+{
+    /** protocol specific information is located in descriptor */
+    Cppi_PSLoc_PS_IN_DESC = 0,
+    /** protocol specific information is located in SOP buffer */
+    Cppi_PSLoc_PS_IN_SOP
+}Cppi_PSLoc;
+
+/** 
+ * @brief extended packet information block
+ */
+typedef enum
+{
+    /** extended packet information block is not present in descriptor */
+    Cppi_EPIB_NO_EPIB_PRESENT = 0,
+    /** extended packet information block is present in descriptor  */
+    Cppi_EPIB_EPIB_PRESENT
+}Cppi_EPIB;
+
+/** 
+ * @brief Descriptor resource management
+ */
+typedef enum
+{
+    /** LLD initializes the descriptors with specified values */
+    Cppi_InitDesc_INIT_DESCRIPTOR = 0,
+    /** LLD does not initialize the descriptor with specified values */    
+    Cppi_InitDesc_BYPASS_INIT 
+}Cppi_InitDesc;
+
+/** 
+@} 
+*/
+
+/** @addtogroup CPPI_LLD_DATASTRUCT
+@{ 
+*/
+
+/** 
+ * @brief CPPI host descriptor configuration structure
+ */
+typedef struct 
+{
+    /** Indicates return policy for the packet. 
+     * Valid only for host descriptor */
+    Cppi_ReturnPolicy       returnPolicy;
+    /** Indicates protocol specific location CPPI_PS_DESC - located in descriptor, CPPI_PS_SOP - located in SOP buffer 
+     * Valid only for host descriptor */
+    Cppi_PSLoc              psLocation;
+}Cppi_HostDescCfg;
+
+/** 
+ * @brief CPPI monolithic descriptor configuration structure
+ */
+typedef struct 
+{
+    /** Byte offset from byte 0 of monolithic descriptor to the location where the valid data begins */
+    uint32_t                  dataOffset;
+}Cppi_MonolithicDescCfg;
+
+/** 
+ * @brief CPPI descriptor configuration structure
+ */
+typedef struct 
+{
+    /** Memory Region corresponding to the descriptor. */
+    Qmss_MemRegion          memRegion;
+    /** Group for memRegion (only applicable in when QMSS is in split mode) */
+    uint32_t                queueGroup;
+    /** Number of descriptors that should be configured with value below */
+    uint32_t                  descNum;
+    /** Queue where the descriptor is stored. If destQueueNum is set to QMSS_PARAM_NOT_SPECIFIED then the next 
+     * available queue of type Qmss_QueueType will be allocated */
+    int32_t                   destQueueNum;
+    /** If destQueueNum is set to QMSS_PARAM_NOT_SPECIFIED then the next available queue of type 
+     * Qmss_QueueType will be allocated */
+    Qmss_QueueType          queueType;
+
+    /** Descriptor configuration parameters */
+    /** Indicates if the descriptor should be initialized with parameters listed below */
+    Cppi_InitDesc           initDesc;
+
+    /** Type of descriptor - Host or Monolithic */
+    Cppi_DescType           descType;
+    /** Indicates return Queue Manager and Queue Number. If both qMgr and qNum in returnQueue is 
+     * set to QMSS_PARAM_NOT_SPECIFIED then the destQueueNum is configured in returnQueue of the descriptor */
+    Qmss_Queue              returnQueue;
+    /** Indicates how the CPDMA returns descriptors to free queue */
+    Qmss_Location           returnPushPolicy;
+    /** Indicates presence of EPIB */
+    Cppi_EPIB               epibPresent;
+
+    /** Union contains configuration that should be initialized in for host or monolithic descriptor. 
+     * The configuration for host or monolithic descriptor is choosen based on "descType" field. 
+     * The approriate structure fields must be specified if "initDesc" field is set to CPPI_INIT_DESCRIPTOR. */
+    union{
+    /** Host descriptor configuration parameters */
+    Cppi_HostDescCfg        host;
+    /** Monolithic  descriptor configuration parameters */
+    Cppi_MonolithicDescCfg  mono;
+    }cfg;
+
+}Cppi_DescCfg;
+
+/** 
+ * @brief CPPI descriptor Word 1 Tag information
+ */
+typedef struct {
+    uint8_t srcTagHi;
+    uint8_t srcTagLo;
+    uint8_t destTagHi;
+    uint8_t destTagLo;
+}Cppi_DescTag;
+
+/** 
+ * @brief CPPI host descriptor layout
+ */
+typedef struct {
+    /** Descriptor type, packet type, protocol specific region location, packet length */
+    uint32_t          descInfo;  
+    /** Source tag, Destination tag */
+    uint32_t          tagInfo;
+    /** EPIB present, PS valid word count, error flags, PS flags, return policy, return push policy, 
+     * packet return QM number, packet return queue number */
+    uint32_t          packetInfo;
+    /** Number of valid data bytes in the buffer */
+    uint32_t          buffLen;
+    /** Byte aligned memory address of the buffer associated with this descriptor */
+    uint32_t          buffPtr;
+    /** 32-bit word aligned memory address of the next buffer descriptor */
+    uint32_t          nextBDPtr;       
+    /** Completion tag, original buffer size */
+    uint32_t          origBufferLen;
+    /** Original buffer pointer */
+    uint32_t          origBuffPtr;
+    /** Optional EPIB word0 */
+    uint32_t          timeStamp;
+    /** Optional EPIB word1 */
+    uint32_t          softwareInfo0;
+    /** Optional EPIB word2 */
+    uint32_t          softwareInfo1;
+    /** Optional EPIB word3 */
+    uint32_t          softwareInfo2;
+    /** Optional protocol specific data */
+    uint32_t          psData; 
+}Cppi_HostDesc;
+
+/** 
+ * @brief CPPI monolithic descriptor layout
+ */
+typedef struct {
+    /** Descriptor type, packet type, data offset, packet length */
+    uint32_t          descInfo;  
+    /** Source tag, Destination tag */
+    uint32_t          tagInfo;
+    /** EPIB present, PS valid word count, error flags, PS flags, return push policy, 
+     * packet return QM number, packet return queue number */
+    uint32_t          packetInfo;
+    /** NULL word to align the extended packet words to a 128 bit boundary */
+    uint32_t          Reserved;
+    /** Optional EPIB word0 */
+    uint32_t          timeStamp;
+    /** Optional EPIB word1 */
+    uint32_t          softwareInfo0;
+    /** Optional EPIB word2 */
+    uint32_t          softwareInfo1;
+    /** Optional EPIB word3 */
+    uint32_t          softwareInfo2;
+    /** Optional protocol specific data */
+    uint32_t          psData; 
+}Cppi_MonolithicDesc;
+
+/** 
+ * @brief CPPI descriptor
+ */
+typedef union {
+    /** Host descriptor */
+    Cppi_HostDesc       *ptrHostDesc;  
+    /** Monolithic descriptor */
+    Cppi_MonolithicDesc *ptrMonoDesc;
+}Cppi_Desc;
+
+/**
+ * @brief CPPI global configuration structure
+ */
+typedef struct
+{
+    /** CPDMA this configuration belongs to */
+    Cppi_CpDma      dmaNum;
+    /** Maximum supported Rx Channels */
+    uint32_t          maxRxCh;
+    /** Maximum supported Tx Channels */
+    uint32_t          maxTxCh;
+    /** Maximum supported Rx Flows */
+    uint32_t          maxRxFlow;
+    /** Priority for all Rx transactions of this CPDMA */
+    uint8_t           rxPriority;
+    /** Priority for all Tx transactions of this CPDMA */
+    uint8_t           txPriority;
+
+    /** Base address for the CPDMA overlay registers */
+
+    /** Global Config registers */
+    CSL_Cppidma_global_configRegs       *gblCfgRegs;
+    /** Tx Channel Config registers */
+    CSL_Cppidma_tx_channel_configRegs   *txChRegs;
+    /** Rx Channel Config registers */
+    CSL_Cppidma_rx_channel_configRegs   *rxChRegs;
+    /** Tx Channel Scheduler registers */
+    CSL_Cppidma_tx_scheduler_configRegs *txSchedRegs;
+    /** Rx Flow Config registers */
+    CSL_Cppidma_rx_flow_configRegs      *rxFlowRegs;
+} Cppi_GlobalCPDMAConfigParams;
+    
+/**
+ *  @b Description
+ *  @n  
+ *      This function is used to set the original buffer information in the host descriptor. 
+ *
+ *      **No validation is done on the input parameters**.
+ *
+ *  @param[in]  descType
+ *      Type of descriptor - Cppi_DescType_HOST
+ *
+ *  @param[in]  descAddr
+ *      Memory address of descriptor.
+ *
+ *  @param[in]  buffAddr
+ *      Memory address of data buffer pointer.
+ *      
+ *  @param[in]  buffLen
+ *      Size of the original data buffer.
+ *
+ *  @pre  
+ *      Descriptor must be allocated and be valid.
+ *
+ *  @post  
+ *      In case of host descriptor Word 6(bits 0 to 31) and Word 7 are updated
+ *
+ *  @retval
+ *      None.
+ */
+static inline void ti_em_cppi_set_original_buf_info (Cppi_DescType descType, 
+						     Cppi_Desc    *descAddr,
+						     uint32_t      buffAddr, 
+						     uint32_t      buffLen)
+{
+    Cppi_HostDesc *hostDescPtr = (Cppi_HostDesc *) descAddr;
+
+    (void)descType;
+    hostDescPtr->origBuffPtr = buffAddr;
+    CSL_FINSR (hostDescPtr->origBufferLen, 21, 0, buffLen);
+
+    return;
+}
+
+/**
+ *  @b Description
+ *  @n  
+ *      This function is used to retrieve the original buffer information from host descriptor. 
+ *
+ *      **No validation is done on the input parameters**.
+ *
+ *  @param[in]  descType
+ *      Type of descriptor - Cppi_DescType_HOST
+ *
+ *  @param[in]  descAddr
+ *      Memory address of descriptor.
+ *
+ *  @param[out]  buffAddr
+ *      Memory address of data buffer pointer.
+ *      
+ *  @param[out]  buffLen
+ *      Size of the original data buffer.
+ *
+ *  @pre  
+ *      Descriptor must be allocated and be valid.
+ *
+ *  @post  
+ *      In case of host descriptor Word 6(bits 0 to 21) and Word 7 are returned
+ *
+ *  @retval
+ *      None.
+ */
+static inline void ti_em_cppi_get_original_buf_info (Cppi_DescType descType, 
+						     Cppi_Desc *descAddr,
+						     uint8_t **buffAddr, 
+						     uint32_t *buffLen)
+{
+    Cppi_HostDesc   *hostDescPtr = (Cppi_HostDesc *) descAddr;
+
+    (void)descType;
+    *buffAddr = (uint8_t *) hostDescPtr->origBuffPtr;
+    *buffLen = CSL_FEXTR (hostDescPtr->origBufferLen, 21, 0);
+
+    return;
+}
+
+/**
+ *  @b Description
+ *  @n  
+ *      This function is used to set the packet type in host or monolithic descriptor.
+ *
+ *      **No validation is done on the input parameters**.
+ *
+ *  @param[in]  descType
+ *      Type of descriptor - Cppi_DescType_HOST, Cppi_DescType_MONOLITHIC
+ *
+ *  @param[in]  descAddr
+ *      Memory address of descriptor.
+ *
+ *  @param[in]  packetType
+ *      Indicates type of packet. Valid range is 0 to 31.
+ *      
+ *  @pre  
+ *      Descriptor must be allocated and be valid.
+ *
+ *  @post  
+ *      Word 0 (bits 25 to 29) of host or monolithic descriptor are updated.
+ *
+ *  @retval
+ *      None
+ */
+static inline void ti_em_cppi_set_packet_type (Cppi_DescType descType, 
+					       Cppi_Desc *descAddr,
+					       uint8_t packetType)
+{
+    Cppi_HostDesc   *descPtr = (Cppi_HostDesc *) descAddr;
+
+    (void)descType;
+    CSL_FINSR (descPtr->descInfo, 29, 25, packetType);
+    return;
+}
+
+/**
+ *  @b Description
+ *  @n  
+ *      This function is used to get the packet type from host or monolithic descriptor.
+ *
+ *      **No validation is done on the input parameters**.
+ *
+ *  @param[in]  descType
+ *      Type of descriptor - Cppi_DescType_HOST, Cppi_DescType_MONOLITHIC
+ *      
+ *  @param[in]  descAddr
+ *      Memory address of descriptor.
+ *      
+ *  @pre  
+ *      Descriptor must be allocated and be valid.
+ *
+ *  @retval
+ *      5 bit packet type field. Valid range is 0 to 31.
+ */
+static inline uint8_t ti_em_cppi_get_packet_type (Cppi_DescType descType, 
+						  Cppi_Desc *descAddr)
+{
+    Cppi_HostDesc   *descPtr = (Cppi_HostDesc *) descAddr;
+
+    (void)descType;
+    return (CSL_FEXTR (descPtr->descInfo, 29, 25));
+}
+
+/**
+ *  @b Description
+ *  @n  
+ *      This function copies the data buffer to the host or monolithic descriptor. 
+ *      It is assumed that enough words are available to store the payload in case 
+ *      of monolithic descriptor.
+ *
+ *      **No validation is done on the input parameters**.
+ *      **Does not update packet length**.
+ *
+ *  @param[in]  descType
+ *      Type of descriptor - Cppi_DescType_HOST, Cppi_DescType_MONOLITHIC
+ *
+ *  @param[in]  descAddr
+ *      Memory address of descriptor.
+ *
+ *  @param[in]  buffAddr
+ *      Memory address of data buffer.
+ *      
+ *  @param[in]  buffLen
+ *      Size of the data buffer.
+ *
+ *  @pre  
+ *      Descriptor and data buffer must be allocated and be valid.
+ *
+ *  @post  
+ *      In case of host descriptor 
+ *          Word 3 and Word 4 are updated
+ *
+ *      In case of monolithic descriptor 
+ *          Word 0 (bits 0 to 15) and payload are updated.
+ *
+ *  @retval
+ *      None.
+ */
+static inline void ti_em_cppi_set_data (Cppi_DescType descType,
+					Cppi_Desc *descAddr,
+					uint8_t *buffAddr,
+					uint32_t buffLen)
+{
+    Cppi_HostDesc   *hostDescPtr;
+
+    /* Does not update packet length */
+    if (descType == Cppi_DescType_HOST)
+    {
+        hostDescPtr = (Cppi_HostDesc *) descAddr;
+        hostDescPtr->buffPtr = (uint32_t) buffAddr;
+        hostDescPtr->buffLen = (uint32_t) buffLen;
+    }
+    else
+    {
+        Cppi_MonolithicDesc *monolithicDescPtr = (Cppi_MonolithicDesc *) descAddr;
+        uint16_t              dataOffset;
+
+        dataOffset = CSL_FEXTR (monolithicDescPtr->descInfo, 24, 16);
+        memcpy ((void *) (((uint8_t *) monolithicDescPtr) + dataOffset), buffAddr, buffLen);
+        CSL_FINSR (monolithicDescPtr->descInfo, 15, 0, buffLen);
+    }
+    return;
+}
+
+/**
+ *  @b Description
+ *  @n  
+ *      This function is update protocol specific data length in host or monolithic descriptor. 
+ *
+ *      **No validation is done on the input parameters**.
+ *      **Does not update packet length**.
+ *
+ *
+ *  @param[in]  descType
+ *      Type of descriptor - Cppi_DescType_HOST, Cppi_DescType_MONOLITHIC
+ *      
+ *  @param[in]  descAddr
+ *      Memory address of descriptor.
+ *
+ *  @param[in]  dataLen
+ *      Size of PS data.
+ *      
+ *  @pre  
+ *      Descriptor must be allocated and be valid.
+ *
+ *  @post  
+ *      Word 2 (bits 24 to 29) are updated.
+ *
+ *  @retval
+ *      None
+ */
+static inline void ti_em_cppi_set_pslen (Cppi_DescType descType, 
+					 Cppi_Desc *descAddr,
+					 uint32_t dataLen)
+{
+    Cppi_HostDesc   *descPtr = (Cppi_HostDesc *) descAddr;
+ 
+    (void)descType;
+    /* Does not update packet length */
+    CSL_FINSR (descPtr->packetInfo, 29, 24, (dataLen / 4));
+    return;
+}
+
+/**
+ *  @b Description
+ *  @n
+ *      This function updates protocol specific flags in host descriptor.
+ *
+ *      **No validation is done on the input parameters**.
+ *
+ *  @param[in]  descAddr
+ *      Memory address of host descriptor.
+ *
+ *  @param[in]  flags
+ *      PS flags.
+ *
+ *  @pre
+ *      Descriptor must be allocated and be valid.
+ *
+ *  @post
+ *      Word 2 (bits 16 to 19) are updated.
+ *
+ *  @retval
+ *      None
+ */
+static inline void ti_em_cppi_set_psflags (Cppi_HostDesc *descAddr,
+						uint32_t flags)
+{
+    CSL_FINSR (descAddr->packetInfo, 19, 16, flags);
+}
+
+/**
+ *  @b Description
+ *  @n
+ *      This function updates packet length in host descriptor.
+ *
+ *      **No validation is done on the input parameters**.
+ *
+ *  @param[in]  descAddr
+ *      Memory address of host descriptor.
+ *
+ *  @param[in]  dataLen
+ *      Size of packet data.
+ *
+ *  @pre
+ *      Descriptor must be allocated and be valid.
+ *
+ *  @post
+ *      Word 0 (bits 0 to 21) are updated.
+ *
+ *  @retval
+ *      None
+ */
+static inline void ti_em_cppi_set_pktlen (Cppi_HostDesc *descAddr,
+					       uint32_t dataLen)
+{
+    Cppi_HostDesc *descPtr = (Cppi_HostDesc *) descAddr;
+    CSL_FINSR (descPtr->descInfo, 21, 0, dataLen);
+    return;
+}
+
+/**
+ *  @b Description
+ *  @n
+ *      This function reads packet length in host descriptor.
+ *
+ *      **No validation is done on the input parameters**.
+ *
+ *  @param[in]  descAddr
+ *      Memory address of host descriptor.
+ *
+ *  @pre
+ *      Descriptor must be allocated and be valid.
+ *
+ *  @retval
+ *      Packet data length in host descriptor.
+ */
+static inline uint32_t ti_em_cppi_get_pktlen (Cppi_HostDesc *descAddr)
+{
+    Cppi_HostDesc *descPtr = (Cppi_HostDesc *) descAddr;
+    return CSL_FEXTR(descPtr->descInfo, 21, 0);
+}
+
+/**
+ *  @b Description
+ *  @n  
+ *      This function is used to set source and destination tags in 
+ *      host or monolithic descriptor. 
+ *
+ *      **No validation is done on the input parameters**.
+ *
+ *  @param[in]  descType
+ *      Type of descriptor - Cppi_DescType_HOST, Cppi_DescType_MONOLITHIC
+ *
+ *  @param[in]  descAddr
+ *      Memory address of descriptor.
+ *
+ *  @param[in]  tag
+ *      Destination and source low and High tag value.
+ *      
+ *  @pre  
+ *      Descriptor must be allocated and be valid.
+ *
+ *  @post  
+ *      Word 1 of host or monolithic descriptor is updated.
+ *
+ *  @retval
+ *      None
+ */
+static inline void ti_em_cppi_set_tag (Cppi_DescType descType, 
+				       Cppi_Desc *descAddr,
+				       Cppi_DescTag *tag)
+{
+    Cppi_HostDesc   *descPtr = (Cppi_HostDesc *) descAddr;
+
+    (void)descType;
+    CSL_FINSR (descPtr->tagInfo, 7, 0, tag->destTagLo);
+    CSL_FINSR (descPtr->tagInfo, 15, 8, tag->destTagHi);
+    CSL_FINSR (descPtr->tagInfo, 23, 16, tag->srcTagLo);
+    CSL_FINSR (descPtr->tagInfo, 31, 24, tag->srcTagHi);
+    return;
+}
+
+/**
+ *  @b Description
+ *  @n  
+ *      This function configures a receive flow.
+ */
+static inline int ti_em_cppi_configure_rx_flow (
+    Cppi_Handle hnd,
+    Cppi_GlobalCPDMAConfigParams *cppiGblCfgParams,
+    Cppi_RxFlowCfg *cfg)
+{
+    CSL_Cppidma_rx_flow_configRegs *rxFlowRegs;
+    uint32_t index  = 0;
+    int32_t  flowId = -1;
+    uint32_t temp   = 0;
+    uint32_t reg;
+
+    if (cfg == NULL)
+        return -1;
+
+    flowId = cfg->flowIdNum;
+    index = flowId;
+
+    rxFlowRegs = cppiGblCfgParams[(uint32_t) hnd].rxFlowRegs;
+
+    /* Rx flow configuration register A */
+    reg = 0;
+    CSL_FINS (reg, CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_DEST_QNUM, cfg->rx_dest_qnum);
+    CSL_FINS (reg, CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_DEST_QMGR, cfg->rx_dest_qmgr);
+    CSL_FINS (reg, CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_SOP_OFFSET, cfg->rx_sop_offset);
+    CSL_FINS (reg, CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_PS_LOCATION, cfg->rx_ps_location);
+    CSL_FINS (reg, CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_DESC_TYPE, cfg->rx_desc_type);
+    CSL_FINS (reg, CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_ERROR_HANDLING, cfg->rx_error_handling);
+    CSL_FINS (reg, CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_PSINFO_PRESENT, cfg->rx_psinfo_present);
+    CSL_FINS (reg, CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_EINFO_PRESENT, cfg->rx_einfo_present);
+    rxFlowRegs->RX_FLOW_CONFIG[index].RX_FLOW_CONFIG_REG_A = reg;
+
+    /* Rx flow configuration register B */
+    reg = 0;
+    CSL_FINS (reg, CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_B_RX_DEST_TAG_LO, cfg->rx_dest_tag_lo);
+    CSL_FINS (reg, CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_B_RX_DEST_TAG_HI, cfg->rx_dest_tag_hi);
+    CSL_FINS (reg, CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_B_RX_SRC_TAG_LO, cfg->rx_src_tag_lo);
+    CSL_FINS (reg, CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_B_RX_SRC_TAG_HI, cfg->rx_src_tag_hi);
+    rxFlowRegs->RX_FLOW_CONFIG[index].RX_FLOW_CONFIG_REG_B = reg;
+
+    /* Rx flow configuration register C */                
+    temp = ((cfg->rx_size_thresh0_en) | (cfg->rx_size_thresh1_en << 1) | (cfg->rx_size_thresh2_en << 2));
+    reg = 0;    
+    CSL_FINS (reg, CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RX_SIZE_THRESH_EN, temp);
+    CSL_FINS (reg, CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RX_DEST_TAG_LO_SEL, cfg->rx_dest_tag_lo_sel);
+    CSL_FINS (reg, CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RX_DEST_TAG_HI_SEL, cfg->rx_dest_tag_hi_sel);
+    CSL_FINS (reg, CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RX_SRC_TAG_LO_SEL, cfg->rx_src_tag_lo_sel);
+    CSL_FINS (reg, CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RX_SRC_TAG_HI_SEL, cfg->rx_src_tag_hi_sel);
+    rxFlowRegs->RX_FLOW_CONFIG[index].RX_FLOW_CONFIG_REG_C = reg;
+
+    /* Rx flow configuration register D */
+    reg = 0;
+    CSL_FINS (reg, CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_D_RX_FDQ1_QNUM, cfg->rx_fdq1_qnum);
+    CSL_FINS (reg, CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_D_RX_FDQ1_QMGR, cfg->rx_fdq1_qmgr);
+    CSL_FINS (reg, CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_D_RX_FDQ0_SZ0_QNUM, cfg->rx_fdq0_sz0_qnum);
+    CSL_FINS (reg, CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_D_RX_FDQ0_SZ0_QMGR, cfg->rx_fdq0_sz0_qmgr);
+    rxFlowRegs->RX_FLOW_CONFIG[index].RX_FLOW_CONFIG_REG_D = reg;
+
+    /* Rx flow configuration register E */
+    reg = 0;
+    CSL_FINS (reg, CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_E_RX_FDQ3_QNUM, cfg->rx_fdq3_qnum);
+    CSL_FINS (reg, CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_E_RX_FDQ3_QMGR, cfg->rx_fdq3_qmgr);
+    CSL_FINS (reg, CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_E_RX_FDQ2_QNUM, cfg->rx_fdq2_qnum);
+    CSL_FINS (reg, CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_E_RX_FDQ2_QMGR, cfg->rx_fdq2_qmgr);
+    rxFlowRegs->RX_FLOW_CONFIG[index].RX_FLOW_CONFIG_REG_E = reg;
+
+    /* Rx flow configuration register F */
+    reg = 0;
+    CSL_FINS (reg, CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_F_RX_SIZE_THRESH1, (cfg->rx_size_thresh1 >> 5));
+    CSL_FINS (reg, CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_F_RX_SIZE_THRESH0, (cfg->rx_size_thresh0  >> 5));
+    rxFlowRegs->RX_FLOW_CONFIG[index].RX_FLOW_CONFIG_REG_F = reg;
+
+    /* Rx flow configuration register G */
+    reg = 0;
+    CSL_FINS (reg, CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_G_RX_FDQ0_SZ1_QNUM, cfg->rx_fdq0_sz1_qnum);
+    CSL_FINS (reg, CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_G_RX_FDQ0_SZ1_QMGR, cfg->rx_fdq0_sz1_qmgr);
+    CSL_FINS (reg, CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_G_RX_SIZE_THRESH2, (cfg->rx_size_thresh2) >> 5);
+    rxFlowRegs->RX_FLOW_CONFIG[index].RX_FLOW_CONFIG_REG_G = reg;
+
+    /* Rx flow configuration register H */
+    reg = 0;
+    CSL_FINS (reg, CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ3_QNUM, cfg->rx_fdq0_sz3_qnum);
+    CSL_FINS (reg, CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ3_QMGR, cfg->rx_fdq0_sz3_qmgr);
+    CSL_FINS (reg, CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ2_QNUM, cfg->rx_fdq0_sz2_qnum);
+    CSL_FINS (reg, CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ2_QMGR, cfg->rx_fdq0_sz2_qmgr);
+    rxFlowRegs->RX_FLOW_CONFIG[index].RX_FLOW_CONFIG_REG_H = reg;
+
+    return 0;
+}
+    
+/**
+ *  @b Description
+ *  @n  
+ *      This function opens a CPPI transmit channel. 
+ */
+static inline int ti_em_cppi_tx_channel_open (
+    Cppi_Handle hnd,
+    Cppi_GlobalCPDMAConfigParams *cppiGblCfgParams,
+    Cppi_TxChInitCfg *cfg)
+{
+    CSL_Cppidma_tx_scheduler_configRegs *txSchedRegs;
+    CSL_Cppidma_tx_channel_configRegs   *txChRegs;
+    int32_t chNum  = -1;
+
+    if (cfg == NULL)
+        return -1;
+
+    chNum       = cfg->channelNum;
+    txSchedRegs = cppiGblCfgParams[(uint32_t) hnd].txSchedRegs;
+    txChRegs    = cppiGblCfgParams[(uint32_t) hnd].txChRegs;
+
+    CSL_FINS (txSchedRegs->TX_CHANNEL_SCHEDULER_CONFIG_REG[chNum],
+	      CPPIDMA_TX_SCHEDULER_CONFIG_TX_CHANNEL_SCHEDULER_CONFIG_REG_PRIORITY, cfg->priority);
+
+    CSL_FINS (txChRegs->TX_CHANNEL_GLOBAL_CONFIG[chNum].TX_CHANNEL_GLOBAL_CONFIG_REG_B,
+	      CPPIDMA_TX_CHANNEL_CONFIG_TX_CHANNEL_GLOBAL_CONFIG_REG_B_TX_FILT_EINFO, cfg->filterEPIB);
+    
+    CSL_FINS (txChRegs->TX_CHANNEL_GLOBAL_CONFIG[chNum].TX_CHANNEL_GLOBAL_CONFIG_REG_B, 
+	      CPPIDMA_TX_CHANNEL_CONFIG_TX_CHANNEL_GLOBAL_CONFIG_REG_B_TX_FILT_PSWORDS, cfg->filterPS);
+    
+    CSL_FINS (txChRegs->TX_CHANNEL_GLOBAL_CONFIG[chNum].TX_CHANNEL_GLOBAL_CONFIG_REG_B, 
+	      CPPIDMA_TX_CHANNEL_CONFIG_TX_CHANNEL_GLOBAL_CONFIG_REG_B_TX_AIF_MONO_MODE, cfg->aifMonoMode);
+    
+    if (cfg->txEnable)
+    {
+	uint32_t value = 0;
+	CSL_FINS (value, CPPIDMA_TX_CHANNEL_CONFIG_TX_CHANNEL_GLOBAL_CONFIG_REG_A_TX_ENABLE, cfg->txEnable);
+	txChRegs->TX_CHANNEL_GLOBAL_CONFIG[chNum].TX_CHANNEL_GLOBAL_CONFIG_REG_A = value;
+    }
+    return 0;
+}
+
+/**
+ *  @b Description
+ *  @n  
+ *      This function opens a CPPI transmit channel. 
+ */
+static inline int ti_em_cppi_rx_channel_open (
+    Cppi_Handle hnd,
+    Cppi_GlobalCPDMAConfigParams *cppiGblCfgParams,
+    Cppi_RxChInitCfg *cfg)
+{
+    CSL_Cppidma_rx_channel_configRegs *rxChRegs;
+    int32_t chNum = -1;
+    uint32_t value = 0;
+
+    if (cfg == NULL)
+        return -1;
+
+    chNum    = cfg->channelNum;
+    rxChRegs = cppiGblCfgParams[(uint32_t) hnd].rxChRegs;
+
+    CSL_FINS (value, CPPIDMA_RX_CHANNEL_CONFIG_RX_CHANNEL_GLOBAL_CONFIG_REG_RX_ENABLE, cfg->rxEnable);
+    rxChRegs->RX_CHANNEL_GLOBAL_CONFIG[chNum].RX_CHANNEL_GLOBAL_CONFIG_REG = value;
+
+    return 0;
+}
+
+/**
+ * @brief Map PDK HAL to Linux OSAL
+ */
+#define ti_em_rx_flow_open          ti_em_osal_cppi_rx_flow_open
+#define ti_em_rx_channel_open       ti_em_osal_cppi_rx_channel_open
+#define ti_em_tx_channel_open       ti_em_osal_cppi_tx_channel_open
+#define ti_em_rx_flow_close         ti_em_osal_cppi_rx_flow_close
+#define ti_em_rx_channel_close      ti_em_osal_cppi_rx_channel_close
+#define ti_em_tx_channel_close      ti_em_osal_cppi_tx_channel_close
+
+#define ti_em_chain_rx_flow_open    ti_em_osal_chain_rx_flow_open
+
+#define ti_em_xge_rx_flow_open      ti_em_osal_xge_rx_flow_open
+#define ti_em_xge_tx_channel_open   ti_em_osal_xge_tx_channel_open
+#define ti_em_xge_rx_channel_open   ti_em_osal_xge_rx_channel_open
+#define ti_em_xge_tx_queue_open     ti_em_osal_xge_tx_queue_open
+#define ti_em_xge_rx_flow_close     ti_em_osal_xge_rx_flow_close
+#define ti_em_xge_rx_channel_close  ti_em_osal_xge_rx_channel_close
+#define ti_em_xge_tx_channel_close  ti_em_osal_xge_tx_channel_close
+#define ti_em_xge_tx_queue_base_idx_get ti_em_osal_xge_tx_queue_base_idx_get
+
+#define ti_em_rio_rx_flow_open      ti_em_osal_rio_rx_flow_open
+#define ti_em_rio_tx_channel_open   ti_em_osal_rio_tx_channel_open
+#define ti_em_rio_tx_queue_open     ti_em_osal_rio_tx_queue_open
+
+#define ti_em_get_absolute_queue_id ti_em_osal_cppi_get_absolute_queue_id
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*TI_EM_HW_CPPI_H_*/
diff --git a/platform/linux-keystone2/prebuilts/openem/include/linux/keystone2/ti_em_hw_csl.h b/platform/linux-keystone2/prebuilts/openem/include/linux/keystone2/ti_em_hw_csl.h
new file mode 100644
index 0000000..7f8f63f
--- /dev/null
+++ b/platform/linux-keystone2/prebuilts/openem/include/linux/keystone2/ti_em_hw_csl.h
@@ -0,0 +1,1146 @@
+/*
+ * Copyright (c) 2012, Texas Instruments Incorporated - http://www.ti.com/
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *       * Redistributions of source code must retain the above copyright
+ *         notice, this list of conditions and the following disclaimer.
+ *       * Redistributions in binary form must reproduce the above copyright
+ *         notice, this list of conditions and the following disclaimer in the
+ *         documentation and/or other materials provided with the distribution.
+ *       * Neither the name of Texas Instruments Incorporated nor the
+ *         names of its contributors may be used to endorse or promote products
+ *         derived from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ *   WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY
+ *   DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ *   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *   ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/**
+ *   @file  ti_em_hw_csl.h
+ *
+ *   @brief   
+ *      This is the Chip Support Library definition file
+ *
+ */
+
+#ifndef TI_EM_HW_CSL_H_
+#define TI_EM_HW_CSL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef STD_
+
+/*
+ * Aliases for standard C types
+ */
+typedef int		Int;
+typedef unsigned	Uns;
+typedef char		Char;
+
+/* pointer to null-terminated character sequence */
+typedef char	       *String;
+
+typedef void	       *Ptr;		/* pointer to arbitrary type */
+
+typedef unsigned short	Bool;		/* boolean */
+
+#endif /* STD_ */
+
+/* Unsigned integer definitions (32bit, 16bit, 8bit) follow... */
+typedef unsigned int	Uint32;
+typedef unsigned short	Uint16;
+typedef unsigned char	Uint8;
+
+/* Signed integer definitions (32bit, 16bit, 8bit) follow... */
+typedef int		Int32;
+typedef short		Int16;
+typedef char		Int8;
+
+/* the "expression" macros */
+
+/* the Field MaKe macro */
+#define CSL_FMK(PER_REG_FIELD, val)                                         \
+    (((val) << CSL_##PER_REG_FIELD##_SHIFT) & CSL_##PER_REG_FIELD##_MASK)
+
+/* the Field EXTract macro */
+#define CSL_FEXT(reg, PER_REG_FIELD)                                        \
+    (((reg) & CSL_##PER_REG_FIELD##_MASK) >> CSL_##PER_REG_FIELD##_SHIFT)
+
+/* the Field INSert macro */
+#define CSL_FINS(reg, PER_REG_FIELD, val)                                   \
+    ((reg) = ((reg) & ~CSL_##PER_REG_FIELD##_MASK)                          \
+    | CSL_FMK(PER_REG_FIELD, val))
+
+
+/* the "token" macros */
+
+/* the Field MaKe (Token) macro */
+#define CSL_FMKT(PER_REG_FIELD, TOKEN)                                      \
+    CSL_FMK(PER_REG_FIELD, CSL_##PER_REG_FIELD##_##TOKEN)
+
+/* the Field INSert (Token) macro */
+#define CSL_FINST(reg, PER_REG_FIELD, TOKEN)                                \
+    CSL_FINS((reg), PER_REG_FIELD, CSL_##PER_REG_FIELD##_##TOKEN)
+
+
+/* the "raw" macros */
+
+/* the Field MaKe (Raw) macro */
+#define CSL_FMKR(msb, lsb, val)                                             \
+    (((val) & ((1 << ((msb) - (lsb) + 1)) - 1)) << (lsb))
+
+/* the Field EXTract (Raw) macro */
+#define CSL_FEXTR(reg, msb, lsb)                                            \
+    (((reg) >> (lsb)) & ((1 << ((msb) - (lsb) + 1)) - 1))
+
+/* the Field INSert (Raw) macro */
+#define CSL_FINSR(reg, msb, lsb, val)                                       \
+    ((reg) = ((reg) &~ (((1 << ((msb) - (lsb) + 1)) - 1) << (lsb)))         \
+    | CSL_FMKR(msb, lsb, val))
+
+/**************************************************************************\
+* Register Overlay Structure
+\**************************************************************************/
+typedef struct CSL_Qm_Queue_Status
+{
+    volatile Uint32 QUEUE_THRESHOLD_STATUS_REG[256];
+}CSL_Qm_Queue_Status;
+
+/**************************************************************************\
+* Register Overlay Structure
+\**************************************************************************/
+typedef struct  {
+    volatile Uint32 REVISION_REG;
+    volatile Uint8 RSVD0[4];
+    volatile Uint32 QUEUE_DIVERSION_REG;
+    volatile Uint32 LINKING_RAM_REGION_0_BASE_ADDRESS_REG;
+    volatile Uint32 LINKING_RAM_REGION_0_SIZE_REG;
+    volatile Uint32 LINKING_RAM_REGION_1_BASE_ADDRESS_REG;
+    volatile Uint8 RSVD1[8];
+    volatile Uint32 FREE_DESCRIPTOR_STARVE_COUNT_REG[16];
+} CSL_Qm_configRegs;
+
+/**************************************************************************\
+* Field Definition Macros
+\**************************************************************************/
+
+/* REVISION_REG */
+
+#define CSL_QM_CONFIG_REVISION_REG_SCHEME_MASK (0xC0000000u)
+#define CSL_QM_CONFIG_REVISION_REG_SCHEME_SHIFT (0x0000001Eu)
+#define CSL_QM_CONFIG_REVISION_REG_SCHEME_RESETVAL (0x00000001u)
+
+#define CSL_QM_CONFIG_REVISION_REG_FUNCTION_MASK (0x0FFF0000u)
+#define CSL_QM_CONFIG_REVISION_REG_FUNCTION_SHIFT (0x00000010u)
+#define CSL_QM_CONFIG_REVISION_REG_FUNCTION_RESETVAL (0x00000E5Du)
+
+#define CSL_QM_CONFIG_REVISION_REG_REVRTL_MASK (0x0000F800u)
+#define CSL_QM_CONFIG_REVISION_REG_REVRTL_SHIFT (0x0000000Bu)
+#define CSL_QM_CONFIG_REVISION_REG_REVRTL_RESETVAL (0x00000000u)
+
+#define CSL_QM_CONFIG_REVISION_REG_REVMAJ_MASK (0x00000700u)
+#define CSL_QM_CONFIG_REVISION_REG_REVMAJ_SHIFT (0x00000008u)
+#define CSL_QM_CONFIG_REVISION_REG_REVMAJ_RESETVAL (0x00000001u)
+
+#define CSL_QM_CONFIG_REVISION_REG_REVCUSTOM_MASK (0x000000C0u)
+#define CSL_QM_CONFIG_REVISION_REG_REVCUSTOM_SHIFT (0x00000006u)
+#define CSL_QM_CONFIG_REVISION_REG_REVCUSTOM_RESETVAL (0x00000000u)
+
+#define CSL_QM_CONFIG_REVISION_REG_REVMIN_MASK (0x0000003Fu)
+#define CSL_QM_CONFIG_REVISION_REG_REVMIN_SHIFT (0x00000000u)
+#define CSL_QM_CONFIG_REVISION_REG_REVMIN_RESETVAL (0x00000005u)
+
+#define CSL_QM_CONFIG_REVISION_REG_RESETVAL (0x4E5D0105u)
+
+/* QUEUE_DIVERSION_REG */
+
+#define CSL_QM_CONFIG_QUEUE_DIVERSION_REG_HEAD_TAIL_MASK (0x80000000u)
+#define CSL_QM_CONFIG_QUEUE_DIVERSION_REG_HEAD_TAIL_SHIFT (0x0000001Fu)
+#define CSL_QM_CONFIG_QUEUE_DIVERSION_REG_HEAD_TAIL_RESETVAL (0x00000000u)
+
+#define CSL_QM_CONFIG_QUEUE_DIVERSION_REG_DEST_QNUM_MASK (0x3FFF0000u)
+#define CSL_QM_CONFIG_QUEUE_DIVERSION_REG_DEST_QNUM_SHIFT (0x00000010u)
+#define CSL_QM_CONFIG_QUEUE_DIVERSION_REG_DEST_QNUM_RESETVAL (0x00000000u)
+
+#define CSL_QM_CONFIG_QUEUE_DIVERSION_REG_SOURCE_QNUM_MASK (0x00003FFFu)
+#define CSL_QM_CONFIG_QUEUE_DIVERSION_REG_SOURCE_QNUM_SHIFT (0x00000000u)
+#define CSL_QM_CONFIG_QUEUE_DIVERSION_REG_SOURCE_QNUM_RESETVAL (0x00000000u)
+
+#define CSL_QM_CONFIG_QUEUE_DIVERSION_REG_RESETVAL (0x00000000u)
+
+/* LINKING_RAM_REGION_0_BASE_ADDRESS_REG */
+
+#define CSL_QM_CONFIG_LINKING_RAM_REGION_0_BASE_ADDRESS_REG_REGION0_BASE_MASK (0xFFFFFFFFu)
+#define CSL_QM_CONFIG_LINKING_RAM_REGION_0_BASE_ADDRESS_REG_REGION0_BASE_SHIFT (0x00000000u)
+#define CSL_QM_CONFIG_LINKING_RAM_REGION_0_BASE_ADDRESS_REG_REGION0_BASE_RESETVAL (0x00000000u)
+
+#define CSL_QM_CONFIG_LINKING_RAM_REGION_0_BASE_ADDRESS_REG_RESETVAL (0x00000000u)
+
+/* LINKING_RAM_REGION_0_SIZE_REG */
+
+#define CSL_QM_CONFIG_LINKING_RAM_REGION_0_SIZE_REG_REGION0_SIZE_MASK (0x0007FFFFu)
+#define CSL_QM_CONFIG_LINKING_RAM_REGION_0_SIZE_REG_REGION0_SIZE_SHIFT (0x00000000u)
+#define CSL_QM_CONFIG_LINKING_RAM_REGION_0_SIZE_REG_REGION0_SIZE_RESETVAL (0x00000000u)
+
+#define CSL_QM_CONFIG_LINKING_RAM_REGION_0_SIZE_REG_RESETVAL (0x00000000u)
+
+/* LINKING_RAM_REGION_1_BASE_ADDRESS_REG */
+
+#define CSL_QM_CONFIG_LINKING_RAM_REGION_1_BASE_ADDRESS_REG_REGION1_BASE_MASK (0xFFFFFFFFu)
+#define CSL_QM_CONFIG_LINKING_RAM_REGION_1_BASE_ADDRESS_REG_REGION1_BASE_SHIFT (0x00000000u)
+#define CSL_QM_CONFIG_LINKING_RAM_REGION_1_BASE_ADDRESS_REG_REGION1_BASE_RESETVAL (0x00000000u)
+
+#define CSL_QM_CONFIG_LINKING_RAM_REGION_1_BASE_ADDRESS_REG_RESETVAL (0x00000000u)
+
+/* FREE_DESCRIPTOR_STARVE_COUNT_REG */
+
+#define CSL_QM_CONFIG_FREE_DESCRIPTOR_STARVE_COUNT_REG_FDBQ3_STARVE_CNT_MASK (0xFF000000u)
+#define CSL_QM_CONFIG_FREE_DESCRIPTOR_STARVE_COUNT_REG_FDBQ3_STARVE_CNT_SHIFT (0x00000018u)
+#define CSL_QM_CONFIG_FREE_DESCRIPTOR_STARVE_COUNT_REG_FDBQ3_STARVE_CNT_RESETVAL (0x00000000u)
+
+#define CSL_QM_CONFIG_FREE_DESCRIPTOR_STARVE_COUNT_REG_FDBQ2_STARVE_CNT_MASK (0x00FF0000u)
+#define CSL_QM_CONFIG_FREE_DESCRIPTOR_STARVE_COUNT_REG_FDBQ2_STARVE_CNT_SHIFT (0x00000010u)
+#define CSL_QM_CONFIG_FREE_DESCRIPTOR_STARVE_COUNT_REG_FDBQ2_STARVE_CNT_RESETVAL (0x00000000u)
+
+#define CSL_QM_CONFIG_FREE_DESCRIPTOR_STARVE_COUNT_REG_FDBQ1_STARVE_CNT_MASK (0x0000FF00u)
+#define CSL_QM_CONFIG_FREE_DESCRIPTOR_STARVE_COUNT_REG_FDBQ1_STARVE_CNT_SHIFT (0x00000008u)
+#define CSL_QM_CONFIG_FREE_DESCRIPTOR_STARVE_COUNT_REG_FDBQ1_STARVE_CNT_RESETVAL (0x00000000u)
+
+#define CSL_QM_CONFIG_FREE_DESCRIPTOR_STARVE_COUNT_REG_FDBQ0_STARVE_CNT_MASK (0x000000FFu)
+#define CSL_QM_CONFIG_FREE_DESCRIPTOR_STARVE_COUNT_REG_FDBQ0_STARVE_CNT_SHIFT (0x00000000u)
+#define CSL_QM_CONFIG_FREE_DESCRIPTOR_STARVE_COUNT_REG_FDBQ0_STARVE_CNT_RESETVAL (0x00000000u)
+
+#define CSL_QM_CONFIG_FREE_DESCRIPTOR_STARVE_COUNT_REG_RESETVAL (0x00000000u)
+
+/**************************************************************************\
+* Register Overlay Structure
+\**************************************************************************/
+typedef struct  {
+    volatile Uint32 MEMORY_REGION_BASE_ADDRESS_REG;
+    volatile Uint32 MEMORY_REGION_START_INDEX_REG;
+    volatile Uint32 MEMORY_REGION_DESCRIPTOR_SETUP_REG;
+    volatile Uint8 RSVD0[4];
+} CSL_Qm_descriptor_region_configMemory_region_base_address_groupRegs;
+
+/**************************************************************************\
+* Register Overlay Structure
+\**************************************************************************/
+typedef struct  {
+    CSL_Qm_descriptor_region_configMemory_region_base_address_groupRegs MEMORY_REGION_BASE_ADDRESS_GROUP[64];
+} CSL_Qm_descriptor_region_configRegs;
+
+/**************************************************************************\
+* Field Definition Macros
+\**************************************************************************/
+
+/* MEMORY_REGION_BASE_ADDRESS_REG */
+
+#define CSL_QM_DESCRIPTOR_REGION_CONFIG_MEMORY_REGION_BASE_ADDRESS_REG_REGR_BASE_MASK (0xFFFFFFFFu)
+#define CSL_QM_DESCRIPTOR_REGION_CONFIG_MEMORY_REGION_BASE_ADDRESS_REG_REGR_BASE_SHIFT (0x00000000u)
+#define CSL_QM_DESCRIPTOR_REGION_CONFIG_MEMORY_REGION_BASE_ADDRESS_REG_REGR_BASE_RESETVAL (0x00000000u)
+
+#define CSL_QM_DESCRIPTOR_REGION_CONFIG_MEMORY_REGION_BASE_ADDRESS_REG_RESETVAL (0x00000000u)
+
+/* MEMORY_REGION_START_INDEX_REG */
+
+#define CSL_QM_DESCRIPTOR_REGION_CONFIG_MEMORY_REGION_START_INDEX_REG_START_INDEX_MASK (0x0007FFFFu)
+#define CSL_QM_DESCRIPTOR_REGION_CONFIG_MEMORY_REGION_START_INDEX_REG_START_INDEX_SHIFT (0x00000000u)
+#define CSL_QM_DESCRIPTOR_REGION_CONFIG_MEMORY_REGION_START_INDEX_REG_START_INDEX_RESETVAL (0x00000000u)
+
+#define CSL_QM_DESCRIPTOR_REGION_CONFIG_MEMORY_REGION_START_INDEX_REG_RESETVAL (0x00000000u)
+
+/* MEMORY_REGION_DESCRIPTOR_SETUP_REG */
+
+#define CSL_QM_DESCRIPTOR_REGION_CONFIG_MEMORY_REGION_DESCRIPTOR_SETUP_REG_DESC_SIZE_MASK (0x1FFF0000u)
+#define CSL_QM_DESCRIPTOR_REGION_CONFIG_MEMORY_REGION_DESCRIPTOR_SETUP_REG_DESC_SIZE_SHIFT (0x00000010u)
+#define CSL_QM_DESCRIPTOR_REGION_CONFIG_MEMORY_REGION_DESCRIPTOR_SETUP_REG_DESC_SIZE_RESETVAL (0x00000000u)
+
+#define CSL_QM_DESCRIPTOR_REGION_CONFIG_MEMORY_REGION_DESCRIPTOR_SETUP_REG_REG_SIZE_MASK (0x0000000Fu)
+#define CSL_QM_DESCRIPTOR_REGION_CONFIG_MEMORY_REGION_DESCRIPTOR_SETUP_REG_REG_SIZE_SHIFT (0x00000000u)
+#define CSL_QM_DESCRIPTOR_REGION_CONFIG_MEMORY_REGION_DESCRIPTOR_SETUP_REG_REG_SIZE_RESETVAL (0x00000000u)
+
+#define CSL_QM_DESCRIPTOR_REGION_CONFIG_MEMORY_REGION_DESCRIPTOR_SETUP_REG_RESETVAL (0x00000000u)
+
+/**************************************************************************\
+* Register Overlay Structure for QUEUE_MGMT_GROUP
+\**************************************************************************/
+typedef struct  {
+    volatile Uint32 QUEUE_REG_A;
+    volatile Uint32 QUEUE_REG_B;
+    volatile Uint32 QUEUE_REG_C;
+    volatile Uint32 QUEUE_REG_D;
+} CSL_Qm_queue_managementQueue_mgmt_groupRegs;
+
+/**************************************************************************\
+* Register Overlay Structure
+\**************************************************************************/
+typedef struct  {
+    CSL_Qm_queue_managementQueue_mgmt_groupRegs QUEUE_MGMT_GROUP[8192];
+} CSL_Qm_queue_managementRegs;
+
+/**************************************************************************\
+* Field Definition Macros
+\**************************************************************************/
+
+/* QUEUE_REG_A */
+
+#define CSL_QM_QUEUE_MANAGEMENT_QUEUE_REG_A_QUEUE_ENTRY_COUNT_MASK (0x0007FFFFu)
+#define CSL_QM_QUEUE_MANAGEMENT_QUEUE_REG_A_QUEUE_ENTRY_COUNT_SHIFT (0x00000000u)
+#define CSL_QM_QUEUE_MANAGEMENT_QUEUE_REG_A_QUEUE_ENTRY_COUNT_RESETVAL (0x00000000u)
+
+#define CSL_QM_QUEUE_MANAGEMENT_QUEUE_REG_A_RESETVAL (0x00000000u)
+
+/* QUEUE_REG_B */
+
+#define CSL_QM_QUEUE_MANAGEMENT_QUEUE_REG_B_QUEUE_BYTE_COUNT_MASK (0xFFFFFFFFu)
+#define CSL_QM_QUEUE_MANAGEMENT_QUEUE_REG_B_QUEUE_BYTE_COUNT_SHIFT (0x00000000u)
+#define CSL_QM_QUEUE_MANAGEMENT_QUEUE_REG_B_QUEUE_BYTE_COUNT_RESETVAL (0x00000000u)
+
+#define CSL_QM_QUEUE_MANAGEMENT_QUEUE_REG_B_RESETVAL (0x00000000u)
+
+/* QUEUE_REG_C */
+
+#define CSL_QM_QUEUE_MANAGEMENT_QUEUE_REG_C_HEAD_TAIL_MASK (0x80000000u)
+#define CSL_QM_QUEUE_MANAGEMENT_QUEUE_REG_C_HEAD_TAIL_SHIFT (0x0000001Fu)
+#define CSL_QM_QUEUE_MANAGEMENT_QUEUE_REG_C_HEAD_TAIL_RESETVAL (0x00000000u)
+
+#define CSL_QM_QUEUE_MANAGEMENT_QUEUE_REG_C_PACKET_SIZE_MASK (0x0001FFFFu)
+#define CSL_QM_QUEUE_MANAGEMENT_QUEUE_REG_C_PACKET_SIZE_SHIFT (0x00000000u)
+#define CSL_QM_QUEUE_MANAGEMENT_QUEUE_REG_C_PACKET_SIZE_RESETVAL (0x00000000u)
+
+#define CSL_QM_QUEUE_MANAGEMENT_QUEUE_REG_C_RESETVAL (0x00000000u)
+
+/* QUEUE_REG_D */
+
+#define CSL_QM_QUEUE_MANAGEMENT_QUEUE_REG_D_DESC_PTR_MASK (0xFFFFFFF0u)
+#define CSL_QM_QUEUE_MANAGEMENT_QUEUE_REG_D_DESC_PTR_SHIFT (0x00000004u)
+#define CSL_QM_QUEUE_MANAGEMENT_QUEUE_REG_D_DESC_PTR_RESETVAL (0x00000000u)
+
+#define CSL_QM_QUEUE_MANAGEMENT_QUEUE_REG_D_DESC_INFO_MASK (0x0000000Fu)
+#define CSL_QM_QUEUE_MANAGEMENT_QUEUE_REG_D_DESC_INFO_SHIFT (0x00000000u)
+#define CSL_QM_QUEUE_MANAGEMENT_QUEUE_REG_D_DESC_INFO_RESETVAL (0x00000000u)
+
+#define CSL_QM_QUEUE_MANAGEMENT_QUEUE_REG_D_RESETVAL (0x00000000u)
+
+/**************************************************************************\
+* Register Overlay Structure for QUEUE_STATUS_CONFIG_GROUP
+\**************************************************************************/
+typedef struct  {
+    volatile Uint32 QUEUE_STATUS_CONFIG_REG_A;
+    volatile Uint32 QUEUE_STATUS_CONFIG_REG_B;
+    volatile Uint32 QUEUE_STATUS_CONFIG_REG_C;
+    volatile Uint32 QUEUE_STATUS_CONFIG_REG_D;
+} CSL_Qm_queue_status_configQueue_status_config_groupRegs;
+
+/**************************************************************************\
+* Register Overlay Structure
+\**************************************************************************/
+typedef struct  {
+    CSL_Qm_queue_status_configQueue_status_config_groupRegs QUEUE_STATUS_CONFIG_GROUP[8192];
+} CSL_Qm_queue_status_configRegs;
+
+/**************************************************************************\
+* Field Definition Macros
+\**************************************************************************/
+
+/* QUEUE_STATUS_CONFIG_REG_A */
+
+#define CSL_QM_QUEUE_STATUS_CONFIG_QUEUE_STATUS_CONFIG_REG_A_QUEUE_ENTRY_COUNT_MASK (0x0007FFFFu)
+#define CSL_QM_QUEUE_STATUS_CONFIG_QUEUE_STATUS_CONFIG_REG_A_QUEUE_ENTRY_COUNT_SHIFT (0x00000000u)
+#define CSL_QM_QUEUE_STATUS_CONFIG_QUEUE_STATUS_CONFIG_REG_A_QUEUE_ENTRY_COUNT_RESETVAL (0x00000000u)
+
+#define CSL_QM_QUEUE_STATUS_CONFIG_QUEUE_STATUS_CONFIG_REG_A_RESETVAL (0x00000000u)
+
+/* QUEUE_STATUS_CONFIG_REG_B */
+
+#define CSL_QM_QUEUE_STATUS_CONFIG_QUEUE_STATUS_CONFIG_REG_B_QUEUE_BYTE_COUNT_MASK (0xFFFFFFFFu)
+#define CSL_QM_QUEUE_STATUS_CONFIG_QUEUE_STATUS_CONFIG_REG_B_QUEUE_BYTE_COUNT_SHIFT (0x00000000u)
+#define CSL_QM_QUEUE_STATUS_CONFIG_QUEUE_STATUS_CONFIG_REG_B_QUEUE_BYTE_COUNT_RESETVAL (0x00000000u)
+
+#define CSL_QM_QUEUE_STATUS_CONFIG_QUEUE_STATUS_CONFIG_REG_B_RESETVAL (0x00000000u)
+
+/* QUEUE_STATUS_CONFIG_REG_C */
+
+#define CSL_QM_QUEUE_STATUS_CONFIG_QUEUE_STATUS_CONFIG_REG_C_PACKET_SIZE_MASK (0x0001FFFFu)
+#define CSL_QM_QUEUE_STATUS_CONFIG_QUEUE_STATUS_CONFIG_REG_C_PACKET_SIZE_SHIFT (0x00000000u)
+#define CSL_QM_QUEUE_STATUS_CONFIG_QUEUE_STATUS_CONFIG_REG_C_PACKET_SIZE_RESETVAL (0x00000000u)
+
+#define CSL_QM_QUEUE_STATUS_CONFIG_QUEUE_STATUS_CONFIG_REG_C_RESETVAL (0x00000000u)
+
+/* QUEUE_STATUS_CONFIG_REG_D */
+
+#define CSL_QM_QUEUE_STATUS_CONFIG_QUEUE_STATUS_CONFIG_REG_D_THRESHOLD_MASK (0x0000000Fu)
+#define CSL_QM_QUEUE_STATUS_CONFIG_QUEUE_STATUS_CONFIG_REG_D_THRESHOLD_SHIFT (0x00000000u)
+#define CSL_QM_QUEUE_STATUS_CONFIG_QUEUE_STATUS_CONFIG_REG_D_THRESHOLD_RESETVAL (0x00000000u)
+
+#define CSL_QM_QUEUE_STATUS_CONFIG_QUEUE_STATUS_CONFIG_REG_D_THRESHOLD_HILO_MASK (0x00000080u)
+#define CSL_QM_QUEUE_STATUS_CONFIG_QUEUE_STATUS_CONFIG_REG_D_THRESHOLD_HILO_SHIFT (0x00000007u)
+#define CSL_QM_QUEUE_STATUS_CONFIG_QUEUE_STATUS_CONFIG_REG_D_THRESHOLD_HILO_RESETVAL (0x00000000u)
+
+#define CSL_QM_QUEUE_STATUS_CONFIG_QUEUE_STATUS_CONFIG_REG_D_RESETVAL (0x00000000u)
+
+/**************************************************************************\
+* Register Overlay Structure
+\**************************************************************************/
+typedef struct  {
+    volatile Uint32 REVISION_REG;
+    volatile Uint8 RSVD0[12];
+    volatile Uint32 EOI_REG;
+    volatile Uint32 INTR_VECTOR_REG;
+    volatile Uint8 RSVD1[488];
+    volatile Uint32 STATUS_REG0;
+    volatile Uint32 STATUS_REG1;
+    volatile Uint32 STATUS_REG2;
+    volatile Uint32 STATUS_REG3;
+    volatile Uint32 STATUS_REG4;
+    volatile Uint8 RSVD2[108];
+    volatile Uint32 STATUS_CLR_REG0;
+    volatile Uint32 STATUS_CLR_REG1;
+    volatile Uint8 RSVD3[8];
+    volatile Uint32 STATUS_CLR_REG4;
+    volatile Uint8 RSVD4[108];
+    volatile Uint32 INTCNT_REG[50];
+    volatile Uint8 RSVD5[184];
+    volatile Uint32 INTR_VECTOR_REG_HOST;
+} CSL_Qm_intdRegs;
+
+/**************************************************************************\
+* Field Definition Macros
+\**************************************************************************/
+
+/* REVISION_REG */
+
+#define CSL_QM_INTD_REVISION_REG_SCHEME_MASK (0xC0000000u)
+#define CSL_QM_INTD_REVISION_REG_SCHEME_SHIFT (0x0000001Eu)
+#define CSL_QM_INTD_REVISION_REG_SCHEME_RESETVAL (0x00000001u)
+
+#define CSL_QM_INTD_REVISION_REG_MODULE_MASK (0x0FFF0000u)
+#define CSL_QM_INTD_REVISION_REG_MODULE_SHIFT (0x00000010u)
+#define CSL_QM_INTD_REVISION_REG_MODULE_RESETVAL (0x00000E83u)
+
+#define CSL_QM_INTD_REVISION_REG_REV_RTL_MASK (0x0000F800u)
+#define CSL_QM_INTD_REVISION_REG_REV_RTL_SHIFT (0x0000000Bu)
+#define CSL_QM_INTD_REVISION_REG_REV_RTL_RESETVAL (0x00000016u)
+
+#define CSL_QM_INTD_REVISION_REG_REV_MAJOR_MASK (0x00000700u)
+#define CSL_QM_INTD_REVISION_REG_REV_MAJOR_SHIFT (0x00000008u)
+#define CSL_QM_INTD_REVISION_REG_REV_MAJOR_RESETVAL (0x00000001u)
+
+#define CSL_QM_INTD_REVISION_REG_REV_CUSTOM_MASK (0x000000C0u)
+#define CSL_QM_INTD_REVISION_REG_REV_CUSTOM_SHIFT (0x00000006u)
+#define CSL_QM_INTD_REVISION_REG_REV_CUSTOM_RESETVAL (0x00000000u)
+
+#define CSL_QM_INTD_REVISION_REG_REV_MINOR_MASK (0x0000003Fu)
+#define CSL_QM_INTD_REVISION_REG_REV_MINOR_SHIFT (0x00000000u)
+#define CSL_QM_INTD_REVISION_REG_REV_MINOR_RESETVAL (0x00000000u)
+
+#define CSL_QM_INTD_REVISION_REG_RESETVAL (0x4E83B100u)
+
+/* EOI_REG */
+
+#define CSL_QM_INTD_EOI_REG_EOI_VECTOR_MASK (0x000000FFu)
+#define CSL_QM_INTD_EOI_REG_EOI_VECTOR_SHIFT (0x00000000u)
+#define CSL_QM_INTD_EOI_REG_EOI_VECTOR_RESETVAL (0x00000000u)
+
+#define CSL_QM_INTD_EOI_REG_RESETVAL     (0x00000000u)
+
+/* INTR_VECTOR_REG */
+
+#define CSL_QM_INTD_INTR_VECTOR_REG_INTR_VECTOR_MASK (0xFFFFFFFFu)
+#define CSL_QM_INTD_INTR_VECTOR_REG_INTR_VECTOR_SHIFT (0x00000000u)
+#define CSL_QM_INTD_INTR_VECTOR_REG_INTR_VECTOR_RESETVAL (0x00000000u)
+
+#define CSL_QM_INTD_INTR_VECTOR_REG_RESETVAL (0x00000000u)
+
+/* STATUS_REG0 */
+
+#define CSL_QM_INTD_STATUS_REG0_STATUS_HOST_HI_IN_INTR_MASK (0xFFFFFFFFu)
+#define CSL_QM_INTD_STATUS_REG0_STATUS_HOST_HI_IN_INTR_SHIFT (0x00000000u)
+#define CSL_QM_INTD_STATUS_REG0_STATUS_HOST_HI_IN_INTR_RESETVAL (0x00000000u)
+
+#define CSL_QM_INTD_STATUS_REG0_RESETVAL (0x00000000u)
+
+/* STATUS_REG1 */
+
+#define CSL_QM_INTD_STATUS_REG1_STATUS_HOST_LO_IN_INTR_MASK (0x0000FFFFu)
+#define CSL_QM_INTD_STATUS_REG1_STATUS_HOST_LO_IN_INTR_SHIFT (0x00000000u)
+#define CSL_QM_INTD_STATUS_REG1_STATUS_HOST_LO_IN_INTR_RESETVAL (0x00000000u)
+
+#define CSL_QM_INTD_STATUS_REG1_RESETVAL (0x00000000u)
+
+/* STATUS_REG2 */
+
+#define CSL_QM_INTD_STATUS_REG2_STATUS_HOST_HI_LINTR_MASK (0xFFFFFFFFu)
+#define CSL_QM_INTD_STATUS_REG2_STATUS_HOST_HI_LINTR_SHIFT (0x00000000u)
+#define CSL_QM_INTD_STATUS_REG2_STATUS_HOST_HI_LINTR_RESETVAL (0x00000000u)
+
+#define CSL_QM_INTD_STATUS_REG2_RESETVAL (0x00000000u)
+
+/* STATUS_REG3 */
+
+#define CSL_QM_INTD_STATUS_REG3_STATUS_HOST_LO_LINTR_MASK (0x0001FFFFu)
+#define CSL_QM_INTD_STATUS_REG3_STATUS_HOST_LO_LINTR_SHIFT (0x00000000u)
+#define CSL_QM_INTD_STATUS_REG3_STATUS_HOST_LO_LINTR_RESETVAL (0x00000000u)
+
+#define CSL_QM_INTD_STATUS_REG3_RESETVAL (0x00000000u)
+
+/* STATUS_REG4 */
+
+#define CSL_QM_INTD_STATUS_REG4_STATUS_HOST_CDMA_STARVE0_MASK (0x00000001u)
+#define CSL_QM_INTD_STATUS_REG4_STATUS_HOST_CDMA_STARVE0_SHIFT (0x00000000u)
+#define CSL_QM_INTD_STATUS_REG4_STATUS_HOST_CDMA_STARVE0_RESETVAL (0x00000000u)
+
+#define CSL_QM_INTD_STATUS_REG4_STATUS_HOST_CDMA_STARVE1_MASK (0x00000002u)
+#define CSL_QM_INTD_STATUS_REG4_STATUS_HOST_CDMA_STARVE1_SHIFT (0x00000001u)
+#define CSL_QM_INTD_STATUS_REG4_STATUS_HOST_CDMA_STARVE1_RESETVAL (0x00000000u)
+
+#define CSL_QM_INTD_STATUS_REG4_RESETVAL (0x00000000u)
+
+/* STATUS_CLR_REG0 */
+
+#define CSL_QM_INTD_STATUS_CLR_REG0_STATUS_HOST_HI_IN_INTR_CLR_MASK (0xFFFFFFFFu)
+#define CSL_QM_INTD_STATUS_CLR_REG0_STATUS_HOST_HI_IN_INTR_CLR_SHIFT (0x00000000u)
+#define CSL_QM_INTD_STATUS_CLR_REG0_STATUS_HOST_HI_IN_INTR_CLR_RESETVAL (0x00000000u)
+
+#define CSL_QM_INTD_STATUS_CLR_REG0_RESETVAL (0x00000000u)
+
+/* STATUS_CLR_REG1 */
+
+#define CSL_QM_INTD_STATUS_CLR_REG1_STATUS_HOST_LO_IN_INTR_CLR_MASK (0x0000FFFFu)
+#define CSL_QM_INTD_STATUS_CLR_REG1_STATUS_HOST_LO_IN_INTR_CLR_SHIFT (0x00000000u)
+#define CSL_QM_INTD_STATUS_CLR_REG1_STATUS_HOST_LO_IN_INTR_CLR_RESETVAL (0x00000000u)
+
+#define CSL_QM_INTD_STATUS_CLR_REG1_RESETVAL (0x00000000u)
+
+/* STATUS_CLR_REG4 */
+
+#define CSL_QM_INTD_STATUS_CLR_REG4_STATUS_HOST_CDMA_STARVE0_CLR_MASK (0x00000001u)
+#define CSL_QM_INTD_STATUS_CLR_REG4_STATUS_HOST_CDMA_STARVE0_CLR_SHIFT (0x00000000u)
+#define CSL_QM_INTD_STATUS_CLR_REG4_STATUS_HOST_CDMA_STARVE0_CLR_RESETVAL (0x00000000u)
+
+#define CSL_QM_INTD_STATUS_CLR_REG4_STATUS_HOST_CDMA_STARVE1_CLR_MASK (0x00000002u)
+#define CSL_QM_INTD_STATUS_CLR_REG4_STATUS_HOST_CDMA_STARVE1_CLR_SHIFT (0x00000001u)
+#define CSL_QM_INTD_STATUS_CLR_REG4_STATUS_HOST_CDMA_STARVE1_CLR_RESETVAL (0x00000000u)
+
+#define CSL_QM_INTD_STATUS_CLR_REG4_RESETVAL (0x00000000u)
+
+/* INTCNT_REG */
+
+#define CSL_QM_INTD_INTCNT_REG_INTCNT_HOST_CNT_HI_IN_INTR_MASK (0x000000FFu)
+#define CSL_QM_INTD_INTCNT_REG_INTCNT_HOST_CNT_HI_IN_INTR_SHIFT (0x00000000u)
+#define CSL_QM_INTD_INTCNT_REG_INTCNT_HOST_CNT_HI_IN_INTR_RESETVAL (0x00000000u)
+
+#define CSL_QM_INTD_INTCNT_REG_RESETVAL  (0x00000000u)
+
+/* INTR_VECTOR_REG_HOST */
+
+#define CSL_QM_INTD_INTR_VECTOR_REG_HOST_INTR_VECTOR_HOST_MASK (0xFFFFFFFFu)
+#define CSL_QM_INTD_INTR_VECTOR_REG_HOST_INTR_VECTOR_HOST_SHIFT (0x00000000u)
+#define CSL_QM_INTD_INTR_VECTOR_REG_HOST_INTR_VECTOR_HOST_RESETVAL (0x00000000u)
+
+#define CSL_QM_INTD_INTR_VECTOR_REG_HOST_RESETVAL (0x00000000u)
+
+/**************************************************************************\
+* Register Overlay Structure
+\**************************************************************************/
+typedef struct  {
+    volatile Uint32 PDSP_CONTROL_REG;
+    volatile Uint32 PDSP_STATUS_REG;
+    volatile Uint32 PDSP_WAKEUP_ENABLE_REG;
+    volatile Uint32 PDSP_CYCLE_COUNT_REG;
+    volatile Uint32 PDSP_STALL_COUNT_REG;
+    volatile Uint8 RSVD0[12];
+    volatile Uint32 PDSP_CONSTANT_TABLE_BLOCK_INDEX_REG_0;
+    volatile Uint32 PDSP_CONSTANT_TABLE_BLOCK_INDEX_REG_1;
+    volatile Uint32 PDSP_CONSTANT_TABLE_PROG_PTR_REG_0;
+    volatile Uint32 PDSP_CONSTANT_TABLE_PROG_PTR_REG_1;
+} CSL_PdspPdsp_regsRegs;
+
+/**************************************************************************\
+* Register Overlay Structure for PDSP_DEBUG_REGS
+\**************************************************************************/
+typedef struct  {
+    volatile Uint32 PDSP_IGP[32];
+    volatile Uint32 PDSP_ICTE[32];
+} CSL_PdspPdsp_debug_regsRegs;
+
+/**************************************************************************\
+* Register Overlay Structure
+\**************************************************************************/
+typedef struct  {
+    volatile Uint32 PDSP_CONTROL_REG;
+    volatile Uint32 PDSP_STATUS_REG;
+    volatile Uint32 PDSP_WAKEUP_ENABLE_REG;
+    volatile Uint32 PDSP_CYCLE_COUNT_REG;
+    volatile Uint32 PDSP_STALL_COUNT_REG;
+    volatile Uint8 RSVD0[12];
+    volatile Uint32 PDSP_CONSTANT_TABLE_BLOCK_INDEX_REG_0;
+    volatile Uint32 PDSP_CONSTANT_TABLE_BLOCK_INDEX_REG_1;
+    volatile Uint32 PDSP_CONSTANT_TABLE_PROG_PTR_REG_0;
+    volatile Uint32 PDSP_CONSTANT_TABLE_PROG_PTR_REG_1;
+    volatile Uint8 RSVD1[2000];
+    volatile Uint32 PDSP_IGP[32];
+    volatile Uint32 PDSP_ICTE[32];
+    volatile Uint8 RSVD2[1792];
+    volatile Uint32 PDSP_IRAM[2048];
+} CSL_PdspRegs;
+
+/**************************************************************************\
+* Field Definition Macros
+\**************************************************************************/
+
+/* PDSP_CONTROL_REG */
+
+#define CSL_PDSP_PDSP_CONTROL_REG_SOFT_RST_N_MASK (0x00000001u)
+#define CSL_PDSP_PDSP_CONTROL_REG_SOFT_RST_N_SHIFT (0x00000000u)
+#define CSL_PDSP_PDSP_CONTROL_REG_SOFT_RST_N_RESETVAL (0x00000001u)
+
+#define CSL_PDSP_PDSP_CONTROL_REG_PDSP_ENABLE_MASK (0x00000002u)
+#define CSL_PDSP_PDSP_CONTROL_REG_PDSP_ENABLE_SHIFT (0x00000001u)
+#define CSL_PDSP_PDSP_CONTROL_REG_PDSP_ENABLE_RESETVAL (0x00000000u)
+
+#define CSL_PDSP_PDSP_CONTROL_REG_PDSP_SLEEPING_MASK (0x00000004u)
+#define CSL_PDSP_PDSP_CONTROL_REG_PDSP_SLEEPING_SHIFT (0x00000002u)
+#define CSL_PDSP_PDSP_CONTROL_REG_PDSP_SLEEPING_RESETVAL (0x00000000u)
+
+#define CSL_PDSP_PDSP_CONTROL_REG_COUNTER_ENABLE_MASK (0x00000008u)
+#define CSL_PDSP_PDSP_CONTROL_REG_COUNTER_ENABLE_SHIFT (0x00000003u)
+#define CSL_PDSP_PDSP_CONTROL_REG_COUNTER_ENABLE_RESETVAL (0x00000000u)
+
+#define CSL_PDSP_PDSP_CONTROL_REG_RESTART_MASK (0x00000010u)
+#define CSL_PDSP_PDSP_CONTROL_REG_RESTART_SHIFT (0x00000004u)
+#define CSL_PDSP_PDSP_CONTROL_REG_RESTART_RESETVAL (0x00000000u)
+
+#define CSL_PDSP_PDSP_CONTROL_REG_SINGLE_STEP_MASK (0x00000100u)
+#define CSL_PDSP_PDSP_CONTROL_REG_SINGLE_STEP_SHIFT (0x00000008u)
+#define CSL_PDSP_PDSP_CONTROL_REG_SINGLE_STEP_RESETVAL (0x00000000u)
+
+#define CSL_PDSP_PDSP_CONTROL_REG_BIG_ENDIAN_MASK (0x00004000u)
+#define CSL_PDSP_PDSP_CONTROL_REG_BIG_ENDIAN_SHIFT (0x0000000Eu)
+#define CSL_PDSP_PDSP_CONTROL_REG_BIG_ENDIAN_RESETVAL (0x00000000u)
+
+#define CSL_PDSP_PDSP_CONTROL_REG_PDSP_STATE_MASK (0x00008000u)
+#define CSL_PDSP_PDSP_CONTROL_REG_PDSP_STATE_SHIFT (0x0000000Fu)
+#define CSL_PDSP_PDSP_CONTROL_REG_PDSP_STATE_RESETVAL (0x00000000u)
+
+#define CSL_PDSP_PDSP_CONTROL_REG_PCOUNTER_RST_VAL_MASK (0xFFFF0000u)
+#define CSL_PDSP_PDSP_CONTROL_REG_PCOUNTER_RST_VAL_SHIFT (0x00000010u)
+#define CSL_PDSP_PDSP_CONTROL_REG_PCOUNTER_RST_VAL_RESETVAL (0x00000000u)
+
+#define CSL_PDSP_PDSP_CONTROL_REG_RESETVAL (0x00000001u)
+
+/* PDSP_STATUS_REG */
+
+#define CSL_PDSP_PDSP_STATUS_REG_PCOUNTER_MASK (0x0000FFFFu)
+#define CSL_PDSP_PDSP_STATUS_REG_PCOUNTER_SHIFT (0x00000000u)
+#define CSL_PDSP_PDSP_STATUS_REG_PCOUNTER_RESETVAL (0x00000000u)
+
+#define CSL_PDSP_PDSP_STATUS_REG_RESETVAL (0x00000000u)
+
+/* PDSP_WAKEUP_ENABLE_REG */
+
+#define CSL_PDSP_PDSP_WAKEUP_ENABLE_REG_BITWISE_ENABLES_MASK (0xFFFFFFFFu)
+#define CSL_PDSP_PDSP_WAKEUP_ENABLE_REG_BITWISE_ENABLES_SHIFT (0x00000000u)
+#define CSL_PDSP_PDSP_WAKEUP_ENABLE_REG_BITWISE_ENABLES_RESETVAL (0x00000000u)
+
+#define CSL_PDSP_PDSP_WAKEUP_ENABLE_REG_RESETVAL (0x00000000u)
+
+/* PDSP_CYCLE_COUNT_REG */
+
+#define CSL_PDSP_PDSP_CYCLE_COUNT_REG_CYCLECOUNT_MASK (0xFFFFFFFFu)
+#define CSL_PDSP_PDSP_CYCLE_COUNT_REG_CYCLECOUNT_SHIFT (0x00000000u)
+#define CSL_PDSP_PDSP_CYCLE_COUNT_REG_CYCLECOUNT_RESETVAL (0x00000000u)
+
+#define CSL_PDSP_PDSP_CYCLE_COUNT_REG_RESETVAL (0x00000000u)
+
+/* PDSP_STALL_COUNT_REG */
+
+#define CSL_PDSP_PDSP_STALL_COUNT_REG_STALLCOUNT_MASK (0xFFFFFFFFu)
+#define CSL_PDSP_PDSP_STALL_COUNT_REG_STALLCOUNT_SHIFT (0x00000000u)
+#define CSL_PDSP_PDSP_STALL_COUNT_REG_STALLCOUNT_RESETVAL (0x00000000u)
+
+#define CSL_PDSP_PDSP_STALL_COUNT_REG_RESETVAL (0x00000000u)
+
+/* PDSP_CONSTANT_TABLE_BLOCK_INDEX_REG_0 */
+
+#define CSL_PDSP_PDSP_CONSTANT_TABLE_BLOCK_INDEX_REG_0_C24_BLK_INDEX_MASK (0x000000FFu)
+#define CSL_PDSP_PDSP_CONSTANT_TABLE_BLOCK_INDEX_REG_0_C24_BLK_INDEX_SHIFT (0x00000000u)
+#define CSL_PDSP_PDSP_CONSTANT_TABLE_BLOCK_INDEX_REG_0_C24_BLK_INDEX_RESETVAL (0x00000000u)
+
+#define CSL_PDSP_PDSP_CONSTANT_TABLE_BLOCK_INDEX_REG_0_C25_BLK_INDEX_MASK (0x00FF0000u)
+#define CSL_PDSP_PDSP_CONSTANT_TABLE_BLOCK_INDEX_REG_0_C25_BLK_INDEX_SHIFT (0x00000010u)
+#define CSL_PDSP_PDSP_CONSTANT_TABLE_BLOCK_INDEX_REG_0_C25_BLK_INDEX_RESETVAL (0x00000000u)
+
+#define CSL_PDSP_PDSP_CONSTANT_TABLE_BLOCK_INDEX_REG_0_RESETVAL (0x00000000u)
+
+/* PDSP_CONSTANT_TABLE_BLOCK_INDEX_REG_1 */
+
+#define CSL_PDSP_PDSP_CONSTANT_TABLE_BLOCK_INDEX_REG_1_C26_BLK_INDEX_MASK (0x000000FFu)
+#define CSL_PDSP_PDSP_CONSTANT_TABLE_BLOCK_INDEX_REG_1_C26_BLK_INDEX_SHIFT (0x00000000u)
+#define CSL_PDSP_PDSP_CONSTANT_TABLE_BLOCK_INDEX_REG_1_C26_BLK_INDEX_RESETVAL (0x00000000u)
+
+#define CSL_PDSP_PDSP_CONSTANT_TABLE_BLOCK_INDEX_REG_1_C27_BLK_INDEX_MASK (0x00FF0000u)
+#define CSL_PDSP_PDSP_CONSTANT_TABLE_BLOCK_INDEX_REG_1_C27_BLK_INDEX_SHIFT (0x00000010u)
+#define CSL_PDSP_PDSP_CONSTANT_TABLE_BLOCK_INDEX_REG_1_C27_BLK_INDEX_RESETVAL (0x00000000u)
+
+#define CSL_PDSP_PDSP_CONSTANT_TABLE_BLOCK_INDEX_REG_1_RESETVAL (0x00000000u)
+
+/* PDSP_CONSTANT_TABLE_PROG_PTR_REG_0 */
+
+#define CSL_PDSP_PDSP_CONSTANT_TABLE_PROG_PTR_REG_0_C28_POINTER_MASK (0x0000FFFFu)
+#define CSL_PDSP_PDSP_CONSTANT_TABLE_PROG_PTR_REG_0_C28_POINTER_SHIFT (0x00000000u)
+#define CSL_PDSP_PDSP_CONSTANT_TABLE_PROG_PTR_REG_0_C28_POINTER_RESETVAL (0x00000000u)
+
+#define CSL_PDSP_PDSP_CONSTANT_TABLE_PROG_PTR_REG_0_C29_POINTER_MASK (0xFFFF0000u)
+#define CSL_PDSP_PDSP_CONSTANT_TABLE_PROG_PTR_REG_0_C29_POINTER_SHIFT (0x00000010u)
+#define CSL_PDSP_PDSP_CONSTANT_TABLE_PROG_PTR_REG_0_C29_POINTER_RESETVAL (0x00000000u)
+
+#define CSL_PDSP_PDSP_CONSTANT_TABLE_PROG_PTR_REG_0_RESETVAL (0x00000000u)
+
+/* PDSP_CONSTANT_TABLE_PROG_PTR_REG_1 */
+
+#define CSL_PDSP_PDSP_CONSTANT_TABLE_PROG_PTR_REG_1_C30_POINTER_MASK (0x0000FFFFu)
+#define CSL_PDSP_PDSP_CONSTANT_TABLE_PROG_PTR_REG_1_C30_POINTER_SHIFT (0x00000000u)
+#define CSL_PDSP_PDSP_CONSTANT_TABLE_PROG_PTR_REG_1_C30_POINTER_RESETVAL (0x00000000u)
+
+#define CSL_PDSP_PDSP_CONSTANT_TABLE_PROG_PTR_REG_1_C31_POINTER_MASK (0xFFFF0000u)
+#define CSL_PDSP_PDSP_CONSTANT_TABLE_PROG_PTR_REG_1_C31_POINTER_SHIFT (0x00000010u)
+#define CSL_PDSP_PDSP_CONSTANT_TABLE_PROG_PTR_REG_1_C31_POINTER_RESETVAL (0x00000000u)
+
+#define CSL_PDSP_PDSP_CONSTANT_TABLE_PROG_PTR_REG_1_RESETVAL (0x00000000u)
+
+/* PDSP_IGP */
+
+#define CSL_PDSP_PDSP_IGP_REGN_MASK      (0xFFFFFFFFu)
+#define CSL_PDSP_PDSP_IGP_REGN_SHIFT     (0x00000000u)
+#define CSL_PDSP_PDSP_IGP_REGN_RESETVAL  (0x00000000u)
+
+#define CSL_PDSP_PDSP_IGP_RESETVAL       (0x00000000u)
+
+/* PDSP_ICTE */
+
+#define CSL_PDSP_PDSP_ICTE_CT_ENTRYN_MASK (0xFFFFFFFFu)
+#define CSL_PDSP_PDSP_ICTE_CT_ENTRYN_SHIFT (0x00000000u)
+#define CSL_PDSP_PDSP_ICTE_CT_ENTRYN_RESETVAL (0x00000000u)
+
+#define CSL_PDSP_PDSP_ICTE_RESETVAL      (0x00000000u)
+
+/* PDSP_IRAM */
+
+#define CSL_PDSP_PDSP_IRAM_PDSP_IRAM_MASK (0xFFFFFFFFu)
+#define CSL_PDSP_PDSP_IRAM_PDSP_IRAM_SHIFT (0x00000000u)
+#define CSL_PDSP_PDSP_IRAM_PDSP_IRAM_RESETVAL (0x00000000u)
+
+#define CSL_PDSP_PDSP_IRAM_RESETVAL      (0x00000000u)
+
+/**************************************************************************\
+* Register Overlay Structure
+\**************************************************************************/
+typedef struct  {
+    volatile Uint32 REVISION_REG;
+    volatile Uint32 PERF_CONTROL_REG;
+    volatile Uint32 EMULATION_CONTROL_REG;
+    volatile Uint32 PRIORITY_CONTROL_REG;
+    volatile Uint32 QM_BASE_ADDRESS_REG[4];
+} CSL_Cppidma_global_configRegs;
+
+/**************************************************************************\
+* Field Definition Macros
+\**************************************************************************/
+
+/* REVISION_REG */
+
+#define CSL_CPPIDMA_GLOBAL_CONFIG_REVISION_REG_REVMIN_MASK (0x0000003Fu)
+#define CSL_CPPIDMA_GLOBAL_CONFIG_REVISION_REG_REVMIN_SHIFT (0x00000000u)
+#define CSL_CPPIDMA_GLOBAL_CONFIG_REVISION_REG_REVMIN_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_GLOBAL_CONFIG_REVISION_REG_CUSTOM_MASK (0x000000C0u)
+#define CSL_CPPIDMA_GLOBAL_CONFIG_REVISION_REG_CUSTOM_SHIFT (0x00000006u)
+#define CSL_CPPIDMA_GLOBAL_CONFIG_REVISION_REG_CUSTOM_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_GLOBAL_CONFIG_REVISION_REG_REVMAJ_MASK (0x00000700u)
+#define CSL_CPPIDMA_GLOBAL_CONFIG_REVISION_REG_REVMAJ_SHIFT (0x00000008u)
+#define CSL_CPPIDMA_GLOBAL_CONFIG_REVISION_REG_REVMAJ_RESETVAL (0x00000001u)
+
+#define CSL_CPPIDMA_GLOBAL_CONFIG_REVISION_REG_REVRTL_MASK (0x0000F800u)
+#define CSL_CPPIDMA_GLOBAL_CONFIG_REVISION_REG_REVRTL_SHIFT (0x0000000Bu)
+#define CSL_CPPIDMA_GLOBAL_CONFIG_REVISION_REG_REVRTL_RESETVAL (0x00000019u)
+
+#define CSL_CPPIDMA_GLOBAL_CONFIG_REVISION_REG_FUNCTION_ID_MASK (0x0FFF0000u)
+#define CSL_CPPIDMA_GLOBAL_CONFIG_REVISION_REG_FUNCTION_ID_SHIFT (0x00000010u)
+#define CSL_CPPIDMA_GLOBAL_CONFIG_REVISION_REG_FUNCTION_ID_RESETVAL (0x00000E5Au)
+
+#define CSL_CPPIDMA_GLOBAL_CONFIG_REVISION_REG_BU_MASK (0x30000000u)
+#define CSL_CPPIDMA_GLOBAL_CONFIG_REVISION_REG_BU_SHIFT (0x0000001Cu)
+#define CSL_CPPIDMA_GLOBAL_CONFIG_REVISION_REG_BU_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_GLOBAL_CONFIG_REVISION_REG_RESERVED_MASK (0xC0000000u)
+#define CSL_CPPIDMA_GLOBAL_CONFIG_REVISION_REG_RESERVED_SHIFT (0x0000001Eu)
+#define CSL_CPPIDMA_GLOBAL_CONFIG_REVISION_REG_RESERVED_RESETVAL (0x00000001u)
+
+#define CSL_CPPIDMA_GLOBAL_CONFIG_REVISION_REG_RESETVAL (0x4E5AC900u)
+
+/* PERF_CONTROL_REG */
+
+#define CSL_CPPIDMA_GLOBAL_CONFIG_PERF_CONTROL_REG_TIMEOUT_CNT_MASK (0x0000FFFFu)
+#define CSL_CPPIDMA_GLOBAL_CONFIG_PERF_CONTROL_REG_TIMEOUT_CNT_SHIFT (0x00000000u)
+#define CSL_CPPIDMA_GLOBAL_CONFIG_PERF_CONTROL_REG_TIMEOUT_CNT_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_GLOBAL_CONFIG_PERF_CONTROL_REG_WARB_FIFO_DEPTH_MASK (0x003F0000u)
+#define CSL_CPPIDMA_GLOBAL_CONFIG_PERF_CONTROL_REG_WARB_FIFO_DEPTH_SHIFT (0x00000010u)
+#define CSL_CPPIDMA_GLOBAL_CONFIG_PERF_CONTROL_REG_WARB_FIFO_DEPTH_RESETVAL (0x00000020u)
+
+#define CSL_CPPIDMA_GLOBAL_CONFIG_PERF_CONTROL_REG_RESETVAL (0x00200000u)
+
+/* EMULATION_CONTROL_REG */
+
+#define CSL_CPPIDMA_GLOBAL_CONFIG_EMULATION_CONTROL_REG_FREE_MASK (0x00000001u)
+#define CSL_CPPIDMA_GLOBAL_CONFIG_EMULATION_CONTROL_REG_FREE_SHIFT (0x00000000u)
+#define CSL_CPPIDMA_GLOBAL_CONFIG_EMULATION_CONTROL_REG_FREE_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_GLOBAL_CONFIG_EMULATION_CONTROL_REG_SOFT_MASK (0x00000002u)
+#define CSL_CPPIDMA_GLOBAL_CONFIG_EMULATION_CONTROL_REG_SOFT_SHIFT (0x00000001u)
+#define CSL_CPPIDMA_GLOBAL_CONFIG_EMULATION_CONTROL_REG_SOFT_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_GLOBAL_CONFIG_EMULATION_CONTROL_REG_LOOPBACK_EN_MASK (0x80000000u)
+#define CSL_CPPIDMA_GLOBAL_CONFIG_EMULATION_CONTROL_REG_LOOPBACK_EN_SHIFT (0x0000001Fu)
+#define CSL_CPPIDMA_GLOBAL_CONFIG_EMULATION_CONTROL_REG_LOOPBACK_EN_RESETVAL (0x00000001u)
+
+#define CSL_CPPIDMA_GLOBAL_CONFIG_EMULATION_CONTROL_REG_RESETVAL (0x80000000u)
+
+/* PRIORITY_CONTROL_REG */
+
+#define CSL_CPPIDMA_GLOBAL_CONFIG_PRIORITY_CONTROL_REG_TX_PRIORITY_MASK (0x00000007u)
+#define CSL_CPPIDMA_GLOBAL_CONFIG_PRIORITY_CONTROL_REG_TX_PRIORITY_SHIFT (0x00000000u)
+#define CSL_CPPIDMA_GLOBAL_CONFIG_PRIORITY_CONTROL_REG_TX_PRIORITY_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_GLOBAL_CONFIG_PRIORITY_CONTROL_REG_RX_PRIORITY_MASK (0x00070000u)
+#define CSL_CPPIDMA_GLOBAL_CONFIG_PRIORITY_CONTROL_REG_RX_PRIORITY_SHIFT (0x00000010u)
+#define CSL_CPPIDMA_GLOBAL_CONFIG_PRIORITY_CONTROL_REG_RX_PRIORITY_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_GLOBAL_CONFIG_PRIORITY_CONTROL_REG_RESETVAL (0x00000000u)
+
+/* QM_BASE_ADDRESS_REG */
+
+#define CSL_CPPIDMA_GLOBAL_CONFIG_QM_BASE_ADDRESS_REG_QM_BASE_MASK (0xFFFFFFFFu)
+#define CSL_CPPIDMA_GLOBAL_CONFIG_QM_BASE_ADDRESS_REG_QM_BASE_SHIFT (0x00000000u)
+#define CSL_CPPIDMA_GLOBAL_CONFIG_QM_BASE_ADDRESS_REG_QM_BASE_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_GLOBAL_CONFIG_QM_BASE_ADDRESS_REG_RESETVAL (0x00000000u)
+
+/**************************************************************************\
+* Register Overlay Structure for TX_CHANNEL_GLOBAL_CONFIG
+\**************************************************************************/
+typedef struct  {
+    volatile Uint32 TX_CHANNEL_GLOBAL_CONFIG_REG_A;
+    volatile Uint32 TX_CHANNEL_GLOBAL_CONFIG_REG_B;
+    volatile Uint8 RSVD0[24];
+} CSL_Cppidma_tx_channel_configTx_channel_global_configRegs;
+
+/**************************************************************************\
+* Register Overlay Structure
+\**************************************************************************/
+typedef struct  {
+    CSL_Cppidma_tx_channel_configTx_channel_global_configRegs TX_CHANNEL_GLOBAL_CONFIG[129];
+} CSL_Cppidma_tx_channel_configRegs;
+
+/**************************************************************************\
+* Field Definition Macros
+\**************************************************************************/
+
+/* TX_CHANNEL_GLOBAL_CONFIG_REG_A */
+
+#define CSL_CPPIDMA_TX_CHANNEL_CONFIG_TX_CHANNEL_GLOBAL_CONFIG_REG_A_TX_PAUSE_MASK (0x20000000u)
+#define CSL_CPPIDMA_TX_CHANNEL_CONFIG_TX_CHANNEL_GLOBAL_CONFIG_REG_A_TX_PAUSE_SHIFT (0x0000001Du)
+#define CSL_CPPIDMA_TX_CHANNEL_CONFIG_TX_CHANNEL_GLOBAL_CONFIG_REG_A_TX_PAUSE_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_TX_CHANNEL_CONFIG_TX_CHANNEL_GLOBAL_CONFIG_REG_A_TX_TEARDOWN_MASK (0x40000000u)
+#define CSL_CPPIDMA_TX_CHANNEL_CONFIG_TX_CHANNEL_GLOBAL_CONFIG_REG_A_TX_TEARDOWN_SHIFT (0x0000001Eu)
+#define CSL_CPPIDMA_TX_CHANNEL_CONFIG_TX_CHANNEL_GLOBAL_CONFIG_REG_A_TX_TEARDOWN_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_TX_CHANNEL_CONFIG_TX_CHANNEL_GLOBAL_CONFIG_REG_A_TX_ENABLE_MASK (0x80000000u)
+#define CSL_CPPIDMA_TX_CHANNEL_CONFIG_TX_CHANNEL_GLOBAL_CONFIG_REG_A_TX_ENABLE_SHIFT (0x0000001Fu)
+#define CSL_CPPIDMA_TX_CHANNEL_CONFIG_TX_CHANNEL_GLOBAL_CONFIG_REG_A_TX_ENABLE_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_TX_CHANNEL_CONFIG_TX_CHANNEL_GLOBAL_CONFIG_REG_A_RESETVAL (0x00000000u)
+
+/* TX_CHANNEL_GLOBAL_CONFIG_REG_B */
+
+#define CSL_CPPIDMA_TX_CHANNEL_CONFIG_TX_CHANNEL_GLOBAL_CONFIG_REG_B_TX_AIF_MONO_MODE_MASK (0x01000000u)
+#define CSL_CPPIDMA_TX_CHANNEL_CONFIG_TX_CHANNEL_GLOBAL_CONFIG_REG_B_TX_AIF_MONO_MODE_SHIFT (0x00000018u)
+#define CSL_CPPIDMA_TX_CHANNEL_CONFIG_TX_CHANNEL_GLOBAL_CONFIG_REG_B_TX_AIF_MONO_MODE_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_TX_CHANNEL_CONFIG_TX_CHANNEL_GLOBAL_CONFIG_REG_B_TX_FILT_PSWORDS_MASK (0x20000000u)
+#define CSL_CPPIDMA_TX_CHANNEL_CONFIG_TX_CHANNEL_GLOBAL_CONFIG_REG_B_TX_FILT_PSWORDS_SHIFT (0x0000001Du)
+#define CSL_CPPIDMA_TX_CHANNEL_CONFIG_TX_CHANNEL_GLOBAL_CONFIG_REG_B_TX_FILT_PSWORDS_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_TX_CHANNEL_CONFIG_TX_CHANNEL_GLOBAL_CONFIG_REG_B_TX_FILT_EINFO_MASK (0x40000000u)
+#define CSL_CPPIDMA_TX_CHANNEL_CONFIG_TX_CHANNEL_GLOBAL_CONFIG_REG_B_TX_FILT_EINFO_SHIFT (0x0000001Eu)
+#define CSL_CPPIDMA_TX_CHANNEL_CONFIG_TX_CHANNEL_GLOBAL_CONFIG_REG_B_TX_FILT_EINFO_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_TX_CHANNEL_CONFIG_TX_CHANNEL_GLOBAL_CONFIG_REG_B_RESETVAL (0x00000000u)
+
+/**************************************************************************\
+* Register Overlay Structure for RX_CHANNEL_GLOBAL_CONFIG
+\**************************************************************************/
+typedef struct  {
+    volatile Uint32 RX_CHANNEL_GLOBAL_CONFIG_REG;
+    volatile Uint8 RSVD0[28];
+} CSL_Cppidma_rx_channel_configRx_channel_global_configRegs;
+
+/**************************************************************************\
+* Register Overlay Structure
+\**************************************************************************/
+typedef struct  {
+    CSL_Cppidma_rx_channel_configRx_channel_global_configRegs RX_CHANNEL_GLOBAL_CONFIG[129];
+} CSL_Cppidma_rx_channel_configRegs;
+
+/**************************************************************************\
+* Field Definition Macros
+\**************************************************************************/
+
+/* RX_CHANNEL_GLOBAL_CONFIG_REG */
+
+#define CSL_CPPIDMA_RX_CHANNEL_CONFIG_RX_CHANNEL_GLOBAL_CONFIG_REG_RX_PAUSE_MASK (0x20000000u)
+#define CSL_CPPIDMA_RX_CHANNEL_CONFIG_RX_CHANNEL_GLOBAL_CONFIG_REG_RX_PAUSE_SHIFT (0x0000001Du)
+#define CSL_CPPIDMA_RX_CHANNEL_CONFIG_RX_CHANNEL_GLOBAL_CONFIG_REG_RX_PAUSE_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_RX_CHANNEL_CONFIG_RX_CHANNEL_GLOBAL_CONFIG_REG_RX_TEARDOWN_MASK (0x40000000u)
+#define CSL_CPPIDMA_RX_CHANNEL_CONFIG_RX_CHANNEL_GLOBAL_CONFIG_REG_RX_TEARDOWN_SHIFT (0x0000001Eu)
+#define CSL_CPPIDMA_RX_CHANNEL_CONFIG_RX_CHANNEL_GLOBAL_CONFIG_REG_RX_TEARDOWN_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_RX_CHANNEL_CONFIG_RX_CHANNEL_GLOBAL_CONFIG_REG_RX_ENABLE_MASK (0x80000000u)
+#define CSL_CPPIDMA_RX_CHANNEL_CONFIG_RX_CHANNEL_GLOBAL_CONFIG_REG_RX_ENABLE_SHIFT (0x0000001Fu)
+#define CSL_CPPIDMA_RX_CHANNEL_CONFIG_RX_CHANNEL_GLOBAL_CONFIG_REG_RX_ENABLE_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_RX_CHANNEL_CONFIG_RX_CHANNEL_GLOBAL_CONFIG_REG_RESETVAL (0x00000000u)
+/**************************************************************************\
+* Register Overlay Structure
+\**************************************************************************/
+typedef struct  {
+    volatile Uint32 TX_CHANNEL_SCHEDULER_CONFIG_REG[129];
+} CSL_Cppidma_tx_scheduler_configRegs;
+
+/**************************************************************************\
+ * Field Definition Macros
+\**************************************************************************/
+
+/* TX_CHANNEL_SCHEDULER_CONFIG_REG */
+
+#define CSL_CPPIDMA_TX_SCHEDULER_CONFIG_TX_CHANNEL_SCHEDULER_CONFIG_REG_PRIORITY_MASK (0x00000003u)
+#define CSL_CPPIDMA_TX_SCHEDULER_CONFIG_TX_CHANNEL_SCHEDULER_CONFIG_REG_PRIORITY_SHIFT (0x00000000u)
+#define CSL_CPPIDMA_TX_SCHEDULER_CONFIG_TX_CHANNEL_SCHEDULER_CONFIG_REG_PRIORITY_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_TX_SCHEDULER_CONFIG_TX_CHANNEL_SCHEDULER_CONFIG_REG_RESETVAL (0x00000000u)
+
+/**************************************************************************\
+* Register Overlay Structure for RX_FLOW_CONFIG
+\**************************************************************************/
+typedef struct  {
+    volatile Uint32 RX_FLOW_CONFIG_REG_A;
+    volatile Uint32 RX_FLOW_CONFIG_REG_B;
+    volatile Uint32 RX_FLOW_CONFIG_REG_C;
+    volatile Uint32 RX_FLOW_CONFIG_REG_D;
+    volatile Uint32 RX_FLOW_CONFIG_REG_E;
+    volatile Uint32 RX_FLOW_CONFIG_REG_F;
+    volatile Uint32 RX_FLOW_CONFIG_REG_G;
+    volatile Uint32 RX_FLOW_CONFIG_REG_H;
+} CSL_Cppidma_rx_flow_configRx_flow_configRegs;
+
+/**************************************************************************\
+ * Register Overlay Structure
+\**************************************************************************/
+typedef struct  {
+    CSL_Cppidma_rx_flow_configRx_flow_configRegs RX_FLOW_CONFIG[129];
+} CSL_Cppidma_rx_flow_configRegs;
+
+/**************************************************************************\
+ * Field Definition Macros
+\**************************************************************************/
+
+/* RX_FLOW_CONFIG_REG_A */
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_DEST_QNUM_MASK (0x00000FFFu)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_DEST_QNUM_SHIFT (0x00000000u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_DEST_QNUM_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_DEST_QMGR_MASK (0x00003000u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_DEST_QMGR_SHIFT (0x0000000Cu)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_DEST_QMGR_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_SOP_OFFSET_MASK (0x01FF0000u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_SOP_OFFSET_SHIFT (0x00000010u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_SOP_OFFSET_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_PS_LOCATION_MASK (0x02000000u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_PS_LOCATION_SHIFT (0x00000019u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_PS_LOCATION_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_DESC_TYPE_MASK (0x0C000000u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_DESC_TYPE_SHIFT (0x0000001Au)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_DESC_TYPE_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_ERROR_HANDLING_MASK (0x10000000u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_ERROR_HANDLING_SHIFT (0x0000001Cu)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_ERROR_HANDLING_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_PSINFO_PRESENT_MASK (0x20000000u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_PSINFO_PRESENT_SHIFT (0x0000001Du)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_PSINFO_PRESENT_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_EINFO_PRESENT_MASK (0x40000000u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_EINFO_PRESENT_SHIFT (0x0000001Eu)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RX_EINFO_PRESENT_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_A_RESETVAL (0x00000000u)
+
+/* RX_FLOW_CONFIG_REG_B */
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_B_RX_DEST_TAG_LO_MASK (0x000000FFu)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_B_RX_DEST_TAG_LO_SHIFT (0x00000000u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_B_RX_DEST_TAG_LO_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_B_RX_DEST_TAG_HI_MASK (0x0000FF00u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_B_RX_DEST_TAG_HI_SHIFT (0x00000008u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_B_RX_DEST_TAG_HI_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_B_RX_SRC_TAG_LO_MASK (0x00FF0000u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_B_RX_SRC_TAG_LO_SHIFT (0x00000010u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_B_RX_SRC_TAG_LO_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_B_RX_SRC_TAG_HI_MASK (0xFF000000u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_B_RX_SRC_TAG_HI_SHIFT (0x00000018u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_B_RX_SRC_TAG_HI_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_B_RESETVAL (0x00000000u)
+
+/* RX_FLOW_CONFIG_REG_C */
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RX_SIZE_THRESH_EN_MASK (0x0000000Fu)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RX_SIZE_THRESH_EN_SHIFT (0x00000000u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RX_SIZE_THRESH_EN_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RX_DEST_TAG_LO_SEL_MASK (0x00070000u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RX_DEST_TAG_LO_SEL_SHIFT (0x00000010u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RX_DEST_TAG_LO_SEL_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RX_DEST_TAG_HI_SEL_MASK (0x00700000u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RX_DEST_TAG_HI_SEL_SHIFT (0x00000014u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RX_DEST_TAG_HI_SEL_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RX_SRC_TAG_LO_SEL_MASK (0x07000000u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RX_SRC_TAG_LO_SEL_SHIFT (0x00000018u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RX_SRC_TAG_LO_SEL_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RX_SRC_TAG_HI_SEL_MASK (0x70000000u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RX_SRC_TAG_HI_SEL_SHIFT (0x0000001Cu)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RX_SRC_TAG_HI_SEL_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_C_RESETVAL (0x00000000u)
+
+/* RX_FLOW_CONFIG_REG_D */
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_D_RX_FDQ1_QNUM_MASK (0x00000FFFu)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_D_RX_FDQ1_QNUM_SHIFT (0x00000000u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_D_RX_FDQ1_QNUM_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_D_RX_FDQ1_QMGR_MASK (0x00003000u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_D_RX_FDQ1_QMGR_SHIFT (0x0000000Cu)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_D_RX_FDQ1_QMGR_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_D_RX_FDQ0_SZ0_QNUM_MASK (0x0FFF0000u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_D_RX_FDQ0_SZ0_QNUM_SHIFT (0x00000010u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_D_RX_FDQ0_SZ0_QNUM_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_D_RX_FDQ0_SZ0_QMGR_MASK (0x30000000u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_D_RX_FDQ0_SZ0_QMGR_SHIFT (0x0000001Cu)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_D_RX_FDQ0_SZ0_QMGR_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_D_RESETVAL (0x00000000u)
+
+/* RX_FLOW_CONFIG_REG_E */
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_E_RX_FDQ3_QNUM_MASK (0x00000FFFu)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_E_RX_FDQ3_QNUM_SHIFT (0x00000000u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_E_RX_FDQ3_QNUM_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_E_RX_FDQ3_QMGR_MASK (0x00003000u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_E_RX_FDQ3_QMGR_SHIFT (0x0000000Cu)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_E_RX_FDQ3_QMGR_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_E_RX_FDQ2_QNUM_MASK (0x0FFF0000u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_E_RX_FDQ2_QNUM_SHIFT (0x00000010u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_E_RX_FDQ2_QNUM_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_E_RX_FDQ2_QMGR_MASK (0x30000000u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_E_RX_FDQ2_QMGR_SHIFT (0x0000001Cu)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_E_RX_FDQ2_QMGR_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_E_RESETVAL (0x00000000u)
+
+/* RX_FLOW_CONFIG_REG_F */
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_F_RX_SIZE_THRESH1_MASK (0x0000FFFFu)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_F_RX_SIZE_THRESH1_SHIFT (0x00000000u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_F_RX_SIZE_THRESH1_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_F_RX_SIZE_THRESH0_MASK (0xFFFF0000u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_F_RX_SIZE_THRESH0_SHIFT (0x00000010u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_F_RX_SIZE_THRESH0_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_F_RESETVAL (0x00000000u)
+
+/* RX_FLOW_CONFIG_REG_G */
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_G_RX_FDQ0_SZ1_QNUM_MASK (0x00000FFFu)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_G_RX_FDQ0_SZ1_QNUM_SHIFT (0x00000000u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_G_RX_FDQ0_SZ1_QNUM_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_G_RX_FDQ0_SZ1_QMGR_MASK (0x00003000u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_G_RX_FDQ0_SZ1_QMGR_SHIFT (0x0000000Cu)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_G_RX_FDQ0_SZ1_QMGR_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_G_RX_SIZE_THRESH2_MASK (0xFFFF0000u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_G_RX_SIZE_THRESH2_SHIFT (0x00000010u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_G_RX_SIZE_THRESH2_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_G_RESETVAL (0x00000000u)
+
+/* RX_FLOW_CONFIG_REG_H */
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ3_QNUM_MASK (0x00000FFFu)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ3_QNUM_SHIFT (0x00000000u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ3_QNUM_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ3_QMGR_MASK (0x00003000u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ3_QMGR_SHIFT (0x0000000Cu)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ3_QMGR_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ2_QNUM_MASK (0x0FFF0000u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ2_QNUM_SHIFT (0x00000010u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ2_QNUM_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ2_QMGR_MASK (0x30000000u)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ2_QMGR_SHIFT (0x0000001Cu)
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_H_RX_FDQ0_SZ2_QMGR_RESETVAL (0x00000000u)
+
+#define CSL_CPPIDMA_RX_FLOW_CONFIG_RX_FLOW_CONFIG_REG_H_RESETVAL (0x00000000u)
+    
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*TI_EM_HW_CSL_H_*/
diff --git a/platform/linux-keystone2/prebuilts/openem/include/linux/keystone2/ti_em_hw_functions.h b/platform/linux-keystone2/prebuilts/openem/include/linux/keystone2/ti_em_hw_functions.h
new file mode 100644
index 0000000..029ea17
--- /dev/null
+++ b/platform/linux-keystone2/prebuilts/openem/include/linux/keystone2/ti_em_hw_functions.h
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2012, Texas Instruments Incorporated - http://www.ti.com/
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *       * Redistributions of source code must retain the above copyright
+ *         notice, this list of conditions and the following disclaimer.
+ *       * Redistributions in binary form must reproduce the above copyright
+ *         notice, this list of conditions and the following disclaimer in the
+ *         documentation and/or other materials provided with the distribution.
+ *       * Neither the name of Texas Instruments Incorporated nor the
+ *         names of its contributors may be used to endorse or promote products
+ *         derived from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ *   WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY
+ *   DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ *   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *   ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/**
+ *   @file  ti_em_hw_functions.h
+ *
+ *   @brief
+ *      Machine platform functions
+ *
+ */
+
+#ifndef TI_EM_HW_FUNCTIONS_H_
+#define TI_EM_HW_FUNCTIONS_H_
+
+/* 
+ * This is for compatibility purpose, DNUM should be removed from OpenEM in the near
+ * future.
+ */
+#define DNUM         (ti_em_osal_get_core_idx())
+
+/* Temporary intrinsic definition, must be written in proper assembly per arch */
+#define _itoll(h, l) (((uint64_t)(h) << 32) | (uint64_t)(l))
+#define _loll(ll)    ((uint32_t)((ll) & 0xFFFFFFFFULL))
+#define _hill(ll)    ((uint32_t)(((ll) >> 32) & 0xFFFFFFFFULL))
+#define _mem8(i)     (*(uint64_t*)(i))
+
+#ifdef TI_EM_C66X
+#define TI_EM_HW_HAS_FAST_TSC
+#define TI_EM_HW_INIT_TSC()  0
+#define TI_EM_HW_GET_TSC()   ti_em_get_hw_c66x_tsc()
+
+static inline uint64_t ti_em_get_hw_c66x_tsc(void) {
+	unsigned int l, h;
+	__asm__ __volatile__  (" dint\n"
+			       " mvc .s2 TSCL,%0\n"
+			       " mvc .s2 TSCH,%1\n"
+			       " rint\n"
+			       : "=b"(l), "=b"(h));
+	return ((uint64_t) h << 32) | l;
+}
+
+static inline unsigned long _ffz(int val)
+{
+	__asm__ __volatile__ (" bitr  .M1  %0,%0\n"
+			      " nop\n"
+			      " lmbd  .L1  0,%0,%0\n"
+			      : "+a"(val));
+	return val;
+}
+
+#define	TI_EM_ARCH_MEM_BARRIER() __asm__ __volatile__ (" .word 0x10008000\n" \
+						       " .word 0x10008000\n")
+#endif /* TI_EM_C66X */
+
+#ifdef TI_EM_ARM_A15
+#include <ti_em_osal_cma.h>
+#define TI_EM_HW_HAS_FAST_TSC
+#define TI_EM_HW_INIT_TSC()  ti_em_osal_cma_enable_user_pmu()
+#define TI_EM_HW_GET_TSC()   ti_em_get_hw_arm_pmccntr()
+
+static inline uint64_t ti_em_get_hw_arm_pmccntr(void) {
+	unsigned int val;
+
+	/* read PMCCNTR */
+        asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val));
+        return (uint64_t) val;
+}
+
+static inline int _ffz(int val)
+{
+        int bit;
+	val = ~val;
+        __asm__ __volatile__ ("clz %0, %1" : "=r" (bit) : "r" (val & -val) : "cc");
+        return (31 - bit);
+}
+
+#define	TI_EM_ARCH_MEM_BARRIER() __asm__ __volatile__ ("dmb" : : : "memory")
+
+#endif /* TI_EM_ARM_A15 */
+#endif /* TI_EM_HW_FUNCTIONS_H_ */
diff --git a/platform/linux-keystone2/prebuilts/openem/include/linux/keystone2/ti_em_hw_mach.h b/platform/linux-keystone2/prebuilts/openem/include/linux/keystone2/ti_em_hw_mach.h
new file mode 100644
index 0000000..1d814f1
--- /dev/null
+++ b/platform/linux-keystone2/prebuilts/openem/include/linux/keystone2/ti_em_hw_mach.h
@@ -0,0 +1,166 @@
+/*
+ * Copyright (c) 2012, Texas Instruments Incorporated - http://www.ti.com/
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *       * Redistributions of source code must retain the above copyright
+ *         notice, this list of conditions and the following disclaimer.
+ *       * Redistributions in binary form must reproduce the above copyright
+ *         notice, this list of conditions and the following disclaimer in the
+ *         documentation and/or other materials provided with the distribution.
+ *       * Neither the name of Texas Instruments Incorporated nor the
+ *         names of its contributors may be used to endorse or promote products
+ *         derived from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ *   WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY
+ *   DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ *   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *   ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/**
+ *   @file  ti_em_hw_mach.h
+ *
+ *   @brief
+ *      Machine platform definitions
+ *
+ */
+
+#ifndef TI_EM_HW_MACH_H_
+#define TI_EM_HW_MACH_H_
+
+/*
+ * Architecture definitions
+ */
+#ifdef TI_EM_ARM_A15
+#define TI_EM_COHERENT_IO                            /* I/O are coherent */     
+#undef  TI_EM_USE_HUGETLB                            /* use hugeTLB feature (not yet available) */
+#define CACHE_L1D_LINESIZE                           (64)   /* size of L1D cache line for alignment purpose */
+#define CACHE_L2_LINESIZE                            (64)   /* size of L2 cache line for alignment purpose */
+#define QMSS_GENERAL_PURPOSE_USER_QUEUE_BASE         (4096) /* first queue available and not used by Linux */
+#endif /* TI_EM_ARM_A15 */
+
+#ifdef TI_EM_C66X
+#define CACHE_L1D_LINESIZE                           (64)   /* size of L1D cache line for alignment purpose */
+#define CACHE_L2_LINESIZE                            (128)  /* size of L2 cache line for alignment purpose */
+#define QMSS_GENERAL_PURPOSE_USER_QUEUE_BASE         (4096) /* first queue available and not used by Linux */
+#endif /* TI_EM_C66X */
+
+/* Linux MMU page size */
+#define PAGE_SIZE                                    (4096)
+
+/* This is the physical memory range that will be mapped as I/O in the virtual user address space*/
+#define TI_EM_IO_CFG_BASE                            (0x02000000)
+#define TI_EM_IO_CFG_SIZE                            (0x01000000)
+
+/*
+ * KeyStone 2 platform definitions
+ */
+#define CSL_QMSS_CFG_QM_1_CFG_REGS                   (0x02A02000)
+#define CSL_QMSS_CFG_QM_1_DESCRIPTOR_REGS            (0x02A02000 + 0x1000)
+#define CSL_QMSS_CFG_QM_2_CFG_REGS                   (0x02A04000)
+#define CSL_QMSS_CFG_QM_2_DESCRIPTOR_REGS            (0x02A04000 + 0x1000)
+#define CSL_QMSS_CFG_QM_1_STATUS_RAM                 (0x02A06000)
+#define CSL_QMSS_CFG_QM_2_STATUS_RAM                 (0x02A06400)
+#define CSL_QMSS_CFG_PKTDMA_1                        (0x02A08000)
+#define CSL_QMSS_CFG_PKTDMA_1_GLOBAL_CFG_REGS        (0x02A08000)
+#define CSL_QMSS_CFG_PKTDMA_1_TX_CFG_REGS            (0x02A08000 + 0x400)
+#define CSL_QMSS_CFG_PKTDMA_1_RX_CFG_REGS            (0x02A08000 + 0x800)
+#define CSL_QMSS_CFG_PKTDMA_1_TX_SCHEDULER_CFG_REGS  (0x02A08000 + 0xC00)
+#define CSL_QMSS_CFG_PKTDMA_1_RX_FLOW_CFG_REGS       (0x02A08000 + 0x1000)
+#define CSL_QMSS_CFG_PKTDMA_2                        (0x02A0A000)
+#define CSL_QMSS_CFG_PKTDMA_2_GLOBAL_CFG_REGS        (0x02A0A000)
+#define CSL_QMSS_CFG_PKTDMA_2_TX_CFG_REGS            (0x02A0A000 + 0x400)
+#define CSL_QMSS_CFG_PKTDMA_2_RX_CFG_REGS            (0x02A0A000 + 0x800)
+#define CSL_QMSS_CFG_PKTDMA_2_TX_SCHEDULER_CFG_REGS  (0x02A0A000 + 0xC00)
+#define CSL_QMSS_CFG_PKTDMA_2_RX_FLOW_CFG_REGS       (0x02A0A000 + 0x1000)
+#define CSL_QMSS_CFG_INTD_1_REGS                     (0x02A0C000)
+#define CSL_QMSS_CFG_INTD_2_REGS                     (0x02A0D000)
+#define CSL_QMSS_CFG_PDSP1_REGS                      (0x02A0F000)
+#define CSL_QMSS_CFG_PDSP2_REGS                      (0x02A0F000 + 0x100)
+#define CSL_QMSS_CFG_PDSP3_REGS                      (0x02A0F000 + 0x200)
+#define CSL_QMSS_CFG_PDSP4_REGS                      (0x02A0F000 + 0x300)
+#define CSL_QMSS_CFG_PDSP5_REGS                      (0x02A0F000 + 0x400)
+#define CSL_QMSS_CFG_PDSP6_REGS                      (0x02A0F000 + 0x500)
+#define CSL_QMSS_CFG_PDSP7_REGS                      (0x02A0F000 + 0x600)
+#define CSL_QMSS_CFG_PDSP8_REGS                      (0x02A0F000 + 0x700)
+#define CSL_QMSS_CFG_PDSP1_IRAM                      (0x02A10000)
+#define CSL_QMSS_CFG_PDSP2_IRAM                      (0x02A10000 + 0x1000)
+#define CSL_QMSS_CFG_PDSP3_IRAM                      (0x02A10000 + 0x2000)
+#define CSL_QMSS_CFG_PDSP4_IRAM                      (0x02A10000 + 0x3000)
+#define CSL_QMSS_CFG_PDSP5_IRAM                      (0x02A10000 + 0x4000)
+#define CSL_QMSS_CFG_PDSP6_IRAM                      (0x02A10000 + 0x5000)
+#define CSL_QMSS_CFG_PDSP7_IRAM                      (0x02A10000 + 0x6000)
+#define CSL_QMSS_CFG_PDSP8_IRAM                      (0x02A10000 + 0x7000)
+#define CSL_QMSS_CFG_PDSP1_SRAM                      (0x02A20000)
+#define CSL_QMSS_CFG_PDSP2_SRAM                      (0x02A20000 + 0x4000)
+#define CSL_QMSS_CFG_PDSP3_SRAM                      (0x02A20000 + 0x8000)
+#define CSL_QMSS_CFG_PDSP4_SRAM                      (0x02A20000 + 0xC000)
+#define CSL_QMSS_CFG_PDSP5_SRAM                      (0x02A20000 + 0x10000)
+#define CSL_QMSS_CFG_PDSP6_SRAM                      (0x02A20000 + 0x14000)
+#define CSL_QMSS_CFG_PDSP7_SRAM                      (0x02A20000 + 0x18000)
+#define CSL_QMSS_CFG_PDSP8_SRAM                      (0x02A20000 + 0x1C000)
+#define CSL_QMSS_CFG_QM_1_QUEUE_PEEK_REGS            (0x02A40000)
+#define CSL_QMSS_CFG_QM_2_QUEUE_PEEK_REGS            (0x02A60000)
+#define CSL_QMSS_CFG_QM_1_QUEUE_MANAGEMENT_REGS      (0x02A80000)
+#define CSL_QMSS_CFG_QM_2_QUEUE_MANAGEMENT_REGS      (0x02AA0000)
+#define CSL_QMSS_CFG_QM_1_QUEUE_PROXY_REGS           (0x02AC0000)
+#define CSL_QMSS_CFG_QM_2_QUEUE_PROXY_REGS           (0x02AE0000)
+#define CSL_QMSS_LINKING_RAM                         (0x02B00000)
+
+#define CSL_SRIO_CFG_PKTDMA_GLOBAL_CFG_REGS          (0x02900000 + 0x1000)
+#define CSL_SRIO_CFG_PKTDMA_TX_CFG_REGS              (0x02900000 + 0x1400)
+#define CSL_SRIO_CFG_PKTDMA_RX_CFG_REGS              (0x02900000 + 0x1800)
+#define CSL_SRIO_CFG_PKTDMA_TX_SCHEDULER_CFG_REGS    (0x02900000 + 0x1C00)
+#define CSL_SRIO_CFG_PKTDMA_RX_FLOW_CFG_REGS         (0x02900000 + 0x2000)
+
+#define CSL_NETCP_CFG_PKTDMA_GLOBAL_CFG_REGS         (0x02000000 + 0x4000)
+#define CSL_NETCP_CFG_PKTDMA_TX_CFG_REGS             (0x02000000 + 0x4400)
+#define CSL_NETCP_CFG_PKTDMA_RX_CFG_REGS             (0x02000000 + 0x4800)
+#define CSL_NETCP_CFG_PKTDMA_TX_SCHEDULER_CFG_REGS   (0x02000000 + 0x4C00)
+#define CSL_NETCP_CFG_PKTDMA_RX_FLOW_CFG_REGS        (0x02000000 + 0x5000)
+
+#define CSL_XGE_CFG_PKTDMA_GLOBAL_CFG_REGS           (0x02F00000 + 0xA1000)
+#define CSL_XGE_CFG_PKTDMA_TX_CFG_REGS               (0x02F00000 + 0xA1400)
+#define CSL_XGE_CFG_PKTDMA_RX_CFG_REGS               (0x02F00000 + 0xA1800)
+#define CSL_XGE_CFG_PKTDMA_TX_SCHEDULER_CFG_REGS     (0x02F00000 + 0xA1C00)
+#define CSL_XGE_CFG_PKTDMA_RX_FLOW_CFG_REGS          (0x02F00000 + 0xA2000)
+
+/*
+ * Our QMSS defines and aliases
+ */
+#define QMSS_OFFSET(i)                               ((CSL_QMSS_CFG_QM_2_CFG_REGS - CSL_QMSS_CFG_QM_1_CFG_REGS) * (i))
+
+#define TI_EM_QMSS_CFG_STARVATION_REGS(i)            (CSL_QMSS_CFG_QM_1_CFG_REGS + QMSS_OFFSET(i))
+#define TI_EM_QMSS_CFG_DESCRIPTOR_REGS(i)            (CSL_QMSS_CFG_QM_1_DESCRIPTOR_REGS + QMSS_OFFSET(i))
+#define TI_EM_QMSS_CFG_QUEUE_MGT_REGS                CSL_QMSS_CFG_QM_1_QUEUE_MANAGEMENT_REGS
+#define TI_EM_QMSS_CFG_DEQUEUE_REGS                  CSL_QMSS_CFG_QM_1_QUEUE_PROXY_REGS
+#define TI_EM_QMSS_CFG_QUEUE_PEEK_REGS               CSL_QMSS_CFG_QM_1_QUEUE_PEEK_REGS
+
+/*
+ * PDSP firmwares
+ */
+#define TI_EM_FIRMWARE_SCHED_PDSP1                   em_scheduler_router_fw_c663x
+#define TI_EM_FIRMWARE_SCHED_PDSP2                   em_scheduler_router_fw_c663x
+#define TI_EM_FIRMWARE_ROUTER_PDSP                   em_router_fw_c663x
+
+/*
+ * PDSP DRAM
+ *
+ * This is located at offset 0x20000 and 0x24000 of the QMSS data space
+ *
+ */
+#define TI_EM_PDSP_DRAM_SIZE                         (0x00004000)
+#define TI_EM_PDSP_DRAM(i)                           (0x23a20000 + (i) * TI_EM_PDSP_DRAM_SIZE)
+#define TI_EM_PDSPSH_DRAM                            (0x23a1c000)
+#define TI_EM_PDSP_DRAM_OFFSET                       (0x0)        /* no offset, CPU and QMSS/PDSP mapping is same */
+
+#endif /*TI_EM_HW_MACH_H_*/
diff --git a/platform/linux-keystone2/prebuilts/openem/include/linux/keystone2/ti_em_hw_qmss.h b/platform/linux-keystone2/prebuilts/openem/include/linux/keystone2/ti_em_hw_qmss.h
new file mode 100644
index 0000000..4bf64b7
--- /dev/null
+++ b/platform/linux-keystone2/prebuilts/openem/include/linux/keystone2/ti_em_hw_qmss.h
@@ -0,0 +1,633 @@
+/*
+ * Copyright (c) 2012, Texas Instruments Incorporated - http://www.ti.com/
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *       * Redistributions of source code must retain the above copyright
+ *         notice, this list of conditions and the following disclaimer.
+ *       * Redistributions in binary form must reproduce the above copyright
+ *         notice, this list of conditions and the following disclaimer in the
+ *         documentation and/or other materials provided with the distribution.
+ *       * Neither the name of Texas Instruments Incorporated nor the
+ *         names of its contributors may be used to endorse or promote products
+ *         derived from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ *   WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY
+ *   DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ *   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *   ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/**
+ *   @file  ti_em_hw_qmss.h
+ *
+ *   @brief   
+ *      This is the Queue Manager module include file.
+ *
+ *  \par
+ *  ============================================================================
+ *  @n   (C) Copyright 2009, 2013 Texas Instruments, Inc.
+ *  @n   Use of this software is controlled by the terms and conditions found 
+ *  @n   in the license agreement under which this software has been supplied.
+ *  ============================================================================ 
+ *  \par
+ */
+
+#ifndef TI_EM_HW_QMSS_H_
+#define TI_EM_HW_QMSS_H_
+
+/** 
+ * @brief Queue start number and maximum number of each type of queue supported.
+ */
+#define QMSS_LOW_PRIORITY_QUEUE_BASE                0
+#define QMSS_MAX_LOW_PRIORITY_QUEUE               512
+
+#define QMSS_AIF_QUEUE_BASE                       512
+#define QMSS_MAX_AIF_QUEUE                        128
+#define QMSS_PASS_QUEUE_BASE                      640
+#define QMSS_MAX_PASS_QUEUE                         9
+
+/* Broadcast to CPINTC 0/1/2 */
+#define QMSS_INTC_SET1_QUEUE_BASE                 652
+#define QMSS_MAX_INTC_SET1_QUEUE                    6
+/* For backward compatibility */
+#define QMSS_INTC_QUEUE_BASE     QMSS_INTC_SET1_QUEUE_BASE
+#define QMSS_MAX_INTC_QUEUE      QMSS_MAX_INTC_SET1_QUEUE
+
+/* Broadcast to CPINTC 0/1/2, GIC, EDMA 4 and Hyperlink */
+#define QMSS_INTC_SET2_QUEUE_BASE                 658
+#define QMSS_MAX_INTC_SET2_QUEUE                    8
+/* Broadcast to CPINTC 0/1/2 */
+#define QMSS_INTC_SET3_QUEUE_BASE                 666
+#define QMSS_MAX_INTC_SET3_QUEUE                    6
+
+#define QMSS_SRIO_QUEUE_BASE                      672
+#define QMSS_MAX_SRIO_QUEUE                        16
+#define QMSS_FFTC_A_QUEUE_BASE                    688
+#define QMSS_MAX_FFTC_A_QUEUE                       4
+#define QMSS_FFTC_B_QUEUE_BASE                    692
+#define QMSS_MAX_FFTC_B_QUEUE                       4
+
+#define QMSS_HIGH_PRIORITY_QUEUE_BASE             704
+#define QMSS_MAX_HIGH_PRIORITY_QUEUE               32
+#define QMSS_STARVATION_COUNTER_QUEUE_BASE        736
+#define QMSS_MAX_STARVATION_COUNTER_QUEUE          64
+
+#define QMSS_QM1_INFRASTRUCTURE_DMA_QUEUE_BASE    800
+#define QMSS_MAX_QM1_INFRASTRUCTURE_DMA_QUEUE      32
+/* For backward compatibility */
+#define QMSS_INFRASTRUCTURE_QUEUE_BASE   QMSS_QM1_INFRASTRUCTURE_DMA_QUEUE_BASE
+#define QMSS_MAX_INFRASTRUCTURE_QUEUE    QMSS_MAX_QM1_INFRASTRUCTURE_DMA_QUEUE
+
+#define QMSS_TRAFFIC_SHAPING_QUEUE_BASE           832
+#define QMSS_MAX_TRAFFIC_SHAPING_QUEUE             32
+
+#define QMSS_BCP_QUEUE_BASE                       864
+#define QMSS_MAX_BCP_QUEUE                          8
+#define QMSS_FFTC_C_QUEUE_BASE                    872
+#define QMSS_MAX_FFTC_C_QUEUE                       4
+#define QMSS_FFTC_D_QUEUE_BASE                    876
+#define QMSS_MAX_FFTC_D_QUEUE                       4
+#define QMSS_FFTC_E_QUEUE_BASE                    880
+#define QMSS_MAX_FFTC_E_QUEUE                       4
+#define QMSS_FFTC_F_QUEUE_BASE                    884
+#define QMSS_MAX_FFTC_F_QUEUE                       4
+
+#define QMSS_GENERAL_PURPOSE_QUEUE_BASE           896
+#define QMSS_MAX_GENERAL_PURPOSE_QUEUE           7296
+
+#define QMSS_QM2_LOW_PRIORITY_QUEUE_BASE         8192
+#define QMSS_MAX_QM2_LOW_PRIORITY_QUEUE           512
+
+#define QMSS_GIC400_QUEUE_BASE                   8704
+#define QMSS_MAX_GIC400_QUEUE                      32
+#define QMSS_EDMA4_QUEUE_BASE                    8736
+#define QMSS_MAX_EDMA4_QUEUE                        8
+#define QMSS_BCAST_HYPERLINK_0_1_QUEUE_BASE      8744
+#define QMSS_MAX_BCAST_HYPERLINK_0_1_QUEUE          8
+#define QMSS_XGE_QUEUE_BASE                      8752
+#define QMSS_MAX_XGE_QUEUE                          8
+#define QMSS_DXB_QUEUE_BASE                      8836
+#define QMSS_DXB_XGE_QUEUE                          8
+
+#define QMSS_HYPERLINK_0_QUEUE_BASE              8760
+#define QMSS_MAX_HYPERLINK_0_QUEUE                 16
+
+/* Broadcast to CPINTC 0/1/2 */                  
+#define QMSS_INTC_SET4_QUEUE_BASE                8844
+#define QMSS_MAX_INTC_SET4_QUEUE                   20
+                                                 
+#define QMSS_HYPERLINK_1_QUEUE_BASE              8864
+#define QMSS_MAX_HYPERLINK_1_QUEUE                 16
+
+#define QMSS_QM2_INFRASTRUCTURE_DMA_QUEUE_BASE   8992
+#define QMSS_MAX_QM2_INFRASTRUCTURE_DMA_QUEUE      32
+
+#define QMSS_QM2_GENERAL_PURPOSE_QUEUE_BASE      9024
+#define QMSS_MAX_QM2_GENERAL_PURPOSE_QUEUE       7360
+
+/** 
+ * @brief Queue Type. Specifies different queue classifications
+ */
+typedef enum
+{
+    /** Low priority queue */
+    Qmss_QueueType_LOW_PRIORITY_QUEUE = 0,
+    /** AIF queue */
+    Qmss_QueueType_AIF_QUEUE,
+    /** PASS queue */
+    Qmss_QueueType_PASS_QUEUE,
+    /** INTC pending queue */
+    Qmss_QueueType_INTC_QUEUE,
+    /** SRIO queue */
+    Qmss_QueueType_SRIO_QUEUE,
+    /** FFTC queue A */
+    Qmss_QueueType_FFTC_A_QUEUE,
+    /** FFTC queue B */
+    Qmss_QueueType_FFTC_B_QUEUE,
+    /** FFTC queue C */
+    Qmss_QueueType_FFTC_C_QUEUE,
+    /** FFTC queue D */
+    Qmss_QueueType_FFTC_D_QUEUE,
+    /** FFTC queue E */
+    Qmss_QueueType_FFTC_E_QUEUE,
+    /** FFTC queue F */
+    Qmss_QueueType_FFTC_F_QUEUE,
+    /** BCP queue */
+    Qmss_QueueType_BCP_QUEUE,
+    /** High priority queue */
+    Qmss_QueueType_HIGH_PRIORITY_QUEUE,
+    /** starvation counter queue */
+    Qmss_QueueType_STARVATION_COUNTER_QUEUE,
+    /** Infrastructure queue first QM */
+    Qmss_QueueType_INFRASTRUCTURE_QUEUE,
+    /** Infrastructure queue second QM */
+    Qmss_QueueType_QM2_INFRASTRUCTURE_QUEUE,
+    /** Traffic shaping queue */
+    Qmss_QueueType_TRAFFIC_SHAPING_QUEUE,
+    /** GIC400 queue */
+    Qmss_QueueType_GIC400_QUEUE,
+    /** EDMA 4 queue */
+    Qmss_QueueType_EDMA_4_QUEUE,
+    /** Broadcast to Hyperlink 0 and 1 queue */
+    Qmss_QueueType_HLINK_BROADCAST_QUEUE,
+    /** Hyperlink 0 queue */
+    Qmss_QueueType_HLINK_0_QUEUE,
+    /** Hyperlink 1 queue */
+    Qmss_QueueType_HLINK_1_QUEUE,
+    /** XGE (10 gigabit ethernet) queue */
+    Qmss_QueueType_XGE_QUEUE,
+    /** DXB queue */
+    Qmss_QueueType_DXB_QUEUE,
+    /** General purpose queue -- MUST be last */
+    Qmss_QueueType_GENERAL_PURPOSE_QUEUE
+}Qmss_QueueType;
+
+/**
+@}
+*/
+/** QMSS maximum number of memory regions */
+#define QMSS_MAX_MEM_REGIONS                        64
+/** QMSS maximum number of PDSPS */
+#define QMSS_MAX_PDSP                               8
+/** QMSS maximum number of INTDs */
+#define QMSS_MAX_INTD                               2
+/** QMSS maximum number of queue groups (QMGRs that run independently) */
+#define QMSS_MAX_QMGR_GROUPS                        2
+/** QMSS maximum number of queue types (per group) */
+#define QMSS_MAX_QUEUE_TYPES                        30
+/** QMSS maximum number of queues */
+#define QMSS_MAX_QUEUES                             16384
+
+/** 
+ * @brief QMSS RM Handle
+ */
+typedef void *  Qmss_RmHnd;
+
+/** 
+ * @brief QMSS start configuration structure
+ */
+typedef struct
+{
+    /** Provide a handle to the Resource Manager instance */
+    Qmss_RmHnd rmHandle;
+} Qmss_StartCfg;
+
+/** 
+ * @brief Queue definition
+ */
+typedef struct
+{
+    /** Queue manager number */
+    int32_t qMgr;        
+    /** Queue number within Queue Manager */
+    int32_t qNum;
+}Qmss_Queue;
+
+/** 
+ * @brief Queue definition
+ */
+typedef struct
+{
+    /** Queue type */
+    Qmss_QueueType queueType;
+    /** Queue manager number */
+    int32_t        startIndex;        
+    /** Queue number within Queue Manager */
+    int32_t        maxNum;
+}Qmss_QueueNumRange;
+
+/** 
+ * @brief QMSS Global register definition for registers that replicate
+ * per QM group
+ */
+typedef struct 
+{
+    /** QM Global Config registers */
+    CSL_Qm_configRegs                       *qmConfigReg;
+    /** QM Descriptor Config registers */
+    CSL_Qm_descriptor_region_configRegs     *qmDescReg;
+    /** QM queue Management registers, accessed via CFG port */
+    CSL_Qm_queue_managementRegs             *qmQueMgmtReg;
+    /** QM queue Management Proxy registers, accessed via CFG port */
+    CSL_Qm_queue_managementRegs             *qmQueMgmtProxyReg;
+    /** QM queue status registers */
+    CSL_Qm_queue_status_configRegs          *qmQueStatReg;
+    /** QM Status RAM */
+    CSL_Qm_Queue_Status                     *qmStatusRAM;
+    /** QM queue Management registers, accessed via DMA port */
+    CSL_Qm_queue_managementRegs             *qmQueMgmtDataReg;
+    /** QM queue Management Proxy registers, accessed via DMA port */
+    CSL_Qm_queue_managementRegs             *qmQueMgmtProxyDataReg;
+} Qmss_GlobalConfigGroupRegs;
+
+/** 
+ * @brief QMSS Global register definition for registers that do not replicate
+ * per QM group
+ */
+typedef struct 
+{
+    /** QM INTD registers */
+    CSL_Qm_intdRegs                         *qmQueIntdReg[QMSS_MAX_INTD];
+    /** QM PDSP command register */
+    volatile uint32_t                       *qmPdspCmdReg[QMSS_MAX_PDSP];
+    /** QM PDSP control register */
+    CSL_PdspRegs                            *qmPdspCtrlReg[QMSS_MAX_PDSP];
+    /** QM PDSP IRAM register */
+    volatile uint32_t                       *qmPdspIRamReg[QMSS_MAX_PDSP];
+    /** QM Linking RAM register */
+    volatile uint32_t                       *qmLinkingRAMReg;
+    /** QM peripheral base address used to calculate internal addresses */
+    void                                    *qmBaseAddr;
+} Qmss_GlobalConfigRegs;
+
+/** 
+ * @brief QMSS Global configuration structure definition
+ */
+typedef struct
+{
+    /** Maximum number of queue manager groups */
+    uint32_t                                maxQueMgrGroups;
+    /** Maximum number of queue Managers */
+    uint32_t                                maxQueMgr;
+    /** Maximum number of queues */
+    uint32_t                                maxQue;
+    /** Maximum number of memory regions */
+    uint32_t                                maxMemReg;
+    /** Maximum number of PDSPs */
+    uint32_t                                maxPDSP;
+    /** Requires ordered memory regions? */
+    int                                     orderedMemReg;
+    /** Queue start index and maximum number of queues of each queue type for each queue group */
+    Qmss_QueueNumRange                      maxQueueNum[QMSS_MAX_QMGR_GROUPS][QMSS_MAX_QUEUE_TYPES];
+    /* Register definitions for each QM group */
+    Qmss_GlobalConfigGroupRegs              groupRegs[QMSS_MAX_QMGR_GROUPS];
+    /* Register definitions for whole SS */
+    Qmss_GlobalConfigRegs                   regs;
+    /** QM stores the Resource Manager handle for internal use */
+    Qmss_RmHnd                              qmRmHandle;
+} Qmss_GlobalConfigParams;
+
+/**
+@}
+*/
+/** Internal Linking RAM default size */
+#define QMSS_LINKING_RAM_REGION_0_DEFAULT_SIZE      0x7FFF
+
+/** Used as input parameter when queue number is 
+ * not known and not specified */
+#define QMSS_PARAM_NOT_SPECIFIED                    -1
+
+/** Used to indicate that QMSS HW Initialization is complete */
+#define QMSS_HW_INIT_COMPLETE                       0xABCD
+
+/** QMSS Low level Driver return and Error Codes */
+/** QMSS successful return code */
+#define QMSS_SOK                                    0
+/** QMSS Error Base */       
+#define QMSS_LLD_EBASE                              (-128)
+/** QMSS LLD invalid parameter */
+#define QMSS_INVALID_PARAM                          QMSS_LLD_EBASE-1
+/** QMSS LLD not initialized */
+#define QMSS_NOT_INITIALIZED                        QMSS_LLD_EBASE-2
+/** QMSS LLD queue open error */
+#define QMSS_QUEUE_OPEN_ERROR                       QMSS_LLD_EBASE-3
+/** QMSS memory region not initialized */
+#define QMSS_MEMREGION_NOT_INITIALIZED              QMSS_LLD_EBASE-4
+/** QMSS memory region already initialized */
+#define QMSS_MEMREGION_ALREADY_INITIALIZED          QMSS_LLD_EBASE-5
+/** QMSS memory region invalid parameter */
+#define QMSS_MEMREGION_INVALID_PARAM                QMSS_LLD_EBASE-6
+/** QMSS maximum number of allowed descriptor are already configured */
+#define QMSS_MAX_DESCRIPTORS_CONFIGURED             QMSS_LLD_EBASE-7
+/** QMSS Specified memory region index is invalid or no memory regions are available */
+#define QMSS_MEMREGION_INVALID_INDEX                QMSS_LLD_EBASE-8
+/** QMSS memory region overlap */
+#define QMSS_MEMREGION_OVERLAP                      QMSS_LLD_EBASE-9
+/** QMSS memory region not in acscending order */
+#define QMSS_MEMREGION_ORDERING                     QMSS_LLD_EBASE-10
+/** QMSS PDSP firmware download failure */
+#define QMSS_FIRMWARE_DOWNLOAD_FAILED               QMSS_LLD_EBASE-11
+/** QMSS resource initialization permission denied */
+#define QMSS_RESOURCE_INIT_DENIED                   QMSS_LLD_EBASE-12
+/** QMSS resource usage permission denied */
+#define QMSS_RESOURCE_USE_DENIED                    QMSS_LLD_EBASE-13
+/** QMSS memory region initialization permission denied */
+#define QMSS_RESOURCE_MEM_REGION_INIT_DENIED        QMSS_LLD_EBASE-14
+/** QMSS memory region usage permission denied */
+#define QMSS_RESOURCE_MEM_REGION_USE_DENIED         QMSS_LLD_EBASE-15
+/** QMSS general linking RAM initialization permission denied */
+#define QMSS_RESOURCE_LINKING_RAM_INIT_DENIED       QMSS_LLD_EBASE-16
+/** QMSS firmware revision difference */
+#define QMSS_FIRMWARE_REVISION_DIFFERENCE           QMSS_LLD_EBASE-17
+/** QMSS firmware invalid garbage return queue */
+#define QMSS_INVALID_SRIO_GARBAGE_QUEUE             QMSS_LLD_EBASE-18
+/** QMSS Bad Queue Number Configuration Table */
+#define QMSS_INVALID_QUEUE_NUMBER_TAB               QMSS_LLD_EBASE-19
+
+/** QMSS maximum number of memory regions */
+#define QMSS_MAX_MEM_REGIONS                        64
+/** QMSS maximum number of PDSPS */
+#define QMSS_MAX_PDSP                               8
+/** QMSS maximum number of INTDs */
+#define QMSS_MAX_INTD                               2
+/** QMSS maximum number of queue groups (QMGRs that run independently) */
+#define QMSS_MAX_QMGR_GROUPS                        2
+/** QMSS maximum number of queue types (per group) */
+#define QMSS_MAX_QUEUE_TYPES                        30
+/** QMSS maximum number of queues */
+#define QMSS_MAX_QUEUES                             16384
+
+/** Macro to get the descriptor pointer if the popped descriptor contains the descriptor size. 
+ * If Qmss_queuePushDescSize() API is used to push a descriptor onto a queue, the descriptor when 
+ * popped will have the descriptor size information in the lower 4 bits. This macro is provided to 
+ * clear out the size information */
+#define QMSS_DESC_PTR(desc)                         ((uint32_t)desc & 0xFFFFFFF0)
+
+/** Macro to get the descriptor size if the popped descriptor contains the descriptor size. 
+ * If Qmss_queuePushDescSize() API is used to push a descriptor onto a queue, the descriptor when 
+ * popped will have the descriptor size information in the lower 4 bits. This macro is provided to 
+ * obtain the size information. Minimum size is 16 bytes. Maximum size is 256 bytes */
+#define QMSS_DESC_SIZE(desc)                        ((((uint32_t)desc & 0x0000000F) + 1) << 4) 
+
+/** Macro to extract the queue manager group from the queue handle */
+#define QMSS_QUEUE_GROUP(hndl)                      ((uint32_t)(hndl) >> 13)
+#define QMSS_QUEUE_NUMBER(hndl)                     ((uint32_t)(hndl) & 0x1FFF)
+
+/** 
+ * @brief location where the packet is queued
+ */
+typedef enum
+{
+    /** Queue packet to the tail of the queue. Default behavior. */
+    Qmss_Location_TAIL = 0,
+    /** Queue packet to the head of the queue. */
+    Qmss_Location_HEAD 
+}Qmss_Location;
+
+/** 
+ * @brief Descriptor resource management
+ */
+typedef enum
+{
+    /** LLD doesnot manage the descriptors. The caller should manage them. */
+    Qmss_ManageDesc_UNMANAGED_DESCRIPTOR = 0,
+    /** LLD manages the descriptors. The descriptors are reclaimed using 
+     * the QMSS_initDescriptor() or CPPI_initDescriptor() APIs
+     * */
+    Qmss_ManageDesc_MANAGE_DESCRIPTOR 
+}Qmss_ManageDesc;
+
+/** 
+ * @brief Queue Manager's memory regions
+ */
+typedef enum
+{
+    /** Memory region not specified. LLD allocates the next available memory region */
+    Qmss_MemRegion_MEMORY_REGION_NOT_SPECIFIED = -1,
+    /** Configure memory region0. */
+    Qmss_MemRegion_MEMORY_REGION0 = 0,
+    /** Configure memory region 1. */
+    Qmss_MemRegion_MEMORY_REGION1,
+    /** Configure memory region 2. */
+    Qmss_MemRegion_MEMORY_REGION2,
+    /** Configure memory region 3. */
+    Qmss_MemRegion_MEMORY_REGION3,
+    /** Configure memory region 4. */
+    Qmss_MemRegion_MEMORY_REGION4,
+    /** Configure memory region 5. */
+    Qmss_MemRegion_MEMORY_REGION5,
+    /** Configure memory region 6. */
+    Qmss_MemRegion_MEMORY_REGION6,
+    /** Configure memory region 7. */
+    Qmss_MemRegion_MEMORY_REGION7,
+    /** Configure memory region 8. */
+    Qmss_MemRegion_MEMORY_REGION8,
+    /** Configure memory region 9. */
+    Qmss_MemRegion_MEMORY_REGION9,
+    /** Configure memory region 10. */
+    Qmss_MemRegion_MEMORY_REGION10,
+    /** Configure memory region 11. */
+    Qmss_MemRegion_MEMORY_REGION11,
+    /** Configure memory region 12. */
+    Qmss_MemRegion_MEMORY_REGION12,
+    /** Configure memory region 13. */
+    Qmss_MemRegion_MEMORY_REGION13,
+    /** Configure memory region 14. */
+    Qmss_MemRegion_MEMORY_REGION14,
+    /** Configure memory region 15. */
+    Qmss_MemRegion_MEMORY_REGION15,
+    /** Configure memory region 16. */
+    Qmss_MemRegion_MEMORY_REGION16,
+    /** Configure memory region 17. */
+    Qmss_MemRegion_MEMORY_REGION17,
+    /** Configure memory region 18. */
+    Qmss_MemRegion_MEMORY_REGION18,
+    /** Configure memory region 19. */
+    Qmss_MemRegion_MEMORY_REGION19,
+    /** Configure memory region 20. */
+    Qmss_MemRegion_MEMORY_REGION20,
+    /** Configure memory region 21. */
+    Qmss_MemRegion_MEMORY_REGION21,
+    /** Configure memory region 22. */
+    Qmss_MemRegion_MEMORY_REGION22,
+    /** Configure memory region 23. */
+    Qmss_MemRegion_MEMORY_REGION23,
+    /** Configure memory region 24. */
+    Qmss_MemRegion_MEMORY_REGION24,
+    /** Configure memory region 25. */
+    Qmss_MemRegion_MEMORY_REGION25,
+    /** Configure memory region 26. */
+    Qmss_MemRegion_MEMORY_REGION26,
+    /** Configure memory region 27. */
+    Qmss_MemRegion_MEMORY_REGION27,
+    /** Configure memory region 28. */
+    Qmss_MemRegion_MEMORY_REGION28,
+    /** Configure memory region 29. */
+    Qmss_MemRegion_MEMORY_REGION29,
+    /** Configure memory region 30. */
+    Qmss_MemRegion_MEMORY_REGION30,
+    /** Configure memory region 31. */
+    Qmss_MemRegion_MEMORY_REGION31,
+    /** Configure memory region 32. */
+    Qmss_MemRegion_MEMORY_REGION32,
+    /** Configure memory region 33. */
+    Qmss_MemRegion_MEMORY_REGION33,
+    /** Configure memory region 34. */
+    Qmss_MemRegion_MEMORY_REGION34,
+    /** Configure memory region 35. */
+    Qmss_MemRegion_MEMORY_REGION35,
+    /** Configure memory region 36. */
+    Qmss_MemRegion_MEMORY_REGION36,
+    /** Configure memory region 37. */
+    Qmss_MemRegion_MEMORY_REGION37,
+    /** Configure memory region 38. */
+    Qmss_MemRegion_MEMORY_REGION38,
+    /** Configure memory region 39. */
+    Qmss_MemRegion_MEMORY_REGION39,
+    /** Configure memory region 40. */
+    Qmss_MemRegion_MEMORY_REGION40,
+    /** Configure memory region 41. */
+    Qmss_MemRegion_MEMORY_REGION41,
+    /** Configure memory region 42. */
+    Qmss_MemRegion_MEMORY_REGION42,
+    /** Configure memory region 43. */
+    Qmss_MemRegion_MEMORY_REGION43,
+    /** Configure memory region 44. */
+    Qmss_MemRegion_MEMORY_REGION44,
+    /** Configure memory region 45. */
+    Qmss_MemRegion_MEMORY_REGION45,
+    /** Configure memory region 46. */
+    Qmss_MemRegion_MEMORY_REGION46,
+    /** Configure memory region 47. */
+    Qmss_MemRegion_MEMORY_REGION47,
+    /** Configure memory region 48. */
+    Qmss_MemRegion_MEMORY_REGION48,
+    /** Configure memory region 49. */
+    Qmss_MemRegion_MEMORY_REGION49,
+    /** Configure memory region 50. */
+    Qmss_MemRegion_MEMORY_REGION50,
+    /** Configure memory region 51. */
+    Qmss_MemRegion_MEMORY_REGION51,
+    /** Configure memory region 52. */
+    Qmss_MemRegion_MEMORY_REGION52,
+    /** Configure memory region 53. */
+    Qmss_MemRegion_MEMORY_REGION53,
+    /** Configure memory region 54. */
+    Qmss_MemRegion_MEMORY_REGION54,
+    /** Configure memory region 55. */
+    Qmss_MemRegion_MEMORY_REGION55,
+    /** Configure memory region 56. */
+    Qmss_MemRegion_MEMORY_REGION56,
+    /** Configure memory region 57. */
+    Qmss_MemRegion_MEMORY_REGION57,
+    /** Configure memory region 58. */
+    Qmss_MemRegion_MEMORY_REGION58,
+    /** Configure memory region 59. */
+    Qmss_MemRegion_MEMORY_REGION59,
+    /** Configure memory region 60. */
+    Qmss_MemRegion_MEMORY_REGION60,
+    /** Configure memory region 61. */
+    Qmss_MemRegion_MEMORY_REGION61,
+    /** Configure memory region 62. */
+    Qmss_MemRegion_MEMORY_REGION62,
+    /** Configure memory region 63. */
+    Qmss_MemRegion_MEMORY_REGION63
+}Qmss_MemRegion;
+
+/** 
+ * @brief PDSP ID
+ */
+typedef enum
+{
+    /** PDSP 1 */
+    Qmss_PdspId_PDSP1 = 0,
+    /** PDSP 2 */
+    Qmss_PdspId_PDSP2,
+    /** PDSP 3 */
+    Qmss_PdspId_PDSP3,
+    /** PDSP 4 */
+    Qmss_PdspId_PDSP4,
+    /** PDSP 5 */
+    Qmss_PdspId_PDSP5,
+    /** PDSP 6 */
+    Qmss_PdspId_PDSP6,
+    /** PDSP 7 */
+    Qmss_PdspId_PDSP7,
+    /** PDSP 8 */
+    Qmss_PdspId_PDSP8
+}Qmss_PdspId;
+
+/** 
+ * @brief Queue handle
+ */
+typedef int32_t   Qmss_QueueHnd;
+
+/** 
+ * @brief QMSS return result
+ */
+typedef int32_t   Qmss_Result;
+
+/** 
+ * @brief Handle used in the "Fast Push" set of APIs
+ */
+typedef uint32_t* Qmss_QueuePushHnd;
+
+/**
+ * @brief Map PDK HAL to Linux OSAL
+ */
+#define ti_em_hw_queue_open      ti_em_osal_hw_queue_open
+#define ti_em_hw_queue_close     ti_em_osal_hw_queue_close
+
+/* Retrieve QMSS manager number from queue (8192 queues per QMSS) */
+#define ti_em_qmss_get(queue)    ((queue) >> 13)
+
+/* Retrieve absolute base queue for a given infrastructure DMA */
+#define ti_em_qmss_get_dma_queue_base(dma_idx) ((dma_idx == Cppi_CpDma_QMSS_CPDMA) ? \
+						QMSS_QM1_INFRASTRUCTURE_DMA_QUEUE_BASE : \
+						QMSS_QM2_INFRASTRUCTURE_DMA_QUEUE_BASE)
+/*
+ * XGE
+ */
+#define TI_EM_XGE_FLOW_NUM       (16) /* total number of flow used for XGE (8 VLAN priorities per interface) */
+
+#ifdef TI_EM_XGE_LOOPBACK
+/* Use infra-PktDMA to simulate XGE */
+#define TI_EM_XGE_FLOW_IDX_START (14) /* starting at flow 14 */
+#define TI_EM_XGE_TX_QUEUE_BASE  (QMSS_INFRASTRUCTURE_QUEUE_BASE)
+#define TI_EM_XGE_TMP_RX_QUEUE   (QMSS_GENERAL_PURPOSE_QUEUE_BASE + QMSS_MAX_GENERAL_PURPOSE_QUEUE -  TI_EM_XGE_FLOW_NUM)
+#else /* TI_EM_XGE_LOOPBACK */
+/* XGE transmit queue base */
+#define TI_EM_XGE_FLOW_IDX_START (0) /* starting at first flow */
+#define TI_EM_XGE_TX_QUEUE_BASE  (QMSS_XGE_QUEUE_BASE)
+#endif /* TI_EM_XGE_LOOPBACK */
+
+#endif /*TI_EM_HW_QMSS_H_*/
diff --git a/platform/linux-keystone2/prebuilts/openem/include/linux/osal/ti_em_osal.h b/platform/linux-keystone2/prebuilts/openem/include/linux/osal/ti_em_osal.h
new file mode 100644
index 0000000..0b49d60
--- /dev/null
+++ b/platform/linux-keystone2/prebuilts/openem/include/linux/osal/ti_em_osal.h
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2013, Texas Instruments Incorporated - http://www.ti.com/
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *       * Redistributions of source code must retain the above copyright
+ *         notice, this list of conditions and the following disclaimer.
+ *       * Redistributions in binary form must reproduce the above copyright
+ *         notice, this list of conditions and the following disclaimer in the
+ *         documentation and/or other materials provided with the distribution.
+ *       * Neither the name of Texas Instruments Incorporated nor the
+ *         names of its contributors may be used to endorse or promote products
+ *         derived from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ *   WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY
+ *   DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ *   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *   ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ *   @file  ti_em_osal_cma.h
+ *
+ *   @brief
+ *      This is the OS abstraction layer for basic services (log, timers, ...).
+ *
+ */
+
+#ifndef TI_EM_OSAL_H_
+#define TI_EM_OSAL_H_
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <unistd.h>
+#include <time.h>
+#include <sched.h>
+#include <signal.h>
+
+#include <ti_em_hw_functions.h>
+
+/*
+ * Trace, error and assert logging macros
+ */
+#define __TI_EM_OSAL_PRINTF(tl, type, fmt, args...)			\
+    do{ if ((tl) <= TI_EM_TRACE_LEVEL) printf("EM[%s][C%d] %s(): " fmt, type, ti_em_osal_get_core_idx(), __FUNCTION__ , ## args); } while(0);
+#define TI_EM_OSAL_ERROR(fmt, args...)      __TI_EM_OSAL_PRINTF(1,  "error", fmt, ## args)
+#define TI_EM_OSAL_TRACE(tl, fmt, args...)  __TI_EM_OSAL_PRINTF(tl, "trace", fmt, ## args)
+#define TI_EM_OSAL_PRINTF(fmt, args...)     printf(fmt, ## args)
+
+#if (EM_CHECK_LEVEL >= 1)
+#define TI_EM_OSAL_ASSERT(cond)             if (!(cond)) TI_EM_OSAL_TRACE(0, "ASSERT %s FAILURE\n", # cond)
+#else
+#define TI_EM_OSAL_ASSERT(cond)
+#endif
+
+#define PAGE_ALIGN_UP(x)     (((x) + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1))
+#define PAGE_ALIGN_LOW(x)    (((x) & ~(PAGE_SIZE - 1)))
+
+/*
+ * Functions to map OS basic services
+ */
+#define TI_EM_OSAL_TIMER_LOCAL    (0)
+#define TI_EM_OSAL_TIMER_GLOBAL   (1)
+
+static inline int ti_em_osal_timer_init(int type)
+{
+	if (type ==  TI_EM_OSAL_TIMER_LOCAL) {
+#ifdef TI_EM_HW_HAS_FAST_TSC
+		return TI_EM_HW_INIT_TSC();
+#endif
+	}
+	return 0;
+}
+
+/*
+ * Retrieve current time:
+ * - local time is in cycles (direct core timestamp counter)
+ * - global time is in nanoseconds (Linux syscall) but is consistent accross cores
+ */
+static inline uint64_t ti_em_osal_timer_read(int type)
+{
+	struct timespec ts;
+	
+#ifdef TI_EM_HW_HAS_FAST_TSC
+	if (type == TI_EM_OSAL_TIMER_LOCAL)
+		return TI_EM_HW_GET_TSC();
+#endif	
+	(void) clock_gettime(type == TI_EM_OSAL_TIMER_LOCAL ?
+			     CLOCK_PROCESS_CPUTIME_ID : CLOCK_MONOTONIC, &ts);
+
+	return (((uint64_t) ts.tv_sec * 1000000000ULL) + (uint64_t) ts.tv_nsec); 
+}
+
+/*
+ * Wait until data written to memory
+ */
+static inline void ti_em_osal_mfence(void)
+{
+	TI_EM_ARCH_MEM_BARRIER();
+}
+
+/*
+ * Cache management functions (not used on Linux)
+ */
+static inline void ti_em_osal_cache_wbinv_L1D(void* block_ptr, unsigned int count) {(void)block_ptr; (void)count;}
+static inline void ti_em_osal_cache_wbinv_L2(void* block_ptr, unsigned int count) {(void)block_ptr; (void)count;}
+static inline void ti_em_osal_cache_wb_L1D(void* block_ptr, unsigned int count) {(void)block_ptr; (void)count;}
+static inline void ti_em_osal_cache_wb_L2(void* block_ptr, unsigned int count) {(void)block_ptr; (void)count;}
+static inline void ti_em_osal_cache_inv_L1D(void* block_ptr, unsigned int count) {(void)block_ptr; (void)count;}
+static inline void ti_em_osal_cache_inv_L2(void* block_ptr, unsigned int count) {(void)block_ptr; (void)count;}
+static inline void ti_em_osal_cache_inv_all_L2(void) { }
+static inline void ti_em_osal_cache_inv_prefetch(void) { }
+
+/*
+ * Main exit wrapper
+ */
+static inline void ti_em_osal_exit(int retval) 
+{
+	exit(retval);
+}
+
+#endif /*TI_EM_OSAL_H_*/
diff --git a/platform/linux-keystone2/prebuilts/openem/include/linux/osal/ti_em_osal_cma.h b/platform/linux-keystone2/prebuilts/openem/include/linux/osal/ti_em_osal_cma.h
new file mode 100644
index 0000000..10a7737
--- /dev/null
+++ b/platform/linux-keystone2/prebuilts/openem/include/linux/osal/ti_em_osal_cma.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2013, Texas Instruments Incorporated - http://www.ti.com/
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *       * Redistributions of source code must retain the above copyright
+ *         notice, this list of conditions and the following disclaimer.
+ *       * Redistributions in binary form must reproduce the above copyright
+ *         notice, this list of conditions and the following disclaimer in the
+ *         documentation and/or other materials provided with the distribution.
+ *       * Neither the name of Texas Instruments Incorporated nor the
+ *         names of its contributors may be used to endorse or promote products
+ *         derived from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ *   WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY
+ *   DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ *   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *   ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/**
+ *   @file  ti_em_osal_cma.h
+ *
+ *   @brief
+ *      This is the OS abstraction layer for the CMA and kernel services management.
+ *
+ */
+
+#ifndef TI_EM_OSAL_CMA_H_
+#define TI_EM_OSAL_CMA_H_
+
+#include <event_machine_hw_ti_macros.h>
+#include <ti_em_hw_mach.h>
+
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <sys/mman.h>
+#include <sys/ioctl.h>
+#include <fcntl.h>
+#include <errno.h>
+
+#define TI_EM_OSAL_CMA_DEVICE   "/dev/openem0"
+
+#define EM_IOC_MAGIC		'O'
+#define EM_IOC_ALLOC	        _IOWR(EM_IOC_MAGIC, 0, int)
+#define EM_IOC_ENABLEPMU        _IO(EM_IOC_MAGIC, 1)
+
+extern int   ti_em_osal_cma_init(void);
+extern void* ti_em_osal_cma_alloc(unsigned int size, int flags, unsigned int *paddr);
+extern void  ti_em_osal_cma_exit(void);
+extern int   ti_em_osal_cma_enable_user_pmu(void);
+
+#endif /*TI_EM_OSAL_CMA_H_*/
diff --git a/platform/linux-keystone2/prebuilts/openem/include/linux/osal/ti_em_osal_core.h b/platform/linux-keystone2/prebuilts/openem/include/linux/osal/ti_em_osal_core.h
new file mode 100644
index 0000000..116431f
--- /dev/null
+++ b/platform/linux-keystone2/prebuilts/openem/include/linux/osal/ti_em_osal_core.h
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2013, Texas Instruments Incorporated - http://www.ti.com/
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *       * Redistributions of source code must retain the above copyright
+ *         notice, this list of conditions and the following disclaimer.
+ *       * Redistributions in binary form must reproduce the above copyright
+ *         notice, this list of conditions and the following disclaimer in the
+ *         documentation and/or other materials provided with the distribution.
+ *       * Neither the name of Texas Instruments Incorporated nor the
+ *         names of its contributors may be used to endorse or promote products
+ *         derived from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ *   WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY
+ *   DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ *   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *   ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/**
+ *   @file  ti_em_osal_core.h
+ *
+ *   @brief
+ *      This is the OS abstraction layer for the core execution services.
+ *
+ */
+
+#ifndef TI_EM_OSAL_CORE_H_
+#define TI_EM_OSAL_CORE_H_
+
+#include <ti_em_osal.h>
+
+#include <sys/mman.h>
+
+#define TI_EM_OSAL_CORE_NUM (8) /* max number of cores manageable by the OSAL library for Core Id */
+
+#ifdef TI_EM_THREAD_MODEL
+ #include <pthread.h>
+ #ifdef TI_EM_HAS___THREAD
+ #define TI_EM_OSAL_CORE_LOCAL_VARIABLE(type, var)  __thread type var
+ #define TI_EM_OSAL_CORE_LOCAL_INIT(var)
+ #define TI_EM_OSAL_CORE_LOCAL_STORE(var, value)    var = *value
+ #define TI_EM_OSAL_CORE_LOCAL_READ(var, dest)      dest = var
+ #define TI_EM_OSAL_CORE_LOCAL_WRITE(var, value)    var = value
+ #else /* TI_EM_HAS___THREAD */
+ #define TI_EM_OSAL_CORE_LOCAL_VARIABLE(type, var)  pthread_key_t __key_##var
+ #define TI_EM_OSAL_CORE_LOCAL_INIT(var)            (void) pthread_key_create(&__key_##var, NULL)
+ #define TI_EM_OSAL_CORE_LOCAL_STORE(var, value)    (void) pthread_setspecific(__key_##var, value)
+
+ #define TI_EM_OSAL_CORE_LOCAL_READ(var, dest)				\
+	{								\
+		typeof(dest) *ptr =					\
+			(typeof(dest)*) pthread_getspecific( __key_##var); \
+		dest = *ptr;						\
+	}
+
+ #define TI_EM_OSAL_CORE_LOCAL_WRITE(var, value)				\
+	{								\
+		typeof(value) *ptr =					\
+			(typeof(value)*) pthread_getspecific( __key_##var); \
+		*ptr = value;						\
+	}
+
+ #endif  /* TI_EM_HAS___THREAD */
+#else   /* TI_EM_THREAD_MODEL */
+ /* Here are the process model definitions and macros */
+ #include <unistd.h>
+ #include <sys/types.h>
+ #include <sys/wait.h>
+ #include <semaphore.h>
+ #include <sched.h>
+ #define TI_EM_OSAL_CORE_LOCAL_VARIABLE(type, var)   type var
+ #define TI_EM_OSAL_CORE_LOCAL_INIT(var, value)
+ #define TI_EM_OSAL_CORE_LOCAL_STORE(var, value)
+ #define TI_EM_OSAL_CORE_LOCAL_READ(var, dest)       dest =  var
+ #define TI_EM_OSAL_CORE_LOCAL_WRITE(var, value)     var = value
+#endif  /* TI_EM_THREAD_MODEL */
+
+extern TI_EM_OSAL_CORE_LOCAL_VARIABLE(uint32_t, __ti_em_osal_core_id);
+
+/*
+ * Return the EM core index
+ */
+static inline uint32_t ti_em_osal_get_core_idx(void)
+{
+	uint32_t id;
+	TI_EM_OSAL_CORE_LOCAL_READ(__ti_em_osal_core_id, id);
+	return id;
+}
+
+/*
+ * Return the hardware core number on which we run (aka cpu id)
+ */
+static inline uint32_t ti_em_osal_get_hw_core(void)
+{
+#ifdef TI_EM_C66X
+	return 0;
+#else
+	return sched_getcpu();
+#endif
+}
+
+static inline int ti_em_osal_core_mlock(void)
+{
+	return mlockall(MCL_FUTURE);
+}
+
+extern int   ti_em_osal_core_spawn(int(*start_routine)(void*), void *arg);
+extern int   ti_em_osal_core_instance_create(int(*start_routine)(void*), void *arg);
+extern int   ti_em_osal_core_exit(int retval);
+extern int   ti_em_osal_core_wait_exit(int core_handler, int *retval);
+extern int   ti_em_osal_core_kill(int core_handler, int sig);
+extern int   ti_em_osal_core_set_affinity(int core_handler, int hw_core_id);
+extern int   ti_em_osal_core_set_rt_priority(int core_handler, int priority);
+extern void  ti_em_osal_core_lock(void);
+extern void  ti_em_osal_core_unlock(void);
+extern int   ti_em_osal_core_barrier_init(int core_num);
+extern void  ti_em_osal_core_barrier_wait(void);
+extern void* ti_em_osal_alloc_per_core(void *ptr, uint32_t size);
+extern void* ti_em_osal_alloc_shared(void *ptr, uint32_t size);
+extern void  ti_em_osal_core_init_global(void);
+extern int   ti_em_osal_core_join(int core_id);
+
+#endif /* TI_EM_OSAL_CORE_H_ */
diff --git a/platform/linux-keystone2/prebuilts/openem/include/linux/osal/ti_em_osal_cppi.h b/platform/linux-keystone2/prebuilts/openem/include/linux/osal/ti_em_osal_cppi.h
new file mode 100644
index 0000000..0526dd8
--- /dev/null
+++ b/platform/linux-keystone2/prebuilts/openem/include/linux/osal/ti_em_osal_cppi.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2013, Texas Instruments Incorporated - http://www.ti.com/
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *       * Redistributions of source code must retain the above copyright
+ *         notice, this list of conditions and the following disclaimer.
+ *       * Redistributions in binary form must reproduce the above copyright
+ *         notice, this list of conditions and the following disclaimer in the
+ *         documentation and/or other materials provided with the distribution.
+ *       * Neither the name of Texas Instruments Incorporated nor the
+ *         names of its contributors may be used to endorse or promote products
+ *         derived from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ *   WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY
+ *   DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ *   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *   ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/**
+ *   @file  ti_em_osal_cppi.h
+ *
+ *   @brief
+ *      This is the OS abstraction layer for the PktDMA (CPPI) management.
+ *
+ */
+
+#ifndef TI_EM_OSAL_CPPI_H_
+#define TI_EM_OSAL_CPPI_H_
+
+#include <event_machine_types.h>
+
+#include <ti_em_hw_csl.h>
+#include <ti_em_hw_qmss.h>
+#include <ti_em_hw_cppi.h>
+
+#include <ti_em_osal_uaccess.h>
+#include <ti_em_osal_queue.h>
+
+extern Cppi_GlobalCPDMAConfigParams ti_em_osal_cppi_global_cfg_params[CPPI_MAX_CPDMA];
+
+extern em_status_t ti_em_osal_cppi_rx_flow_open(int dma_idx, int flow_idx, int dst_queue, int free_queue, int error_handling);
+extern em_status_t ti_em_osal_cppi_tx_channel_open(int dma_idx, int channel_idx);
+extern em_status_t ti_em_osal_cppi_rx_channel_open(int dma_idx, int channel_idx);
+extern em_status_t ti_em_osal_cppi_rx_flow_close(int dma_idx, int flow_idx);
+extern em_status_t ti_em_osal_cppi_tx_channel_close(int dma_idx, int channel_idx);
+extern em_status_t ti_em_osal_cppi_rx_channel_close(int dma_idx, int channel_idx);
+extern em_status_t ti_em_osal_cppi_init(void);
+extern em_status_t ti_em_osal_chain_rx_flow_open(int dma_idx,
+						 int flow_idx,
+						 int dst_queue,
+						 int free_queue_sizea,
+						 int sizea,
+						 int free_queue_sizeb,
+						 int sizeb,
+						 int free_queue_sizec,
+						 int sizec,
+						 int free_queue_sized,
+						 int sized,
+						 int free_queue_overflow,
+						 int error_handling);
+extern ti_em_queue_id_t ti_em_osal_cppi_get_absolute_queue_id(ti_em_dma_id_t dma_idx, ti_em_queue_id_t queue_idx);
+
+#endif /*TI_EM_OSAL_CPPI_H_*/
diff --git a/platform/linux-keystone2/prebuilts/openem/include/linux/osal/ti_em_osal_event.h b/platform/linux-keystone2/prebuilts/openem/include/linux/osal/ti_em_osal_event.h
new file mode 100644
index 0000000..2eb6c2b
--- /dev/null
+++ b/platform/linux-keystone2/prebuilts/openem/include/linux/osal/ti_em_osal_event.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2013, Texas Instruments Incorporated - http://www.ti.com/
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *       * Redistributions of source code must retain the above copyright
+ *         notice, this list of conditions and the following disclaimer.
+ *       * Redistributions in binary form must reproduce the above copyright
+ *         notice, this list of conditions and the following disclaimer in the
+ *         documentation and/or other materials provided with the distribution.
+ *       * Neither the name of Texas Instruments Incorporated nor the
+ *         names of its contributors may be used to endorse or promote products
+ *         derived from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ *   WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY
+ *   DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ *   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *   ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/**
+ *   @file  ti_em_osal_event.h
+ *
+ *   @brief
+ *      This is the OS abstraction layer for waiting events
+ *
+ */
+#ifndef TI_EM_OSAL_EVENT_H_
+#define TI_EM_OSAL_EVENT_H_
+
+#include <event_machine_hw_ti_macros.h>
+#include <ti_em_hw_mach.h>
+
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <sys/mman.h>
+#include <sys/ioctl.h>
+#include <fcntl.h>
+#include <errno.h>
+
+#define TI_EM_OSAL_EVENT_DEVICE_BASENAME   "/dev/openem"
+
+struct ti_em_intd_irq_config {
+	int channel_base;
+	int intd;
+};
+
+#define EM_IOC_MAGIC		           'O'
+#define EM_IOC_WAITEVENT                   _IO(EM_IOC_MAGIC, 2)
+#define EM_IOC_WAITEVENTINIT               _IOWR(EM_IOC_MAGIC, 3, struct ti_em_intd_irq_config)
+#define EM_IOC_WAITEVENTFREE               _IO(EM_IOC_MAGIC, 4)
+
+extern int  ti_em_osal_event_init(int pdsp, int channel_base);
+extern int  ti_em_osal_event_release(void);
+extern int  ti_em_osal_event_wait(void);
+
+#endif /*TI_EM_OSAL_EVENT_H_*/
diff --git a/platform/linux-keystone2/prebuilts/openem/include/linux/osal/ti_em_osal_firmware.h b/platform/linux-keystone2/prebuilts/openem/include/linux/osal/ti_em_osal_firmware.h
new file mode 100644
index 0000000..99fdd9d
--- /dev/null
+++ b/platform/linux-keystone2/prebuilts/openem/include/linux/osal/ti_em_osal_firmware.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2013, Texas Instruments Incorporated - http://www.ti.com/
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *       * Redistributions of source code must retain the above copyright
+ *         notice, this list of conditions and the following disclaimer.
+ *       * Redistributions in binary form must reproduce the above copyright
+ *         notice, this list of conditions and the following disclaimer in the
+ *         documentation and/or other materials provided with the distribution.
+ *       * Neither the name of Texas Instruments Incorporated nor the
+ *         names of its contributors may be used to endorse or promote products
+ *         derived from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ *   WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY
+ *   DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ *   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *   ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/**
+ *   @file  ti_em_osal_cma.h
+ *
+ *   @brief
+ *      This is the OS abstraction layer for the firmware management.
+ *
+ */
+
+#ifndef TI_EM_OSAL_FIRMWARE_H_
+#define TI_EM_OSAL_FIRMWARE_H_
+
+extern em_status_t ti_em_osal_pdsp_download_firmware(short pdsp_id, void* firmware, unsigned int size);
+extern em_status_t ti_em_osal_pdsp_stop(short pdsp_id);
+
+#endif /*TI_EM_OSAL_FIRMWARE_H_*/
diff --git a/platform/linux-keystone2/prebuilts/openem/include/linux/osal/ti_em_osal_queue.h b/platform/linux-keystone2/prebuilts/openem/include/linux/osal/ti_em_osal_queue.h
new file mode 100644
index 0000000..f7c5ff1
--- /dev/null
+++ b/platform/linux-keystone2/prebuilts/openem/include/linux/osal/ti_em_osal_queue.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2013, Texas Instruments Incorporated - http://www.ti.com/
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *       * Redistributions of source code must retain the above copyright
+ *         notice, this list of conditions and the following disclaimer.
+ *       * Redistributions in binary form must reproduce the above copyright
+ *         notice, this list of conditions and the following disclaimer in the
+ *         documentation and/or other materials provided with the distribution.
+ *       * Neither the name of Texas Instruments Incorporated nor the
+ *         names of its contributors may be used to endorse or promote products
+ *         derived from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ *   WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY
+ *   DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ *   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *   ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/**
+ *   @file  ti_em_osal_queue.h
+ *
+ *   @brief
+ *      This is the OS abstraction layer for the QMSS management.
+ *
+ */
+
+#ifndef TI_EM_OSAL_QUEUE_H_
+#define TI_EM_OSAL_QUEUE_H_
+
+#include <event_machine_types.h>
+
+#include <ti_em_hw_csl.h>
+#include <ti_em_hw_qmss.h>
+#include <ti_em_hw_cppi.h>
+
+#include <ti_em_osal_uaccess.h>
+
+typedef struct ti_em_osal_hw_region_config_t_
+{
+	uint32_t    region_idx;
+	phys_addr_t desc_base;
+	uint32_t    desc_vbase;
+	uint32_t    desc_offset;
+	uint32_t    desc_size;
+	uint32_t    desc_num;
+	uint32_t    desc_flag;
+	int32_t     start_idx;
+} ti_em_osal_hw_region_config_t;
+
+extern em_status_t  ti_em_osal_hw_queue_open(int queue);
+extern em_status_t  ti_em_osal_hw_queue_close(int queue);
+extern em_status_t  ti_em_osal_hw_queue_empty(int queue);
+extern em_status_t  ti_em_osal_hw_queue_insert_region(ti_em_osal_hw_region_config_t *config, int qmss);
+extern unsigned int ti_em_osal_hw_queue_get_memory_region_addr(short memory_idx, int qmss);
+extern void         ti_em_osal_hw_queue_push(int queue, void *desc, short mapping);
+extern void         ti_em_osal_hw_queue_push_size(int queue, void *desc, int size, short mapping);
+
+extern void         ti_em_osal_hw_queue_push_to_head(int queue, void *desc, short mapping);
+extern void*        ti_em_osal_hw_queue_pop(int queue, short mapping);
+extern void         ti_em_osal_hw_queue_set_threshold(int queue, short hilo, char threshold);
+extern void         ti_em_osal_hw_queue_divert(int src_queue, int dst_queue, char location);
+extern unsigned int ti_em_osal_hw_queue_peek(int queue);
+
+static inline void* ti_em_osal_queue_desc_ptov(unsigned int paddr, short mapping) {
+	return (paddr == 0) ?
+		NULL : (void*) ti_em_osal_mem_phys_to_virt(paddr, mapping);
+}
+
+static inline unsigned int ti_em_osal_queue_desc_vtop(void *vaddr, short mapping) {
+	return (vaddr == NULL) ?
+		0 : ti_em_osal_mem_virt_to_phys((unsigned int) vaddr, mapping);
+}
+
+#endif /*TI_EM_OSAL_QUEUE_H_*/
diff --git a/platform/linux-keystone2/prebuilts/openem/include/linux/osal/ti_em_osal_shm.h b/platform/linux-keystone2/prebuilts/openem/include/linux/osal/ti_em_osal_shm.h
new file mode 100644
index 0000000..39c1927
--- /dev/null
+++ b/platform/linux-keystone2/prebuilts/openem/include/linux/osal/ti_em_osal_shm.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2013, Texas Instruments Incorporated - http://www.ti.com/
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *       * Redistributions of source code must retain the above copyright
+ *         notice, this list of conditions and the following disclaimer.
+ *       * Redistributions in binary form must reproduce the above copyright
+ *         notice, this list of conditions and the following disclaimer in the
+ *         documentation and/or other materials provided with the distribution.
+ *       * Neither the name of Texas Instruments Incorporated nor the
+ *         names of its contributors may be used to endorse or promote products
+ *         derived from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ *   WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY
+ *   DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ *   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *   ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/**
+ *   @file  ti_em_osal_shm.h
+ *
+ *   @brief
+ *      This is the OS abstraction layer for the shared memory management
+ *
+ */
+
+#ifndef TI_EM_OSAL_SHM_H_
+#define TI_EM_OSAL_SHM_H_
+
+extern int   ti_em_osal_shm_init(int id, const char *shm_name, unsigned int size, short create);
+extern void  ti_em_osal_shm_release(int id);
+extern void* ti_em_osal_shm_get(int id, unsigned int size);
+extern void* ti_em_osal_shm_alloc(int id, unsigned int size);
+extern void  ti_em_osal_shm_free(void *ptr);
+
+
+#define TI_EM_OSAL_SHM_MAPPING_NUM             8 /* number of shared memory mappings */
+#define TI_EM_OSAL_SHM_OSAL_ID                 1 /* shared mem Id 1 is used by OSAL */
+#define TI_EM_OSAL_SHM_OSAL_NAME               "openem_osal"
+#define TI_EM_OSAL_SHM_OSAL_MAPPING_DB_ID      2 /* shared mem Id 2 is used for OSAL mapping db */
+#define TI_EM_OSAL_SHM_OSAL_MAPPING_DB_NAME    "openem_osal_mapping_db"
+#define TI_EM_OSAL_SHM_DEFAULT_ID              3 /* first available mapping*/
+
+#define TI_EM_OSAL_SHM_GLOBAL_ALLOC(p) p  = (typeof(p)) ti_em_osal_shm_alloc(TI_EM_OSAL_SHM_DEFAULT_ID, \
+									     sizeof(*p))
+
+#endif /* TI_EM_OSAL_SHM_H_ */
diff --git a/platform/linux-keystone2/prebuilts/openem/include/linux/osal/ti_em_osal_uaccess.h b/platform/linux-keystone2/prebuilts/openem/include/linux/osal/ti_em_osal_uaccess.h
new file mode 100644
index 0000000..dec8624
--- /dev/null
+++ b/platform/linux-keystone2/prebuilts/openem/include/linux/osal/ti_em_osal_uaccess.h
@@ -0,0 +1,119 @@
+/*
+ * Copyright (c) 2013, Texas Instruments Incorporated - http://www.ti.com/
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *       * Redistributions of source code must retain the above copyright
+ *         notice, this list of conditions and the following disclaimer.
+ *       * Redistributions in binary form must reproduce the above copyright
+ *         notice, this list of conditions and the following disclaimer in the
+ *         documentation and/or other materials provided with the distribution.
+ *       * Neither the name of Texas Instruments Incorporated nor the
+ *         names of its contributors may be used to endorse or promote products
+ *         derived from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ *   WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY
+ *   DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ *   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *   ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/**
+ *   @file  ti_em_osal_uaccess.h
+ *
+ *   @brief
+ *      This is the OS abstraction layer for the I/O accesses from user mode
+ *
+ */
+
+#ifndef TI_EM_OSAL_UACCESS_H_
+#define TI_EM_OSAL_UACCESS_H_
+
+#include <event_machine_hw_ti_macros.h>
+#include <ti_em_hw_mach.h>
+
+#define TI_EM_OSAL_MEM_UACCESS_DEVICE    "/dev/openem0"
+
+#define TI_EM_OSAL_MEM_CACHED            (0x0)
+#define TI_EM_OSAL_MEM_UNCACHED          (0x1)
+
+#define TI_EM_OSAL_DEFAULT_MAPPING_FLAGS (TI_EM_OSAL_MEM_UNCACHED)
+
+typedef unsigned int phys_addr_t;
+
+struct ti_em_osal_mem_mapping {
+	int          fd;
+	phys_addr_t  paddr;
+	unsigned int vaddr;
+	unsigned int size;
+	off_t        offset;
+	unsigned int flags;
+};
+
+extern struct ti_em_osal_mem_mapping __ti_em_osal_mem_mappings[TI_EM_MEM_NUM];
+
+/*
+ * Transform a physical address to a virtual one for a given mapping
+ *
+ * There is no check here since we must do this fast.
+ */
+static inline unsigned int ti_em_osal_mem_phys_to_virt(phys_addr_t paddr, short mapping)
+{
+	return __ti_em_osal_mem_mappings[mapping].vaddr
+	    + (paddr - __ti_em_osal_mem_mappings[mapping].paddr);
+}
+
+/*
+ * Transform a physical address to a virtual one for a given mapping
+ *
+ * There is no check here since we must do this fast.
+ */
+static inline phys_addr_t ti_em_osal_mem_virt_to_phys(unsigned int vaddr, short mapping)
+{
+	return (phys_addr_t) __ti_em_osal_mem_mappings[mapping].paddr
+	    + (vaddr -  __ti_em_osal_mem_mappings[mapping].vaddr);
+}
+
+static inline unsigned int ti_em_osal_io_phys_to_virt(phys_addr_t paddr)
+{
+	return (unsigned int) ti_em_osal_mem_phys_to_virt(paddr, TI_EM_MEM_QMSS_REGS);
+}
+
+static inline phys_addr_t ti_em_osal_io_virt_to_phys(unsigned int vaddr)
+{
+	return (phys_addr_t) ti_em_osal_mem_virt_to_phys(vaddr, TI_EM_MEM_QMSS_REGS);
+}
+
+static inline phys_addr_t ti_em_osal_get_mem_base(short mapping)
+{
+	return __ti_em_osal_mem_mappings[mapping].paddr;
+}
+
+extern phys_addr_t __ti_em_osal_pdsp_comm_mem_base;
+
+static inline phys_addr_t ti_em_osal_get_pdsp_comm_mem_base(uint32_t slot)
+{
+	return __ti_em_osal_pdsp_comm_mem_base + (slot * PAGE_SIZE);
+}
+
+static inline void ti_em_osal_set_pdsp_comm_mem_base(phys_addr_t paddr)
+{
+	__ti_em_osal_pdsp_comm_mem_base = paddr;
+}
+
+extern int ti_em_osal_create_mapping(short mapping, struct ti_em_osal_mem_mapping *mapping_info);
+extern void ti_em_osal_release_mapping(short mapping);
+
+#ifndef TI_EM_THREAD_MODEL
+extern int ti_em_osal_retrieve_mapping(short mapping, struct ti_em_osal_mem_mapping *mapping_info);
+#endif
+
+#endif /*TI_EM_OSAL_UACCESS_H_*/
diff --git a/platform/linux-keystone2/prebuilts/openem/include/linux/osal/ti_em_osal_xge.h b/platform/linux-keystone2/prebuilts/openem/include/linux/osal/ti_em_osal_xge.h
new file mode 100644
index 0000000..5299580
--- /dev/null
+++ b/platform/linux-keystone2/prebuilts/openem/include/linux/osal/ti_em_osal_xge.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2013, Texas Instruments Incorporated - http://www.ti.com/
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *       * Redistributions of source code must retain the above copyright
+ *         notice, this list of conditions and the following disclaimer.
+ *       * Redistributions in binary form must reproduce the above copyright
+ *         notice, this list of conditions and the following disclaimer in the
+ *         documentation and/or other materials provided with the distribution.
+ *       * Neither the name of Texas Instruments Incorporated nor the
+ *         names of its contributors may be used to endorse or promote products
+ *         derived from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ *   WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY
+ *   DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ *   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *   ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/**
+ *   @file  ti_em_osal_xge.c
+ *
+ *   @brief
+ *      This is the OS abstraction layer for the 10Gig Ethernet management.
+ *
+ */
+
+#ifndef TI_EM_OSAL_XGE_H_
+#define TI_EM_OSAL_XGE_H_
+
+#include <event_machine_types.h>
+
+#include <ti_em_hw_csl.h>
+#include <ti_em_hw_qmss.h>
+#include <ti_em_hw_cppi.h>
+
+#include <ti_em_osal_uaccess.h>
+#include <ti_em_osal_queue.h>
+
+extern em_status_t ti_em_osal_xge_rx_flow_open(int dma_idx, int flow_idx, int dst_queue_idx, int free_queue_idx0, int free_queue_idx1, int error_handling);
+extern em_status_t ti_em_osal_xge_tx_channel_open(int dma_idx, int channel_idx);
+extern em_status_t ti_em_osal_xge_rx_channel_open(int dma_idx, int channel_idx);
+extern ti_em_queue_id_t ti_em_osal_xge_tx_queue_open(ti_em_queue_id_t queue_base_idx, int vlan_priority);
+extern em_status_t ti_em_osal_xge_rx_flow_close(int dma_idx, int flow_idx);
+extern em_status_t ti_em_osal_xge_rx_channel_close(int dma_idx, int channel_idx);
+extern em_status_t ti_em_osal_xge_tx_channel_close(int dma_idx, int channel_idx);
+extern ti_em_queue_id_t ti_em_osal_xge_tx_queue_base_idx_get (void);
+extern ti_em_queue_id_t ti_em_osal_xge_rx_queue_idx_get(int flow_idx);
+#ifdef TI_EM_XGE_LOOPBACK
+extern em_status_t ti_em_osal_xge_rx_insert_crc(int flow_idx,
+						ti_em_queue_id_t rx_fragment_free_queue,
+						ti_em_queue_id_t xge_dst_queue,
+						int count);
+#else /* TI_EM_XGE_LOOPBACK */
+static inline em_status_t ti_em_osal_xge_rx_insert_crc(int flow_idx,
+						       ti_em_queue_id_t rx_fragment_free_queue,
+						       ti_em_queue_id_t xge_dst_queue,
+						       int count) { return EM_OK; };
+#endif /* TI_EM_XGE_LOOPBACK */
+#endif /*TI_EM_OSAL_XGE_H_*/
diff --git a/platform/linux-keystone2/prebuilts/openem/include/linux/rh/ti_em_rh.h b/platform/linux-keystone2/prebuilts/openem/include/linux/rh/ti_em_rh.h
new file mode 100644
index 0000000..6e2d262
--- /dev/null
+++ b/platform/linux-keystone2/prebuilts/openem/include/linux/rh/ti_em_rh.h
@@ -0,0 +1,139 @@
+/*
+ * Copyright (c) 2013, Texas Instruments Incorporated - http://www.ti.com/
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *       * Redistributions of source code must retain the above copyright
+ *         notice, this list of conditions and the following disclaimer.
+ *       * Redistributions in binary form must reproduce the above copyright
+ *         notice, this list of conditions and the following disclaimer in the
+ *         documentation and/or other materials provided with the distribution.
+ *       * Neither the name of Texas Instruments Incorporated nor the
+ *         names of its contributors may be used to endorse or promote products
+ *         derived from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ *   WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY
+ *   DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ *   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *   ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/**
+ *   @file  ti_em_rh.h
+ *
+ *   @brief
+ *      This is the OpenEM runtime helper library for Linux
+ *
+ */
+#ifndef _TI_EM_RH_H_
+#define _TI_EM_RH_H_
+
+#include <ti_em_osal.h>
+#include <ti_em_osal_queue.h>
+
+#include <event_machine_hw_ti_types.h>
+
+#define TI_EM_RH_PUBLIC                (0)
+#define TI_EM_RH_PRIVATE               (1)
+
+#define TI_EM_RH_UNMANAGED_DESCRIPTOR  (0)
+#define TI_EM_RH_MANAGE_DESCRIPTOR     (1)
+
+#define TI_EM_RH_POLL_MODE             (0)
+#define TI_EM_RH_INTERRUPT_MODE        (1)
+
+#define TI_EM_RH_PRIVATE_EVENT_NUM     (TI_EM_PDSP_GLOBAL_DATA_SIZE / TI_EM_PRIVATE_EVENT_DSC_SIZE)
+
+/* 
+ * PDSP firmware download information structure
+ */
+typedef struct ti_em_rh_pdsp_config_t_
+{
+	short     pdsp_id;
+	void     *firmware;
+	uint32_t  size; 
+} ti_em_rh_pdsp_config_t;
+
+/*
+ * Physical memory description structure
+ */
+typedef struct ti_em_rh_mem_config_t_
+{
+	phys_addr_t paddr;
+	uint32_t    vaddr;
+	uint32_t    size;
+	uint32_t    offset;
+	uint32_t    mapping_id;
+	uint32_t    flags;
+} ti_em_rh_mem_config_t;
+
+/*
+ * Pool of event configuration structure
+ */
+typedef struct ti_em_rh_pool_config_t_
+{
+	uint32_t              event_num;
+	uint32_t              buffer_size;
+	uint32_t              offset;
+	uint32_t              ps_word_num;
+	uint32_t              free_policy;
+	ti_em_pool_config_t   pool;
+	ti_em_rh_mem_config_t mem;
+} ti_em_rh_pool_config_t;
+
+/*
+ * Main OpenEM hw configuration structure
+ */
+typedef struct ti_em_rh_hw_config_t_
+{
+	ti_em_device_id_t              device_id;
+	ti_em_process_id_t             process_id;
+	ti_em_chain_config_t*          chain_config_ptr;
+	uint32_t                       private_free_queue_idx;
+	uint32_t                       region_num; 
+	ti_em_osal_hw_region_config_t *region_configs;
+	uint32_t                       hw_queue_base_idx;
+	uint32_t                       dma_queue_base_idx;
+	int32_t                        dma_idx;
+	uint32_t                       preload_size_a;
+	uint32_t                       preload_size_b;
+	uint32_t                       preload_size_c;
+	ti_em_rh_mem_config_t          pdsp_comm_mem_config;
+	uint32_t                       pdsp_num;
+	ti_em_rh_pdsp_config_t         pdsp_sched[TI_EM_SCHEDULER_THREAD_NUM];
+	ti_em_rh_pdsp_config_t         pdsp_router;
+	uint32_t                       dispatch_mode;
+	uint32_t                       hw_interrupt_base_idx;
+} ti_em_rh_hw_config_t;
+
+extern em_status_t ti_em_rh_init_global(
+	uint32_t                       pool_num,
+	ti_em_rh_pool_config_t        *pool_configs,
+	uint32_t                       core_num,
+	ti_em_rh_hw_config_t          *hw_config);
+extern em_status_t ti_em_rh_release_global(void);
+extern em_status_t ti_em_rh_init_local(void);
+extern em_status_t ti_em_rh_release_local(void);
+extern em_status_t ti_em_rh_join(int core_id);
+extern em_status_t ti_em_rh_create_cores(
+	int core_num,
+	int(*dispatcher_fn)(void*),
+	int(*init_fn)(void),
+	int hw_core_start);
+extern em_status_t ti_em_rh_wait_cores(int core_num);
+extern em_status_t ti_em_rh_kill_cores(int core_num);
+extern em_status_t ti_em_rh_dispatch(int mode, uint32_t sleep_quota, uint32_t cancel_quota);
+extern int ti_em_rh_alloc_map_cma(ti_em_rh_mem_config_t *mem);
+extern void* ti_em_rh_public_desc_addr(uint32_t idx, uintptr_t *paddr);
+void ti_em_rh_dump_io_mem(phys_addr_t paddr, uint32_t size, const char *desc);
+void ti_em_rh_dump_mem(void *addr, uint32_t size, const char *desc);
+
+#endif /*_TI_EM_RH_H_*/
diff --git a/platform/linux-keystone2/prebuilts/openem/include/src/event_machine_hwpform.h b/platform/linux-keystone2/prebuilts/openem/include/src/event_machine_hwpform.h
new file mode 100644
index 0000000..23e5881
--- /dev/null
+++ b/platform/linux-keystone2/prebuilts/openem/include/src/event_machine_hwpform.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2012, Texas Instruments Incorporated - http://www.ti.com/
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *       * Redistributions of source code must retain the above copyright
+ *         notice, this list of conditions and the following disclaimer.
+ *       * Redistributions in binary form must reproduce the above copyright
+ *         notice, this list of conditions and the following disclaimer in the
+ *         documentation and/or other materials provided with the distribution.
+ *       * Neither the name of Texas Instruments Incorporated nor the
+ *         names of its contributors may be used to endorse or promote products
+ *         derived from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ *   WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY
+ *   DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ *   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *   ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef EVENT_MACHINE_HWPFORM_H_
+#define EVENT_MACHINE_HWPFORM_H_
+
+#ifndef TI_EM_LINUX
+/* CSL Header Files. */
+#include <ti/csl/csl_chip.h>
+#include <ti/csl/csl_cache.h>
+#include <ti/csl/csl_cacheAux.h>
+#include <ti/csl/csl_semAux.h>
+
+/* CPPI/QMSS Include Files. */
+#include <ti/drv/cppi/cppi_drv.h>
+#include <ti/drv/cppi/cppi_desc.h>
+#include <ti/drv/qmss/qmss_drv.h>
+#include <ti/csl/csl_xmcAux.h>
+#else /* TI_EM_LINUX */
+#include <ti_em_hw_mach.h>      /* needed for CACHE_L2_LINESIZE definitions */
+#include <ti_em_hw_csl.h>       /* CPPI/QMSS descriptor definitions */
+#include <ti_em_hw_qmss.h>      /* CPPI/QMSS descriptor definitions */
+#include <ti_em_hw_cppi.h>      /* CPPI/QMSS descriptor definitions */
+#endif /* TI_EM_LINUX */
+
+#endif /*EVENT_MACHINE_HWPFORM_H_ */
