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[54.225.227.206]) by mx.google.com with ESMTPS id 66si9714339qgg.117.2014.08.08.03.49.16 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 08 Aug 2014 03:49:16 -0700 (PDT) Received-SPF: none (google.com: lng-odp-bounces@lists.linaro.org does not designate permitted sender hosts) client-ip=54.225.227.206; Received: from localhost ([127.0.0.1] helo=ip-10-141-164-156.ec2.internal) by ip-10-141-164-156.ec2.internal with esmtp (Exim 4.76) (envelope-from ) id 1XFhjX-0003vq-Pi; Fri, 08 Aug 2014 10:49:15 +0000 Received: from mail-pd0-f178.google.com ([209.85.192.178]) by ip-10-141-164-156.ec2.internal with esmtp (Exim 4.76) (envelope-from ) id 1XFhjR-0003vi-FD for lng-odp@lists.linaro.org; Fri, 08 Aug 2014 10:49:09 +0000 Received: by mail-pd0-f178.google.com with SMTP id w10so6902158pde.9 for ; Fri, 08 Aug 2014 03:49:03 -0700 (PDT) X-Received: by 10.70.140.75 with SMTP id re11mr23567431pdb.65.1407494943882; Fri, 08 Aug 2014 03:49:03 -0700 (PDT) Received: from pnqlab023.amcc.com ([182.73.239.130]) by mx.google.com with ESMTPSA id t7sm3741346pdj.94.2014.08.08.03.49.00 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 08 Aug 2014 03:49:03 -0700 (PDT) From: Ankit Jindal To: lng-odp@lists.linaro.org Date: Fri, 8 Aug 2014 16:18:26 +0530 Message-Id: <1407494906-18610-1-git-send-email-ankit.jindal@linaro.org> X-Mailer: git-send-email 1.7.9.5 X-Topics: Architecture patch Cc: patches@apm.com, Tushar Jagad Subject: [lng-odp] [PATCHv2] Add write memory barrier for aarch64 X-BeenThere: lng-odp@lists.linaro.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Errors-To: lng-odp-bounces@lists.linaro.org Sender: lng-odp-bounces@lists.linaro.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ankit.jindal@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.178 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 This patch updates odp_sync_stores routine to add write memory barrier for aarch64. Signed-off-by: Ankit Jindal Signed-off-by: Tushar Jagad Reviewed-by: Anders Roxell --- include/odp_sync.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/odp_sync.h b/include/odp_sync.h index c106c75..9cf4d46 100644 --- a/include/odp_sync.h +++ b/include/odp_sync.h @@ -31,7 +31,7 @@ static inline void odp_sync_stores(void) __asm__ __volatile__ ("sfence\n" : : : "memory"); -#elif defined __arm__ +#elif defined __arm__ || defined __aarch64__ __asm__ __volatile__ ("dmb st" : : : "memory");