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[54.225.227.206]) by mx.google.com with ESMTPS id s5si5277071qai.126.2014.09.26.02.51.08 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 26 Sep 2014 02:51:08 -0700 (PDT) Received-SPF: none (google.com: lng-odp-bounces@lists.linaro.org does not designate permitted sender hosts) client-ip=54.225.227.206; Received: from localhost ([127.0.0.1] helo=ip-10-35-177-41.ec2.internal) by ip-10-35-177-41.ec2.internal with esmtp (Exim 4.76) (envelope-from ) id 1XXSB9-0001aH-4O; Fri, 26 Sep 2014 09:51:07 +0000 Received: from mail-pa0-f49.google.com ([209.85.220.49]) by ip-10-35-177-41.ec2.internal with esmtp (Exim 4.76) (envelope-from ) id 1XXSB3-0001a5-2W for lng-odp@lists.linaro.org; Fri, 26 Sep 2014 09:51:01 +0000 Received: by mail-pa0-f49.google.com with SMTP id lf10so13007081pab.36 for ; Fri, 26 Sep 2014 02:50:55 -0700 (PDT) X-Received: by 10.66.65.130 with SMTP id x2mr28560165pas.79.1411725054615; Fri, 26 Sep 2014 02:50:54 -0700 (PDT) Received: from yogesh-Dell-System-Vostro-3360.Airtel4Grouter.cpe ([14.140.2.178]) by mx.google.com with ESMTPSA id fp17sm4449618pdb.42.2014.09.26.02.50.51 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 26 Sep 2014 02:50:53 -0700 (PDT) From: Yogesh Tillu To: lng-odp@lists.linaro.org Date: Fri, 26 Sep 2014 15:16:45 +0530 Message-Id: <1411724805-6304-2-git-send-email-yogesh.tillu@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1411724805-6304-1-git-send-email-yogesh.tillu@linaro.org> References: <1411724805-6304-1-git-send-email-yogesh.tillu@linaro.org> X-Topics: patch Cc: Yogesh Tillu Subject: [lng-odp] [PATCH] [Initial Commit] API for Direct access of perf counters from Userspace X-BeenThere: lng-odp@lists.linaro.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Errors-To: lng-odp-bounces@lists.linaro.org Sender: lng-odp-bounces@lists.linaro.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: yogesh.tillu@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.172 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Signed-off-by: Yogesh Tillu --- helper/include/odph_perf.h | 118 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 118 insertions(+) create mode 100644 helper/include/odph_perf.h diff --git a/helper/include/odph_perf.h b/helper/include/odph_perf.h new file mode 100644 index 0000000..3560924 --- /dev/null +++ b/helper/include/odph_perf.h @@ -0,0 +1,118 @@ +/* Copyright (c) 2014, Linaro Limited + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +/** + * @file + * + * ODP Performance Counter Direct access from Userspace Header + */ + +#ifndef ODPH_PERF_H_ +#define ODPH_PERF_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#if __aarch64__ /**< Check for ArmV8 */ +#define ARMV8_PMCNTENSET_EL0_ENABLE (1<<31) /**< Enable Perf count reg */ +#endif + +/** + * Open Performance counter + * + * @note api to enable performance counters in system, this function does + * enable sequence for respective arm versions + * + * @param void + * + * @return 0 if open successfully, otherwise -1 + */ +static inline int odph_perf_open_counter(void) +{ +#if __aarch64__ +/* Performance Monitors Count Enable Set register bit 31:0 disable, +1 enable */ +asm volatile("msr pmcntenset_el0, %0" : : "r" (ARMV8_PMCNTENSET_EL0_ENABLE)); +return 0; +#elif defined(__ARM_ARCH_7A__) + return 0; +#else + #error Unsupported Architecture + return -1; +#endif +} + +/** + * Read Performance counter + * + * @note api to read performance cycle counters in system + * + * @param void + * + * @return cycle counter value if read successfully, otherwise -1 + */ +static inline uint64_t +odph_perf_read_counter(void) +{ +uint64_t ret; +#if defined __aarch64__ + asm volatile("mrs %0, pmccntr_el0" : "=r" (ret)); + return ret; +#elif defined(__ARM_ARCH_7A__) + asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r"(ret)); + return ret; +#else + #error Unsupported architecture/compiler! + return -1; +#endif +} + +/** + * Write Performance counter + * + * @note api to write value to Performance counter, + * NA for now + * + * @param void + * + * @return 0 if written successfully, otherwise -1 + */ +static inline int odph_perf_write_counter(void) +{ +/* TODO: Stub, might be populated based on requirnment */ +} + +/** + * Close Performance counter + * + * @note api to perform close sequnce for cycle counters in system + * + * @param void + * + * @return 0 if close successfully, otherwise -1 + */ +static inline int odph_perf_close_counter(void) +{ +#if defined __aarch64__ +/* Performance Monitors Count Enable Set register bit 31:0 disable, +1 enable */ + asm volatile("msr pmcntenset_el0, %0" : : "r" (0<<31)); + /* Note above statement does not really clearing register. TODO */ + return 0; +#elif defined(__ARM_ARCH_7A__) + return 0; +#else + #error Unsupported architecture/compiler! + return -1; +#endif +} + +#ifdef __cplusplus +} +#endif + +#endif /* ODPH_PERF_H_ */