| Message ID | 20201012105719.12492-1-schalla@marvell.com |
|---|---|
| Headers | show |
| Series | Add Support for Marvell OcteonTX2 Cryptographic | expand |
On Mon, 12 Oct 2020 16:27:08 +0530 Srujana Challa wrote: > On OcteonTX2 SoC, the admin function (AF) is the only one with all > priviliges to configure HW and alloc resources, PFs and it's VFs > have to request AF via mailbox for all their needs. This patch adds > a mailbox interface for CPT PFs and VFs to allocate resources > for cryptography and inline-IPsec. > Inline-IPsec mailbox messages are added here to provide the interface > to Marvell VFIO drivers to allocate and configure HW resources > for inline IPsec feature. > > Signed-off-by: Suheil Chandran <schandran@marvell.com> > Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com> > Signed-off-by: Srujana Challa <schalla@marvell.com> Please drop the IPsec support from this series, and limit it to just what's needed to get the Linux crypto API working.
On Mon, 12 Oct 2020 16:27:13 +0530 Srujana Challa wrote: > +/* tar header as defined in POSIX 1003.1-1990. */ > +struct tar_hdr_t { > + char name[100]; > + char mode[8]; > + char uid[8]; > + char gid[8]; > + char size[12]; > + char mtime[12]; > + char chksum[8]; > + char typeflag; > + char linkname[100]; > + char magic[6]; > + char version[2]; > + char uname[32]; > + char gname[32]; > + char devmajor[8]; > + char devminor[8]; > + char prefix[155]; > +}; > + > +struct tar_blk_t { > + union { > + struct tar_hdr_t hdr; > + char block[TAR_BLOCK_LEN]; > + }; > +}; In networking we've been pushing back on parsing firmware files in the kernel. Why do you need to parse tar archives?
> Subject: [EXT] Re: [PATCH v7,net-next,07/13] crypto: octeontx2: load microcode > and create engine groups > > External Email > > ---------------------------------------------------------------------- > On Mon, 12 Oct 2020 16:27:13 +0530 Srujana Challa wrote: > > +/* tar header as defined in POSIX 1003.1-1990. */ > > +struct tar_hdr_t { > > + char name[100]; > > + char mode[8]; > > + char uid[8]; > > + char gid[8]; > > + char size[12]; > > + char mtime[12]; > > + char chksum[8]; > > + char typeflag; > > + char linkname[100]; > > + char magic[6]; > > + char version[2]; > > + char uname[32]; > > + char gname[32]; > > + char devmajor[8]; > > + char devminor[8]; > > + char prefix[155]; > > +}; > > + > > +struct tar_blk_t { > > + union { > > + struct tar_hdr_t hdr; > > + char block[TAR_BLOCK_LEN]; > > + }; > > +}; > > In networking we've been pushing back on parsing firmware files > in the kernel. Why do you need to parse tar archives? We have 3 variants of crypto engines and each uses a different firmware file. So instead of 3 independent files in /lib/firmware, we have a consolidated tar file. The tar file is a container. Minimal parsing of firmware file is required to ensure parity between engine, firmware and driver. For example we verify version compatibility.
This series introduces crypto(CPT) drivers(PF & VF) for Marvell OcteonTX2 CN96XX Soc. OcteonTX2 SOC's resource virtualization unit (RVU) supports multiple physical and virtual functions. Each of the PF/VF's functionality is determined by what kind of resources are attached to it. When the CPT block is attached to a VF, it can function as a security device. The following document provides an overview of the hardware and different drivers for the OcteonTX2 SOC: https://www.kernel.org/doc/Documentation/networking/device_drivers/marvell/octeontx2.rst The CPT PF driver is responsible for: - Forwarding messages to/from VFs from/to admin function(AF), - Enabling/disabling VFs, - Loading/unloading microcode (creation/deletion of engine groups). The CPT VF driver works as a crypto offload device. This patch series includes: - Patch to update existing Marvell sources to support the CPT driver. - Patch that adds mailbox messages to the admin function (AF) driver, to configure CPT HW registers. - CPT PF driver patches that include AF<=>PF<=>VF mailbox communication, sriov_configure, and firmware load to the acceleration engines. - CPT VF driver patches that include VF<=>PF mailbox communication and crypto offload support through the kernel cryptographic API. This series is tested with CRYPTO_EXTRA_TESTS enabled and CRYPTO_DISABLE_TESTS disabled. Changes since v6: * Removed driver version. Changes since v4: * Rebased the patches onto net-next tree with base 'commit bc081a693a56 ("Merge branch 'Offload-tc-vlan-mangle-to-mscc_ocelot-switch'")' Changes since v3: * Splitup the patches into smaller patches with more informartion. Changes since v2: * Fixed C=1 warnings. * Added code to exit CPT VF driver gracefully. * Moved OcteonTx2 asm code to a header file under include/linux/soc/ Changes since v1: * Moved Makefile changes from patch4 to patch2 and patch3. Srujana Challa (13): octeontx2-pf: move lmt flush to include/linux/soc octeontx2-af: add mailbox interface for CPT octeontx2-af: add debugfs entries for CPT block drivers: crypto: add Marvell OcteonTX2 CPT PF driver crypto: octeontx2: add mailbox communication with AF crypto: octeontx2: enable SR-IOV and mailbox communication with VF crypto: octeontx2: load microcode and create engine groups crypto: octeontx2: add LF framework crypto: octeontx2: add support to get engine capabilities crypto: octeontx2: add mailbox for inline-IPsec RX LF cfg crypto: octeontx2: add virtual function driver support crypto: octeontx2: add support to process the crypto request crypto: octeontx2: register with linux crypto framework MAINTAINERS | 2 + drivers/crypto/marvell/Kconfig | 14 + drivers/crypto/marvell/Makefile | 1 + drivers/crypto/marvell/octeontx2/Makefile | 10 + .../marvell/octeontx2/otx2_cpt_common.h | 132 ++ .../marvell/octeontx2/otx2_cpt_hw_types.h | 464 +++++ .../marvell/octeontx2/otx2_cpt_mbox_common.c | 202 ++ .../marvell/octeontx2/otx2_cpt_reqmgr.h | 197 ++ drivers/crypto/marvell/octeontx2/otx2_cptlf.c | 426 +++++ drivers/crypto/marvell/octeontx2/otx2_cptlf.h | 351 ++++ drivers/crypto/marvell/octeontx2/otx2_cptpf.h | 53 + .../marvell/octeontx2/otx2_cptpf_main.c | 531 ++++++ .../marvell/octeontx2/otx2_cptpf_mbox.c | 424 +++++ .../marvell/octeontx2/otx2_cptpf_ucode.c | 1533 +++++++++++++++ .../marvell/octeontx2/otx2_cptpf_ucode.h | 162 ++ drivers/crypto/marvell/octeontx2/otx2_cptvf.h | 28 + .../marvell/octeontx2/otx2_cptvf_algs.c | 1665 +++++++++++++++++ .../marvell/octeontx2/otx2_cptvf_algs.h | 170 ++ .../marvell/octeontx2/otx2_cptvf_main.c | 408 ++++ .../marvell/octeontx2/otx2_cptvf_mbox.c | 139 ++ .../marvell/octeontx2/otx2_cptvf_reqmgr.c | 539 ++++++ .../ethernet/marvell/octeontx2/af/Makefile | 3 +- .../net/ethernet/marvell/octeontx2/af/mbox.h | 85 + .../net/ethernet/marvell/octeontx2/af/rvu.c | 2 +- .../net/ethernet/marvell/octeontx2/af/rvu.h | 7 + .../ethernet/marvell/octeontx2/af/rvu_cpt.c | 343 ++++ .../marvell/octeontx2/af/rvu_debugfs.c | 342 ++++ .../ethernet/marvell/octeontx2/af/rvu_nix.c | 75 + .../ethernet/marvell/octeontx2/af/rvu_reg.h | 65 +- .../marvell/octeontx2/nic/otx2_common.h | 13 +- include/linux/soc/marvell/octeontx2/asm.h | 29 + 31 files changed, 8395 insertions(+), 20 deletions(-) create mode 100644 drivers/crypto/marvell/octeontx2/Makefile create mode 100644 drivers/crypto/marvell/octeontx2/otx2_cpt_common.h create mode 100644 drivers/crypto/marvell/octeontx2/otx2_cpt_hw_types.h create mode 100644 drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c create mode 100644 drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h create mode 100644 drivers/crypto/marvell/octeontx2/otx2_cptlf.c create mode 100644 drivers/crypto/marvell/octeontx2/otx2_cptlf.h create mode 100644 drivers/crypto/marvell/octeontx2/otx2_cptpf.h create mode 100644 drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c create mode 100644 drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c create mode 100644 drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c create mode 100644 drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.h create mode 100644 drivers/crypto/marvell/octeontx2/otx2_cptvf.h create mode 100644 drivers/crypto/marvell/octeontx2/otx2_cptvf_algs.c create mode 100644 drivers/crypto/marvell/octeontx2/otx2_cptvf_algs.h create mode 100644 drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c create mode 100644 drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c create mode 100644 drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c create mode 100644 drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c create mode 100644 include/linux/soc/marvell/octeontx2/asm.h