| Message ID | 20210115135339.3127198-1-steen.hegelund@microchip.com |
|---|---|
| Headers | show |
| Series | Adding the Sparx5 Switch Driver | expand |
On Fri, Jan 15, 2021 at 02:53:32PM +0100, Steen Hegelund wrote: > Document the Sparx5 switch device driver bindings > > Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> > Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> > --- > .../bindings/net/microchip,sparx5-switch.yaml | 211 ++++++++++++++++++ > 1 file changed, 211 insertions(+) > create mode 100644 Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml > > diff --git a/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml b/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml > new file mode 100644 > index 000000000000..479a36874fe5 > --- /dev/null > +++ b/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml > @@ -0,0 +1,211 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/net/microchip,sparx5-switch.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Microchip Sparx5 Ethernet switch controller > + > +maintainers: > + - Lars Povlsen <lars.povlsen@microchip.com> > + - Steen Hegelund <steen.hegelund@microchip.com> > + > +description: | > + The SparX-5 Enterprise Ethernet switch family provides a rich set of > + Enterprise switching features such as advanced TCAM-based VLAN and > + QoS processing enabling delivery of differentiated services, and > + security through TCAM-based frame processing using versatile content > + aware processor (VCAP). > + > + IPv4/IPv6 Layer 3 (L3) unicast and multicast routing is supported > + with up to 18K IPv4/9K IPv6 unicast LPM entries and up to 9K IPv4/3K > + IPv6 (S,G) multicast groups. > + > + L3 security features include source guard and reverse path > + forwarding (uRPF) tasks. Additional L3 features include VRF-Lite and > + IP tunnels (IP over GRE/IP). > + > + The SparX-5 switch family targets managed Layer 2 and Layer 3 > + equipment in SMB, SME, and Enterprise where high port count > + 1G/2.5G/5G/10G switching with 10G/25G aggregation links is required. > + > +properties: > + $nodename: > + pattern: "^switch@[0-9a-f]+$" > + > + compatible: > + const: microchip,sparx5-switch > + > + reg: > + minItems: 2 > + > + reg-names: > + items: > + - const: devices > + - const: gcb > + > + interrupts: > + maxItems: 1 > + description: Interrupt used for reception of packets to the CPU > + > + mac-address: > + maxItems: 1 The MAC address is 1 byte? > + description: > + Specifies the MAC address that is used as the template for the MAC > + addresses assigned to the ports provided by the driver. If not provided > + a randomly generated MAC address will be used. > + > + ethernet-ports: > + type: object > + properties: > + '#address-cells': > + const: 1 > + '#size-cells': > + const: 0 > + > + patternProperties: > + "^port@[0-9]+$": Unit-addresses are hex. > + type: object > + description: Switch ports > + > + allOf: > + - $ref: ethernet-controller.yaml# > + > + properties: > + reg: > + description: Switch port number > + > + bandwidth: Needs a vendor prefix. > + maxItems: 1 Not an array. Drop. > + $ref: /schemas/types.yaml#definitions/uint32 > + description: Specifies bandwidth in Mbit/s allocated to the port. 0-2^32 allowed? > + > + phys: > + maxItems: 1 > + description: > + phandle of a Ethernet SerDes PHY. This defines which SerDes > + instance will handle the Ethernet traffic. > + > + phy-handle: > + maxItems: 1 Always a single item. (Note phys is not, so that's correct.) > + description: > + phandle of a Ethernet PHY. This is optional and if provided it > + points to the cuPHY used by the Ethernet SerDes. > + > + phy-mode: > + maxItems: 1 Not an array. Drop. I'd assume it's some subset of modes? > + description: > + This specifies the interface used by the Ethernet SerDes towards the > + phy or SFP. > + > + sfp: > + maxItems: 1 'sfp' is already defined as a single item. Drop > + description: > + phandle of an SFP. This is optional and used when not specifying > + a cuPHY. It points to the SFP node that describes the SFP used by > + the Ethernet SerDes. > + > + managed: > + maxItems: 1 > + description: > + SFP management. This must be provided when specifying an SFP. 'managed: true' is sufficient. It's already described in ethernet-controller.yaml and the schema expresses the 2nd sentence. > + > + sd_sgpio: Vendor specific? Then needs a vendor prefix. s/_/-/ > + $ref: /schemas/types.yaml#/definitions/uint32 > + maxItems: 1 A uint32 is always 1 item. Drop. > + description: > + Index of the ports Signal Detect SGPIO in the set of 384 SGPIOs > + This is optional, and only needed if the default used index is > + is not correct. Sounds like constraints?: minimum: 0 maximum: 383 > + > + required: > + - reg > + - bandwidth > + - phys > + - phy-mode > + > + oneOf: > + - required: > + - phy-handle > + - required: > + - sfp > + - managed > + > + additionalProperties: false > + > +required: > + - compatible > + - reg > + - reg-names > + - interrupts > + - ethernet-ports > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + switch: switch@600000000 { > + compatible = "microchip,sparx5-switch"; > + reg = <0x10000000 0x800000>, > + <0x11010000 0x1b00000>; > + reg-names = "devices", "gcb"; > + > + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; > + ethernet-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port0: port@0 { > + reg = <0>; > + bandwidth = <1000>; > + phys = <&serdes 13>; > + phy-handle = <&phy0>; > + phy-mode = "qsgmii"; > + }; > + /* ... */ > + /* Then the 25G interfaces */ > + port60: port@60 { > + reg = <60>; > + bandwidth = <25000>; > + phys = <&serdes 29>; > + phy-mode = "10gbase-r"; > + sfp = <&sfp_eth60>; > + managed = "in-band-status"; > + }; > + port61: port@61 { > + reg = <61>; > + bandwidth = <25000>; > + phys = <&serdes 30>; > + phy-mode = "10gbase-r"; > + sfp = <&sfp_eth61>; > + managed = "in-band-status"; > + }; > + port62: port@62 { > + reg = <62>; > + bandwidth = <25000>; > + phys = <&serdes 31>; > + phy-mode = "10gbase-r"; > + sfp = <&sfp_eth62>; > + managed = "in-band-status"; > + }; > + port63: port@63 { > + reg = <63>; > + bandwidth = <25000>; > + phys = <&serdes 32>; > + phy-mode = "10gbase-r"; > + sfp = <&sfp_eth63>; > + managed = "in-band-status"; > + }; > + /* Finally the Management interface */ > + port64: port@64 { > + reg = <64>; > + bandwidth = <1000>; > + phys = <&serdes 0>; > + phy-handle = <&phy64>; > + phy-mode = "sgmii"; > + }; > + }; > + }; > + > +... > -- > 2.29.2 >
This series provides the Microchip Sparx5 Switch Driver The Sparx5 Carrier Ethernet and Industrial switch family delivers 64 Ethernet ports and up to 200 Gbps of switching bandwidth. It provides a rich set of Ethernet switching features such as hierarchical QoS, hardware-based OAM and service activation testing, protection switching, IEEE 1588, and Synchronous Ethernet. Using provider bridging (Q-in-Q) and MPLS/MPLS-TP technology, it delivers MEF CE 2.0 Ethernet virtual connections (EVCs) and features advanced TCAM classification in both ingress and egress. Per-EVC features include advanced L3-aware classification, a rich set of statistics, OAM for end-to-end performance monitoring, and dual-rate policing and shaping. Time sensitive networking (TSN) is supported through a comprehensive set of features including frame preemption, cut-through, frame replication and elimination for reliability, enhanced scheduling: credit-based shaping, time-aware shaping, cyclic queuing, and forwarding, and per-stream policing and filtering. Together with IEEE 1588 and IEEE 802.1AS support, this guarantees low-latency deterministic networking for Fronthaul, Carrier, and Industrial Ethernet. The Sparx5 switch family consists of following SKUs: - VSC7546 Sparx5-64 up to 64 Gbps of bandwidth with the following primary port configurations: - 6 *10G - 16 * 2.5G + 2 * 10G - 24 * 1G + 4 * 10G - VSC7549 Sparx5-90 up to 90 Gbps of bandwidth with the following primary port configurations: - 9 * 10G - 16 * 2.5G + 4 * 10G - 48 * 1G + 4 * 10G - VSC7552 Sparx5-128 up to 128 Gbps of bandwidth with the following primary port configurations: - 12 * 10G - 16 * 2.5G + 8 * 10G - 48 * 1G + 8 * 10G - VSC7556 Sparx5-160 up to 160 Gbps of bandwidth with the following primary port configurations: - 16 * 10G - 10 * 10G + 2 * 25G - 16 * 2.5G + 10 * 10G - 48 * 1G + 10 * 10G - VSC7558 Sparx5-200 up to 200 Gbps of bandwidth with the following primary port configurations: - 20 * 10G - 8 * 25G In addition, the device supports one 10/100/1000/2500/5000 Mbps SGMII/SerDes node processor interface (NPI) Ethernet port. The Sparx5 support is developed on the PCB134 and PCB135 evaluation boards. - PCB134 main networking features: - 12x SFP+ front 10G module slots (connected to Sparx5 through SFI). - 8x SFP28 front 25G module slots (connected to Sparx5 through SFI high speed). - Optional, one additional 10/100/1000BASE-T (RJ45) Ethernet port (on-board VSC8211 PHY connected to Sparx5 through SGMII). - PCB135 main networking features: - 48x1G (10/100/1000M) RJ45 front ports using 12xVSC8514 QuadPHY’s each connected to VSC7558 through QSGMII. - 4x10G (1G/2.5G/5G/10G) RJ45 front ports using the AQR407 10G QuadPHY each port connects to VSC7558 through SFI. - 4x SFP28 25G module slots on back connected to VSC7558 through SFI high speed. - Optional, one additional 1G (10/100/1000M) RJ45 port using an on-board VSC8211 PHY, which can be connected to VSC7558 NPI port through SGMII using a loopback add-on PCB) This series provides support for: - SFPs and DAC cables via PHYLINK with a number of 5G, 10G and 25G devices and media types. - Port module configuration for 10M to 25G speeds with SGMII, QSGMII, 1000BASEX, 2500BASEX and 10GBASER as appropriate for these modes. - SerDes configuration via the Sparx5 SerDes driver (see below). - Host mode providing register based injection and extraction. - Switch mode providing MAC/VLAN table learning and Layer2 switching offloaded to the Sparx5 switch. - STP state, VLAN support, host/bridge port mode, Forwarding DB, and configuration and statistics via ethtool. More support will be added at a later stage. The Sparx5 Switch chip register model can be browsed here: Link: https://microchip-ung.github.io/sparx-5_reginfo/reginfo_sparx-5.html The series depends on the following series currently on their way into the kernel: - Sparx5 SerDes Driver Link: https://lore.kernel.org/r/20201211090541.157926-1-steen.hegelund@microchip.com/ - Sparx5 Reset Driver Link: https://lore.kernel.org/lkml/20210114162432.3039657-1-steen.hegelund@microchip.com/ The 100 Base-X mode is being added to the kernel with this series: Link: https://lore.kernel.org/netdev/20210113115626.17381-1-bjarni.jonasson@microchip.com/ ChangeLog: v3: - Updated the bindings with - adding maxItems: 1 to the port properties in general. - mac-address property added - sd-gpio property added - phy-mode is now required - Main module - Reworked the driver probe to have 3 stages: - Initalization, DT parsing and creating SerDes instances - Mapping IO targets - Creating ports using DT information and further switch initialization. - Wrapped long lines to fit to 80 chars (netdev style) - Reworking the switch RAM initialization - Made the target table const - Return -EINVAL if no coreclock was found. - Applied the Reverse Christmas Tree pattern to several functions - Changes to DT properties: - max-speed changed to bandwidth - phy-mode is required - Removed the reset postcore_initcall code (will be provided in a reset driver, see link above) - Requesting the reset driver and using that for resetting the switch core. - Using a bool (has_sfp) to determine if an SFP is available for the particular port and removing the sparx5_use_cu_phy function. - For the basic driver patch: added comments to indicate where subsequent patches will be adding more functionality. - Netdev module - Increment Ethernet addresses correctly. - Removed ether_setup() call. - Packet module - Used error codes instead of -1. - Phylink module - Include autoneg and pause when detecting port config changes - Port module - Added decode_* status functions - Removed the preliminary 100fx functionality. There is phylink support on the way for 100 Base-X (see link above), so when that is available the 100fx mode will be added again. - Made the taxi dist table constant - Using named symbols in autoneg decoding - MAC table module - Removed inline from functions. - Changed the default aging to BR_DEFAULT_AGEING_TIME - Ethtool module - Removed the mutex. Copy statistic on request. Updating time is 1s. - Device tree - Added reset controller properties - Common - Remove the inclusion of the sparx5_main_regs.h in the sparx5_main.h v2: - The driver patch has been split into 6 patches by functionality like this: - the basic sparx5 driver - hostmode with phylink support - port module support - switching, vlan and mactable support - calendar bandwidth allocation support - ethtool configuration and statistics support - IO ranges have been collapsed into just 2 (the SerDes driver uses the area inbetween) and the driver uses an offset table to get the target instances. - register macros have been converted to functions - register_netdev() moved to the end of the switch initialization. - sparx5_update_port_stats: use reverse christmas tree - sparx5_get_sset_strings: copy individual strings - sparx5_port_open: updated to better use phylink: just call phylink_of_phy_connect directly - sparx5_destroy_netdev: always take the NL lock - sparx5_attr_stp_state_set: added learning state. - sparx5_phylink_mac_config: use phylink to provide the status for the devices phylink controls. - sparx5_get_1000basex_status: renamed to sparx5_get_dev2g5_status and corrected an error when combining the sync and link status information. - let phylink provide link status for cuPHYs and SFPs - corrected the pause mode status handling - use ethtool's get_link function directly - remove the use of the phy_validate function - sparx5_update_counter function: no longer inline - Removed the wrapper functions around the mactable mutex Steen Hegelund (8): dt-bindings: net: sparx5: Add sparx5-switch bindings net: sparx5: add the basic sparx5 driver net: sparx5: add hostmode with phylink support net: sparx5: add port module support net: sparx5: add switching, vlan and mactable support net: sparx5: add calendar bandwidth allocation support net: sparx5: add ethtool configuration and statistics support arm64: dts: sparx5: Add the Sparx5 switch node .../bindings/net/microchip,sparx5-switch.yaml | 211 + arch/arm64/boot/dts/microchip/sparx5.dtsi | 62 + .../dts/microchip/sparx5_pcb134_board.dtsi | 444 +- .../dts/microchip/sparx5_pcb135_board.dtsi | 606 ++- drivers/net/ethernet/microchip/Kconfig | 2 + drivers/net/ethernet/microchip/Makefile | 2 + drivers/net/ethernet/microchip/sparx5/Kconfig | 9 + .../net/ethernet/microchip/sparx5/Makefile | 11 + .../microchip/sparx5/sparx5_calendar.c | 596 +++ .../microchip/sparx5/sparx5_ethtool.c | 969 ++++ .../microchip/sparx5/sparx5_mactable.c | 500 +++ .../ethernet/microchip/sparx5/sparx5_main.c | 851 ++++ .../ethernet/microchip/sparx5/sparx5_main.h | 358 ++ .../microchip/sparx5/sparx5_main_regs.h | 3922 +++++++++++++++++ .../ethernet/microchip/sparx5/sparx5_netdev.c | 247 ++ .../ethernet/microchip/sparx5/sparx5_packet.c | 283 ++ .../microchip/sparx5/sparx5_phylink.c | 195 + .../ethernet/microchip/sparx5/sparx5_port.c | 1123 +++++ .../ethernet/microchip/sparx5/sparx5_port.h | 98 + .../microchip/sparx5/sparx5_switchdev.c | 517 +++ .../ethernet/microchip/sparx5/sparx5_vlan.c | 224 + 21 files changed, 11170 insertions(+), 60 deletions(-) create mode 100644 Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml create mode 100644 drivers/net/ethernet/microchip/sparx5/Kconfig create mode 100644 drivers/net/ethernet/microchip/sparx5/Makefile create mode 100644 drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c create mode 100644 drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c create mode 100644 drivers/net/ethernet/microchip/sparx5/sparx5_mactable.c create mode 100644 drivers/net/ethernet/microchip/sparx5/sparx5_main.c create mode 100644 drivers/net/ethernet/microchip/sparx5/sparx5_main.h create mode 100644 drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h create mode 100644 drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c create mode 100644 drivers/net/ethernet/microchip/sparx5/sparx5_packet.c create mode 100644 drivers/net/ethernet/microchip/sparx5/sparx5_phylink.c create mode 100644 drivers/net/ethernet/microchip/sparx5/sparx5_port.c create mode 100644 drivers/net/ethernet/microchip/sparx5/sparx5_port.h create mode 100644 drivers/net/ethernet/microchip/sparx5/sparx5_switchdev.c create mode 100644 drivers/net/ethernet/microchip/sparx5/sparx5_vlan.c -- 2.29.2