From patchwork Thu Mar 25 17:39:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Voon, Weifeng" X-Patchwork-Id: 409300 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32BB7C433DB for ; Thu, 25 Mar 2021 17:40:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0AF9561A28 for ; Thu, 25 Mar 2021 17:40:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229592AbhCYRjo (ORCPT ); Thu, 25 Mar 2021 13:39:44 -0400 Received: from mga03.intel.com ([134.134.136.65]:27389 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230115AbhCYRjV (ORCPT ); Thu, 25 Mar 2021 13:39:21 -0400 IronPort-SDR: eCMT3yTW2EGZfcHUZ2cznwuD39V1r3Wv8rWYBODxCpbcZsPd8dLMaJUQBDcigvG3+HOb4pWxD+ oOH07vNPzr7g== X-IronPort-AV: E=McAfee;i="6000,8403,9934"; a="191016762" X-IronPort-AV: E=Sophos;i="5.81,278,1610438400"; d="scan'208";a="191016762" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Mar 2021 10:39:20 -0700 IronPort-SDR: 0TVUNNIh1zGMOZkz9T8MOMTbvezKxkBGMPrRwvQYfSYl3crsztv7KNCfOsmDbicfxRs66uxUql uPdv8m+t/djg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,278,1610438400"; d="scan'208";a="416112200" Received: from climb.png.intel.com ([10.221.118.165]) by orsmga008.jf.intel.com with ESMTP; 25 Mar 2021 10:39:16 -0700 From: Voon Weifeng To: "David S . Miller" , Maxime Coquelin Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Jose Abreu , Jakub Kicinski , Giuseppe Cavallaro , Andrew Lunn , Alexandre Torgue , linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Ong Boon Leong , Voon Weifeng , Wong Vee Khee Subject: [PATCH v2 net-next 0/5] net: stmmac: enable multi-vector MSI Date: Fri, 26 Mar 2021 01:39:11 +0800 Message-Id: <20210325173916.13203-1-weifeng.voon@intel.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This patchset adds support for multi MSI interrupts in addition to current single common interrupt implementation. Each MSI interrupt is tied to a newly introduce interrupt service routine(ISR). Hence, each interrupt will only go through the corresponding ISR. In order to increase the efficiency, enabling multi MSI interrupt will automatically select the interrupt mode configuration INTM=1. When INTM=1, the TX/RX transfer complete signal will only asserted on corresponding sbd_perch_tx_intr_o[] or sbd_perch_rx_intr_o[] without asserting signal on the common sbd_intr_o. Hence, for each TX/RX interrupts, only the corresponding ISR will be triggered. Every vendor might have different MSI vector assignment. So, this patchset only includes multi-vector MSI assignment for Intel platform. Changes: v1 -> v2 patch 2/5 -Remove defensive check for invalid dev pointer patch 3/5 - Refactor out a huge if statement into separate subfunctions. - Removed the netdev_info for every successful request of IRQs. - Return 0 for each successful request of IRQs. patch 4/5 - Moved the msi tx/rx base vector check before alloc irq - Restuctured the clean up code after fail to alloc irq and fail to probe - Unprepared and unregistered the stmmac-clk if fail to alloc irq patch 5/5 -Moved the readl and writel into the if statement as it is only executed when multi msi is enabled Ong Boon Leong (4): net: stmmac: introduce DMA interrupt status masking per traffic direction net: stmmac: make stmmac_interrupt() function more friendly to MSI net: stmmac: introduce MSI Interrupt routines for mac, safety, RX & TX stmmac: intel: add support for multi-vector msi and msi-x Wong, Vee Khee (1): net: stmmac: use interrupt mode INTM=1 for multi-MSI drivers/net/ethernet/stmicro/stmmac/common.h | 21 + .../net/ethernet/stmicro/stmmac/dwmac-intel.c | 120 ++++- .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 24 +- .../net/ethernet/stmicro/stmmac/dwmac4_dma.c | 7 + .../net/ethernet/stmicro/stmmac/dwmac4_dma.h | 24 +- .../net/ethernet/stmicro/stmmac/dwmac4_lib.c | 30 +- .../net/ethernet/stmicro/stmmac/dwmac_dma.h | 22 +- .../net/ethernet/stmicro/stmmac/dwmac_lib.c | 8 +- .../net/ethernet/stmicro/stmmac/dwxgmac2.h | 6 + .../ethernet/stmicro/stmmac/dwxgmac2_dma.c | 8 +- drivers/net/ethernet/stmicro/stmmac/hwif.h | 2 +- drivers/net/ethernet/stmicro/stmmac/stmmac.h | 16 + .../net/ethernet/stmicro/stmmac/stmmac_main.c | 499 +++++++++++++++--- include/linux/stmmac.h | 9 + 14 files changed, 697 insertions(+), 99 deletions(-)