From patchwork Sat Feb 6 16:45:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Chulski X-Patchwork-Id: 377919 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7F88BC433E0 for ; Sat, 6 Feb 2021 16:49:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4FB1964E81 for ; Sat, 6 Feb 2021 16:49:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230475AbhBFQs5 (ORCPT ); Sat, 6 Feb 2021 11:48:57 -0500 Received: from mx0a-0016f401.pphosted.com ([67.231.148.174]:30408 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S230439AbhBFQsM (ORCPT ); Sat, 6 Feb 2021 11:48:12 -0500 Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 116Gj2qi021859; Sat, 6 Feb 2021 08:47:24 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=6pDdBO4FiW4J3ZSh6Q2cfqQ4yvjsrELQlYlAuzrXKH0=; b=Mxxmg3AmZHB97AwEZvkBQI+614WwSEx1vXK08n8fYIQdW9aqGgqXM+bAf7ELJ5fcHLtf 0hPkVxli+y7ChRUCxjqmEfRxXZOoqgjiVUz4OjY0Tp2m0yUoxzkrskzUPO0z6G29bO97 +C+R9glTEmQGxe8/VGt9Z4DYCIHrxdUNomoqWq6oEYcfj3yu3JS01dsmKlofv4L62fi9 g7fQObwYvdh9clR79jpnRvMUQHasVjzfawOyNFFyOOjdVXX+5SkXOl9mwNTKW2Ua6iY/ 6FtpTdNLF/l6cslwJCNnzNkOeHbvdj6CBFMZFsBDlNRk16YqFwYoxnpsTMKKxVcWLWK7 xw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 36hsbr8gve-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sat, 06 Feb 2021 08:47:24 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 6 Feb 2021 08:47:22 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 6 Feb 2021 08:47:22 -0800 Received: from stefan-pc.marvell.com (stefan-pc.marvell.com [10.5.25.21]) by maili.marvell.com (Postfix) with ESMTP id EE6043F703F; Sat, 6 Feb 2021 08:47:19 -0800 (PST) From: To: CC: , , , , , , , , , , , Subject: [PATCH v8 net-next 07/15] net: mvpp2: add FCA periodic timer configurations Date: Sat, 6 Feb 2021 18:45:53 +0200 Message-ID: <1612629961-11583-8-git-send-email-stefanc@marvell.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1612629961-11583-1-git-send-email-stefanc@marvell.com> References: <1612629961-11583-1-git-send-email-stefanc@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.737 definitions=2021-02-06_06:2021-02-05,2021-02-06 signatures=0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Stefan Chulski Flow Control periodic timer would be used if port in XOFF to transmit periodic XOFF frames. Signed-off-by: Stefan Chulski --- drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 13 +++++- drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 45 ++++++++++++++++++++ 2 files changed, 57 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h index cac9885..73f087c 100644 --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h @@ -596,6 +596,15 @@ #define MVPP22_MPCS_CLK_RESET_DIV_RATIO(n) ((n) << 4) #define MVPP22_MPCS_CLK_RESET_DIV_SET BIT(11) +/* FCA registers. PPv2.2 and PPv2.3 */ +#define MVPP22_FCA_BASE(port) (0x7600 + (port) * 0x1000) +#define MVPP22_FCA_REG_SIZE 16 +#define MVPP22_FCA_REG_MASK 0xFFFF +#define MVPP22_FCA_CONTROL_REG 0x0 +#define MVPP22_FCA_ENABLE_PERIODIC BIT(11) +#define MVPP22_PERIODIC_COUNTER_LSB_REG (0x110) +#define MVPP22_PERIODIC_COUNTER_MSB_REG (0x114) + /* XPCS registers. PPv2.2 and PPv2.3 */ #define MVPP22_XPCS_BASE(port) (0x7400 + (port) * 0x1000) #define MVPP22_XPCS_CFG0 0x0 @@ -752,7 +761,9 @@ ((kb) * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN) /* MSS Flow control */ -#define MSS_SRAM_SIZE 0x800 +#define MSS_SRAM_SIZE 0x800 +#define FC_QUANTA 0xFFFF +#define FC_CLK_DIVIDER 100 /* RX buffer constants */ #define MVPP2_SKB_SHINFO_SIZE \ diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c index d80947a..6e59d07 100644 --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c @@ -1281,6 +1281,49 @@ static void mvpp22_gop_init_10gkr(struct mvpp2_port *port) writel(val, mpcs + MVPP22_MPCS_CLK_RESET); } +static void mvpp22_gop_fca_enable_periodic(struct mvpp2_port *port, bool en) +{ + struct mvpp2 *priv = port->priv; + void __iomem *fca = priv->iface_base + MVPP22_FCA_BASE(port->gop_id); + u32 val; + + val = readl(fca + MVPP22_FCA_CONTROL_REG); + val &= ~MVPP22_FCA_ENABLE_PERIODIC; + if (en) + val |= MVPP22_FCA_ENABLE_PERIODIC; + writel(val, fca + MVPP22_FCA_CONTROL_REG); +} + +static void mvpp22_gop_fca_set_timer(struct mvpp2_port *port, u32 timer) +{ + struct mvpp2 *priv = port->priv; + void __iomem *fca = priv->iface_base + MVPP22_FCA_BASE(port->gop_id); + u32 lsb, msb; + + lsb = timer & MVPP22_FCA_REG_MASK; + msb = timer >> MVPP22_FCA_REG_SIZE; + + writel(lsb, fca + MVPP22_PERIODIC_COUNTER_LSB_REG); + writel(msb, fca + MVPP22_PERIODIC_COUNTER_MSB_REG); +} + +/* Set Flow Control timer x100 faster than pause quanta to ensure that link + * partner won't send traffic if port is in XOFF mode. + */ +static void mvpp22_gop_fca_set_periodic_timer(struct mvpp2_port *port) +{ + u32 timer; + + timer = (port->priv->tclk / (USEC_PER_SEC * FC_CLK_DIVIDER)) + * FC_QUANTA; + + mvpp22_gop_fca_enable_periodic(port, false); + + mvpp22_gop_fca_set_timer(port, timer); + + mvpp22_gop_fca_enable_periodic(port, true); +} + static int mvpp22_gop_init(struct mvpp2_port *port) { struct mvpp2 *priv = port->priv; @@ -1325,6 +1368,8 @@ static int mvpp22_gop_init(struct mvpp2_port *port) val |= GENCONF_SOFT_RESET1_GOP; regmap_write(priv->sysctrl_base, GENCONF_SOFT_RESET1, val); + mvpp22_gop_fca_set_periodic_timer(port); + unsupported_conf: return 0;