From patchwork Thu Jun 18 21:10:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Murphy X-Patchwork-Id: 191152 Delivered-To: patch@linaro.org Received: by 2002:a92:cf06:0:0:0:0:0 with SMTP id c6csp1787384ilo; Thu, 18 Jun 2020 14:10:57 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwozEEji4ppdw7DvhQsKxH4WmE1JQPSsfvmwdlY1bEgyEgY4SEeDiQubVHTea0QCQRMrfrv X-Received: by 2002:a17:906:b293:: with SMTP id q19mr629918ejz.412.1592514657382; Thu, 18 Jun 2020 14:10:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1592514657; cv=none; d=google.com; s=arc-20160816; b=FEvD/YXJoJRCR2Ayqjvd205/akK9Qf/O2dhyXJpPW4hJWhMW9njlg4Te94bnAC3Q7a PYbXMFdXUOaI0pVNwuhLKBYsAimdqwhTucES2Mq6GHGhF5Ex3W5EOWTmpWk9dg/v7StA 3E7wbx9HVUYvMmn+gsAQv11ROedRxCArCnPUazyrmtgCH01LwgN1daAC58W6wDaBEaC8 mgAhv19iJ+Ie+LyT/39WGbtTzu3MH/EIETuvHVCbCLdJ9KVOAef4PugQ1Mj66mrk3NyQ 410/AuoTaozIUr3DNeSIpXCPcIGtTK8kiranCG0MFvM8YPWH0CmI6vxTD+HRkoXXgjPc xyRg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ehq+Ty1gZ2t4R0aAfzFJjltOQ0z7TJBMi3aVsQVQchg=; b=IfEmKCJn+5hovfVX1+QrXNhr4kI8iDeDOSbTi5QpWH5hTr2lJdYyomh98REpp50J7D wagLex8QWQSk+P15j3xfxebSikmd5cATHhwjgO6oIxJf5Ba8QMHWnWcJoRQt0be6v1me JFOLloFOVQw1mDJugqajJBzihmuXn6xJhwA3atPoTN2RdleJk+kHYv1VbiIIDwBzdcoX y6x7fTXdzc2UpwLMEzOUWs2Rtpxltdqk8b6JtCISom623gAhGxUa51XVk8407bHra6w0 XYlzJUSNkFz06jQmBLHgSWbr3LeD1v7qGnFQ1W8mMPiSOKW6bi30S9j/MC+ZzF9Y+zbZ 2rGg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="opI/u/XV"; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id ar22si2387435ejc.434.2020.06.18.14.10.57; Thu, 18 Jun 2020 14:10:57 -0700 (PDT) Received-SPF: pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="opI/u/XV"; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731288AbgFRVKz (ORCPT + 9 others); Thu, 18 Jun 2020 17:10:55 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:57058 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730989AbgFRVKs (ORCPT ); Thu, 18 Jun 2020 17:10:48 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 05ILAh43036218; Thu, 18 Jun 2020 16:10:43 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1592514643; bh=ehq+Ty1gZ2t4R0aAfzFJjltOQ0z7TJBMi3aVsQVQchg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=opI/u/XVls5qmauY8k3rC4TzC+lQsGCbqkcL55OjFbLaMI5VFm0heUj5WIyJjLZM+ ylY+iYoz9W6kr6oxkcB/Gp15EhsWejlPcX+hPMgW/3U2KHOC+RCt+tWmS8l0rHEvXr eIfB7PrmNSGMO1YAR4U7gINWilqGOrJxrmvmmBBg= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 05ILAhSQ084551; Thu, 18 Jun 2020 16:10:43 -0500 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 18 Jun 2020 16:10:43 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 18 Jun 2020 16:10:43 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 05ILAhgF015270; Thu, 18 Jun 2020 16:10:43 -0500 From: Dan Murphy To: , , , , CC: , , , Dan Murphy Subject: [PATCH net-next v8 5/5] net: phy: DP83822: Add setting the fixed internal delay Date: Thu, 18 Jun 2020 16:10:11 -0500 Message-ID: <20200618211011.28837-6-dmurphy@ti.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200618211011.28837-1-dmurphy@ti.com> References: <20200618211011.28837-1-dmurphy@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The DP83822 can be configured to use the RGMII interface. There are independent fixed 3.5ns clock shift (aka internal delay) for the TX and RX paths. This allow either one to be set if the MII interface is RGMII and the value is set in the firmware node. Signed-off-by: Dan Murphy --- drivers/net/phy/dp83822.c | 78 ++++++++++++++++++++++++++++++++++----- 1 file changed, 68 insertions(+), 10 deletions(-) -- 2.26.2 Reported-by: kernel test robot diff --git a/drivers/net/phy/dp83822.c b/drivers/net/phy/dp83822.c index 1dd19d0cb269..0fe91119d57f 100644 --- a/drivers/net/phy/dp83822.c +++ b/drivers/net/phy/dp83822.c @@ -26,7 +26,9 @@ #define MII_DP83822_PHYSCR 0x11 #define MII_DP83822_MISR1 0x12 #define MII_DP83822_MISR2 0x13 +#define MII_DP83822_RCSR 0x17 #define MII_DP83822_RESET_CTRL 0x1f +#define MII_DP83822_GENCFG 0x465 #define DP83822_HW_RESET BIT(15) #define DP83822_SW_RESET BIT(14) @@ -77,6 +79,10 @@ #define DP83822_WOL_INDICATION_SEL BIT(8) #define DP83822_WOL_CLR_INDICATION BIT(11) +/* RSCR bits */ +#define DP83822_RX_CLK_SHIFT BIT(12) +#define DP83822_TX_CLK_SHIFT BIT(11) + static int dp83822_ack_interrupt(struct phy_device *phydev) { int err; @@ -255,7 +261,7 @@ static int dp83822_config_intr(struct phy_device *phydev) return phy_write(phydev, MII_DP83822_PHYSCR, physcr_status); } -static int dp83822_config_init(struct phy_device *phydev) +static int dp8382x_disable_wol(struct phy_device *phydev) { int value = DP83822_WOL_EN | DP83822_WOL_MAGIC_EN | DP83822_WOL_SECURE_ON; @@ -264,6 +270,45 @@ static int dp83822_config_init(struct phy_device *phydev) MII_DP83822_WOL_CFG, value); } +static int dp83822_config_init(struct phy_device *phydev) +{ + struct device *dev = &phydev->mdio.dev; + int rgmii_delay; + s32 rx_int_delay; + s32 tx_int_delay; + int err = 0; + + if (phy_interface_is_rgmii(phydev)) { + rx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0, + true); + if (rx_int_delay <= 0) + rx_int_delay = 0; + else + rgmii_delay = DP83822_RX_CLK_SHIFT; + + tx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0, + false); + if (tx_int_delay <= 0) + tx_int_delay = 0; + else + rgmii_delay |= DP83822_TX_CLK_SHIFT; + + if (rgmii_delay) { + err = phy_set_bits_mmd(phydev, DP83822_DEVADDR, + MII_DP83822_RCSR, rgmii_delay); + if (err) + return err; + } + } + + return dp8382x_disable_wol(phydev); +} + +static int dp8382x_config_init(struct phy_device *phydev) +{ + return dp8382x_disable_wol(phydev); +} + static int dp83822_phy_reset(struct phy_device *phydev) { int err; @@ -272,9 +317,7 @@ static int dp83822_phy_reset(struct phy_device *phydev) if (err < 0) return err; - dp83822_config_init(phydev); - - return 0; + return phydev->drv->config_init(phydev); } static int dp83822_suspend(struct phy_device *phydev) @@ -318,14 +361,29 @@ static int dp83822_resume(struct phy_device *phydev) .resume = dp83822_resume, \ } +#define DP8382X_PHY_DRIVER(_id, _name) \ + { \ + PHY_ID_MATCH_MODEL(_id), \ + .name = (_name), \ + /* PHY_BASIC_FEATURES */ \ + .soft_reset = dp83822_phy_reset, \ + .config_init = dp8382x_config_init, \ + .get_wol = dp83822_get_wol, \ + .set_wol = dp83822_set_wol, \ + .ack_interrupt = dp83822_ack_interrupt, \ + .config_intr = dp83822_config_intr, \ + .suspend = dp83822_suspend, \ + .resume = dp83822_resume, \ + } + static struct phy_driver dp83822_driver[] = { DP83822_PHY_DRIVER(DP83822_PHY_ID, "TI DP83822"), - DP83822_PHY_DRIVER(DP83825I_PHY_ID, "TI DP83825I"), - DP83822_PHY_DRIVER(DP83826C_PHY_ID, "TI DP83826C"), - DP83822_PHY_DRIVER(DP83826NC_PHY_ID, "TI DP83826NC"), - DP83822_PHY_DRIVER(DP83825S_PHY_ID, "TI DP83825S"), - DP83822_PHY_DRIVER(DP83825CM_PHY_ID, "TI DP83825M"), - DP83822_PHY_DRIVER(DP83825CS_PHY_ID, "TI DP83825CS"), + DP8382X_PHY_DRIVER(DP83825I_PHY_ID, "TI DP83825I"), + DP8382X_PHY_DRIVER(DP83826C_PHY_ID, "TI DP83826C"), + DP8382X_PHY_DRIVER(DP83826NC_PHY_ID, "TI DP83826NC"), + DP8382X_PHY_DRIVER(DP83825S_PHY_ID, "TI DP83825S"), + DP8382X_PHY_DRIVER(DP83825CM_PHY_ID, "TI DP83825M"), + DP8382X_PHY_DRIVER(DP83825CS_PHY_ID, "TI DP83825CS"), }; module_phy_driver(dp83822_driver);