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[23.128.96.18]) by mx.google.com with ESMTP id du22si14633319ejc.330.2020.06.23.06.48.57; Tue, 23 Jun 2020 06:48:57 -0700 (PDT) Received-SPF: pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=cUXgPSfu; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732755AbgFWNs4 (ORCPT + 9 others); Tue, 23 Jun 2020 09:48:56 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:55218 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732743AbgFWNsx (ORCPT ); Tue, 23 Jun 2020 09:48:53 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 05NDmlkk110142; Tue, 23 Jun 2020 08:48:47 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1592920127; bh=NjHRGQyuPawgk7rsFcYQJon3wpp+3lTd1hxMTCsjXxs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=cUXgPSfucGEb1HraXngmB22wBe+dSyqQKUoy7g/Tbet8Gl5wF+lSSJxpzKvbWFRZW ZuihmQnSAoxv8kQxWbkBMJGzs1MaxqifxYE+yJ4EI9EK4jdxoKMrZVlhlDu67wO4YV /zVRYBwhli2zfS9bhg1PVW1I/y4NVKbAEAj9BegY= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 05NDmlTx013813 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 23 Jun 2020 08:48:47 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 23 Jun 2020 08:48:47 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 23 Jun 2020 08:48:47 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 05NDmlm8093493; Tue, 23 Jun 2020 08:48:47 -0500 From: Dan Murphy To: , , , , CC: , , , Dan Murphy Subject: [PATCH net-next v10 1/5] dt-bindings: net: Add tx and rx internal delays Date: Tue, 23 Jun 2020 08:48:32 -0500 Message-ID: <20200623134836.21981-2-dmurphy@ti.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200623134836.21981-1-dmurphy@ti.com> References: <20200623134836.21981-1-dmurphy@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org tx-internal-delays and rx-internal-delays are a common setting for RGMII capable devices. These properties are used when the phy-mode or phy-controller is set to rgmii-id, rgmii-rxid or rgmii-txid. These modes indicate to the controller that the PHY will add the internal delay for the connection. Signed-off-by: Dan Murphy --- .../devicetree/bindings/net/ethernet-phy.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) -- 2.26.2 diff --git a/Documentation/devicetree/bindings/net/ethernet-phy.yaml b/Documentation/devicetree/bindings/net/ethernet-phy.yaml index 9b1f1147ca36..a9e547ac7905 100644 --- a/Documentation/devicetree/bindings/net/ethernet-phy.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-phy.yaml @@ -162,6 +162,18 @@ properties: description: Specifies a reference to a node representing a SFP cage. + rx-internal-delay-ps: + description: | + RGMII Receive PHY Clock Delay defined in pico seconds. This is used for + PHY's that have configurable RX internal delays. If this property is + present then the PHY applies the RX delay. + + tx-internal-delay-ps: + description: | + RGMII Transmit PHY Clock Delay defined in pico seconds. This is used for + PHY's that have configurable TX internal delays. If this property is + present then the PHY applies the TX delay. + required: - reg