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[93.35.189.2]) by smtp.googlemail.com with ESMTPSA id t4sm3408635edd.6.2021.04.22.18.48.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 18:48:08 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 11/14] drivers: net: dsa: qca8k: apply switch revision fix Date: Fri, 23 Apr 2021 03:47:37 +0200 Message-Id: <20210423014741.11858-12-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210423014741.11858-1-ansuelsmth@gmail.com> References: <20210423014741.11858-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org qca8k require special debug value based on the switch revision. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 193c269d8ed3..12d2c97d1417 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -909,7 +909,7 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, { const struct qca8k_match_data *data; struct qca8k_priv *priv = ds->priv; - u32 reg, val; + u32 phy, reg, val; /* get the switches ID from the compatible */ data = of_device_get_match_data(priv->dev); @@ -928,7 +928,26 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, case 3: case 4: case 5: - /* Internal PHY, nothing to do */ + /* Internal PHY, apply revision fixup */ + phy = qca8k_port_to_phy(port) % PHY_MAX_ADDR; + switch (priv->switch_revision) { + case 1: + /* For 100M waveform */ + qca8k_phy_dbg_write(priv, phy, 0, 0x02ea); + /* Turn on Gigabit clock */ + qca8k_phy_dbg_write(priv, phy, 0x3d, 0x68a0); + break; + + case 2: + qca8k_phy_mmd_write(priv, phy, 0x7, 0x3c, 0x0); + fallthrough; + case 4: + qca8k_phy_mmd_write(priv, phy, 0x3, 0x800d, 0x803f); + qca8k_phy_dbg_write(priv, phy, 0x3d, 0x6860); + qca8k_phy_dbg_write(priv, phy, 0x5, 0x2c46); + qca8k_phy_dbg_write(priv, phy, 0x3c, 0x6000); + break; + } return; case 6: /* 2nd CPU port / external PHY */ if (state->interface != PHY_INTERFACE_MODE_RGMII &&