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Fri, 9 Jul 2021 07:54:00 +0000 From: Joakim Zhang To: davem@davemloft.net, kuba@kernel.org, robh+dt@kernel.org, andrew@lunn.ch Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-imx@nxp.com Subject: [PATCH V1 1/5] dt-bindings: fec: add the missing clocks properties Date: Fri, 9 Jul 2021 15:53:51 +0800 Message-Id: <20210709075355.27218-2-qiangqing.zhang@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210709075355.27218-1-qiangqing.zhang@nxp.com> References: <20210709075355.27218-1-qiangqing.zhang@nxp.com> X-ClientProxiedBy: SG2PR06CA0147.apcprd06.prod.outlook.com (2603:1096:1:1f::25) To DB8PR04MB6795.eurprd04.prod.outlook.com (2603:10a6:10:fa::15) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.71) by SG2PR06CA0147.apcprd06.prod.outlook.com (2603:1096:1:1f::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4308.19 via Frontend Transport; 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Signed-off-by: Fugang Duan Signed-off-by: Joakim Zhang --- Documentation/devicetree/bindings/net/fsl-fec.txt | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/net/fsl-fec.txt b/Documentation/devicetree/bindings/net/fsl-fec.txt index 9b543789cd52..6754be1b91c4 100644 --- a/Documentation/devicetree/bindings/net/fsl-fec.txt +++ b/Documentation/devicetree/bindings/net/fsl-fec.txt @@ -39,6 +39,17 @@ Optional properties: tx/rx queues 1 and 2. "int0" will be used for queue 0 and ENET_MII interrupts. For imx6sx, "int0" handles all 3 queues and ENET_MII. "pps" is for the pulse per second interrupt associated with 1588 precision time protocol(PTP). +- clocks: Phandles to input clocks. +- clock-name: Should be the names of the clocks + - "ipg", for MAC ipg_clk_s, ipg_clk_mac_s that are for register accessing. + - "ahb", for MAC ipg_clk, ipg_clk_mac that are bus clock. + - "ptp"(option), for IEEE1588 timer clock that requires the clock. + - "enet_clk_ref"(option), for MAC transmit/receiver reference clock like + RGMII TXC clock or RMII reference clock. It depends on board design, + the clock is required if RGMII TXC and RMII reference clock source from + SOC internal PLL. + - "enet_out"(option), output clock for external device, like supply clock + for PHY. The clock is required if PHY clock source from SOC. Optional subnodes: - mdio : specifies the mdio bus in the FEC, used as a container for phy nodes