From patchwork Mon Jul 22 21:39:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 169449 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp8012520ilk; Mon, 22 Jul 2019 14:41:34 -0700 (PDT) X-Google-Smtp-Source: APXvYqwEms3XhL24fd4yZ3G0e0GNFqCCCMdQ2Up5ddv7exljb3dbpbUkfgkyiHOsuHljXfd+SVXe X-Received: by 2002:a02:ac03:: with SMTP id a3mr77581276jao.132.1563831693961; Mon, 22 Jul 2019 14:41:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1563831693; cv=none; d=google.com; s=arc-20160816; b=F5WqSzHrAfQXBJzHCLt/ylqxYO+lSd9RGt70bU6+P2Oad97lcSJQUjl9yP0cCBCyea mRtslWzfmYnEdV9wbwMSIRu+Y8YFiMtNfv2jP/Cny929Ccy8vZgEsY3OPabDyZxE6EcI H05HGgsWEf+t2Pu+idWPfMGG/3EnPBTiMKLWGz9iEwOMvktfpEGBRi1jl9g7G2EZJcEg 8JHu/e1niWvo0p6hpv5s1mzf0938MqpaNwX2V3OVwW+qzD029xaKB2CHfEXzlvMcYRdt e7zLy1NrB22Tk0sCiwZ7OAOM8S7f5rjvxeqdiCKDLPLrkGswRIAo8XFRpQbnuk/AvPov 7gTA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:message-id:date:to:from; bh=IEU1yaAOuhkeE/LAzZixKOOifJiOsJItPqvKROPIL1I=; b=zSDUwmddfL4Qqglt79jMEGS5TScppEd0Q9eszAbeP7eRvKMqs8lJeyViDNtUVpfnc3 1afymICg2HF2cgmyq9jeGBNGDIJkss+S+azu597zzaxfcGJvV/gThb/wd/OpMlXOuYDm s3ZJwtkUTOzOhNa0/MRbGhdxRazKcVoTinDMEhwMCrccuhs1hbvF4PVIAX89QVfHVs/M JQtiuLh3gzi5tp6QQFyc7gWpbu5azveAYh4IGnFqWhex/YQtWPzlsrafKqHEhSjdR0DB yVL1pGAxYMw5Dk6KUz+ZKey+Hhc6d+X93f6FGhDqZE9fukBSkHq6l2JcORCP6oymr8Vf s2Xg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id c129si60768290iof.100.2019.07.22.14.41.33 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 22 Jul 2019 14:41:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hpg2T-0002Pt-5z; Mon, 22 Jul 2019 21:40:09 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hpg2R-0002MS-Km for xen-devel@lists.xenproject.org; Mon, 22 Jul 2019 21:40:07 +0000 X-Inumbo-ID: 451f2d58-acc9-11e9-8980-bc764e045a96 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 451f2d58-acc9-11e9-8980-bc764e045a96; Mon, 22 Jul 2019 21:40:06 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B53C2344; Mon, 22 Jul 2019 14:40:05 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 07EB33F71F; Mon, 22 Jul 2019 14:40:04 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Mon, 22 Jul 2019 22:39:23 +0100 Message-Id: <20190722213958.5761-1-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 Subject: [Xen-devel] [PATCH v2 00/35] xen/arm: Rework head.S to make it more compliant with the Arm Arm X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , Stefano Stabellini , Volodymyr Babchuk MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Hi all, This is part of the boot/memory rework for Xen on Arm, but not sent as MM-PARTx as this is focusing on the boot code. Similar to the memory code, the boot code is not following the Arm Arm and could lead to memory corruption/TLB conflict abort. I am not aware of any platforms where Xen fails to boot, yet it should be fixed sooner rather than later. While making the code more compliant, I have also took the opportunity to simplify the boot and also add more documentation. After this series, the boot CPU and secondary CPUs path is mostly compliant with the Arm Arm. The only non-compliant places I am aware of are: 1) create_page_tables: Some rework is necessary to update the page-tables safely without the MMU on. 2) The switches between boot and runtime page-tables (for both boot CPU and secondary CPUs) are not safe. 3) The 1:1 mapping should only use page granularity mapping to avoid mapping memory that should not be accessed All will be addressed in follow-up series. The boot code would also benefits another proof read for missing isb()/dsb(). The arm32 code has been aded in this version but so far lightly tested. For convenience I provided a branch based on staging: git://xenbits.xen.org/people/julieng/xen-unstable.git branch boot/v2 Cheers, Julien Grall (35): xen/arm64: macros: Introduce an assembly macro to alias x30 xen/arm64: head: Mark the end of subroutines with ENDPROC xen/arm64: head: Don't clobber x30/lr in the macro PRINT xen/arm64: head: Rework UART initialization on boot CPU xen/arm64: head: Introduce print_reg xen/arm64: head: Introduce distinct paths for the boot CPU and secondary CPUs xen/arm64: head: Rework and document check_cpu_mode() xen/arm64: head: Rework and document zero_bss() xen/arm64: head: Improve coding style and document cpu_init() xen/arm64: head: Improve coding style and document create_pages_tables() xen/arm64: head: Document enable_mmu() xen/arm64: head: Move assembly switch to the runtime PT in secondary CPUs path xen/arm64: head: Don't setup the fixmap on secondary CPUs xen/arm64: head: Remove 1:1 mapping as soon as it is not used xen/arm64: head: Rework and document setup_fixmap() xen/arm64: head: Rework and document launch() xen/arm64: head: Setup TTBR_EL2 in enable_mmu() and add missing isb xen/arm64: head: Introduce a macro to get a PC-relative address of a symbol xen/arm32: head: Add a macro to move an immediate constant into a 32-bit register xen/arm32: head: Mark the end of subroutines with ENDPROC xen/arm32: head: Don't clobber r14/lr in the macro PRINT xen/arm32: head: Rework UART initialization on boot CPU xen/arm32: head: Introduce print_reg xen/arm32: head: Introduce distinct paths for the boot CPU and secondary CPUs xen/arm32: head: Rework and document check_cpu_mode() xen/arm32: head: Rework and document zero_bss() xen/arm32: head: Document create_pages_tables() xen/arm32: head: Document enable_mmu() xen/arm32: head: Move assembly switch to the runtime PT in secondary CPUs path xen/arm32: head: Don't setup the fixmap on secondary CPUs xen/arm32: head: Remove 1:1 mapping as soon as it is not used xen/arm32: head: Rework and document setup_fixmap() xen/arm32: head: Rework and document launch() xen/arm32: head: Setup HTTBR in enable_mmu() and add missing isb xen/arm: Zero BSS after the MMU and D-cache is turned on xen/arch/arm/arm32/head.S | 393 +++++++++++++++++++++++---------- xen/arch/arm/arm64/entry.S | 5 - xen/arch/arm/arm64/head.S | 432 +++++++++++++++++++++++++++---------- xen/arch/arm/mm.c | 23 +- xen/include/asm-arm/arm64/macros.h | 5 + 5 files changed, 619 insertions(+), 239 deletions(-)