From patchwork Wed Mar 2 07:34:37 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shannon Zhao X-Patchwork-Id: 63371 Delivered-To: patch@linaro.org Received: by 10.112.199.169 with SMTP id jl9csp2242314lbc; Tue, 1 Mar 2016 23:37:42 -0800 (PST) X-Received: by 10.140.101.5 with SMTP id t5mr31961593qge.24.1456904253473; Tue, 01 Mar 2016 23:37:33 -0800 (PST) Return-Path: Received: from lists.xen.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id q141si34828308qha.77.2016.03.01.23.37.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 01 Mar 2016 23:37:33 -0800 (PST) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.84) (envelope-from ) id 1ab1KN-0004r7-Sk; Wed, 02 Mar 2016 07:36:11 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.84) (envelope-from ) id 1ab1KM-0004qb-On for xen-devel@lists.xen.org; Wed, 02 Mar 2016 07:36:10 +0000 Received: from [193.109.254.147] by server-11.bemta-14.messagelabs.com id 39/1D-02989-AE796D65; Wed, 02 Mar 2016 07:36:10 +0000 X-Env-Sender: zhaoshenglong@huawei.com X-Msg-Ref: server-12.tower-27.messagelabs.com!1456904165!27960080!1 X-Originating-IP: [119.145.14.66] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogMTE5LjE0NS4xNC42NiA9PiA4NTI3\n X-StarScan-Received: X-StarScan-Version: 8.11; banners=-,-,- X-VirusChecked: Checked Received: (qmail 47613 invoked from network); 2 Mar 2016 07:36:08 -0000 Received: from szxga03-in.huawei.com (HELO szxga03-in.huawei.com) (119.145.14.66) by server-12.tower-27.messagelabs.com with RC4-SHA encrypted SMTP; 2 Mar 2016 07:36:08 -0000 Received: from 172.24.1.47 (EHLO SZXEML424-HUB.china.huawei.com) ([172.24.1.47]) by szxrg03-dlp.huawei.com (MOS 4.4.3-GA FastPath queued) with ESMTP id BXB04009; Wed, 02 Mar 2016 15:35:41 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by SZXEML424-HUB.china.huawei.com (10.82.67.153) with Microsoft SMTP Server id 14.3.235.1; Wed, 2 Mar 2016 15:35:21 +0800 From: Shannon Zhao To: Date: Wed, 2 Mar 2016 15:34:37 +0800 Message-ID: <1456904083-13168-12-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1456904083-13168-1-git-send-email-zhaoshenglong@huawei.com> References: <1456904083-13168-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020206.56D697CE.0032, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-05-26 15:14:31, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: e6c46d7f73eef46bc9b0f69bebe2aa6a Cc: zhaoshenglong@huawei.com, stefano.stabellini@citrix.com, ian.campbell@citrix.com, shannon.zhao@linaro.org Subject: [Xen-devel] [PATCH v8 11/17] arm/gic-v3: Add ACPI boot support for GICv3 X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" From: Shannon Zhao Like GICv2, ACPI on Xen hypervisor uses MADT table for proper GICv3 initialization. Parse GIC distributor subtable, redistributor subtable and interrupt subtable. Signed-off-by: Shannon Zhao Reviewed-by: Stefano Stabellini --- xen/arch/arm/gic-v3.c | 171 +++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 170 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index a42577b..f83fd88 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -34,6 +34,8 @@ #include #include #include +#include +#include #include #include #include @@ -41,6 +43,7 @@ #include #include #include +#include /* Global state */ static struct { @@ -1232,6 +1235,153 @@ static void __init gicv3_dt_init(void) &vbase, &vsize); } +#ifdef CONFIG_ACPI +static int __init +gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header, + const unsigned long end) +{ + static int cpu_base_assigned = 0; + struct acpi_madt_generic_interrupt *processor = + container_of(header, struct acpi_madt_generic_interrupt, header); + + if ( BAD_MADT_ENTRY(processor, end) ) + return -EINVAL; + + /* Read from APIC table and fill up the GIC variables */ + if ( !cpu_base_assigned ) + { + cbase = processor->base_address; + csize = SZ_8K; + vbase = processor->gicv_base_address; + gicv3_info.maintenance_irq = processor->vgic_interrupt; + + if ( processor->flags & ACPI_MADT_VGIC_IRQ_MODE ) + irq_set_type(gicv3_info.maintenance_irq, IRQ_TYPE_EDGE_BOTH); + else + irq_set_type(gicv3_info.maintenance_irq, IRQ_TYPE_LEVEL_MASK); + + cpu_base_assigned = 1; + } + else + { + if ( cbase != processor->base_address + || vbase != processor->gicv_base_address + || gicv3_info.maintenance_irq != processor->vgic_interrupt ) + { + printk("GICv3: GICC entries are not same in MADT table\n"); + return -EINVAL; + } + } + + return 0; +} + +static int __init +gic_acpi_parse_madt_distributor(struct acpi_subtable_header *header, + const unsigned long end) +{ + struct acpi_madt_generic_distributor *dist = + container_of(header, struct acpi_madt_generic_distributor, header); + + if ( BAD_MADT_ENTRY(dist, end) ) + return -EINVAL; + + dbase = dist->base_address; + + return 0; +} +static int __init +gic_acpi_get_madt_redistributor_num(struct acpi_subtable_header *header, + const unsigned long end) +{ + /* Nothing to do here since it only wants to get the number of GIC + * redistributors. + */ + return 0; +} + +static void __init gicv3_acpi_init(void) +{ + struct acpi_table_header *table; + struct rdist_region *rdist_regs; + acpi_status status; + int count, i; + + status = acpi_get_table(ACPI_SIG_MADT, 0, &table); + + if ( ACPI_FAILURE(status) ) + { + const char *msg = acpi_format_exception(status); + + panic("GICv3: Failed to get MADT table, %s", msg); + } + + /* + * Find distributor base address. We expect one distributor entry since + * ACPI 5.0 spec neither support multi-GIC instances nor GIC cascade. + */ + count = acpi_parse_entries(ACPI_SIG_MADT, sizeof(struct acpi_table_madt), + gic_acpi_parse_madt_distributor, table, + ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 0); + + if ( count <= 0 ) + panic("GICv3: No valid GICD entries exists"); + + if ( (dbase & ~PAGE_MASK) ) + panic("GICv3: Found unaligned distributor address %"PRIpaddr"", + dbase); + + /* Get number of redistributor */ + count = acpi_parse_entries(ACPI_SIG_MADT, sizeof(struct acpi_table_madt), + gic_acpi_get_madt_redistributor_num, table, + ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 0); + if ( count <= 0 ) + panic("GICv3: No valid GICR entries exists"); + + gicv3.rdist_count = count; + + if ( gicv3.rdist_count > MAX_RDIST_COUNT ) + panic("GICv3: Number of redistributor regions is more than" + "%d (Increase MAX_RDIST_COUNT!!)\n", MAX_RDIST_COUNT); + + rdist_regs = xzalloc_array(struct rdist_region, gicv3.rdist_count); + if ( !rdist_regs ) + panic("GICv3: Failed to allocate memory for rdist regions\n"); + + for ( i = 0; i < gicv3.rdist_count; i++ ) + { + struct acpi_subtable_header *header; + struct acpi_madt_generic_redistributor *gic_rdist; + + header = acpi_table_get_entry_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, + i); + if ( !header ) + panic("GICv3: Can't get GICR entry"); + + gic_rdist = + container_of(header, struct acpi_madt_generic_redistributor, header); + rdist_regs[i].base = gic_rdist->base_address; + rdist_regs[i].size = gic_rdist->length; + } + + /* The vGIC code requires the region to be sorted */ + sort(rdist_regs, gicv3.rdist_count, sizeof(*rdist_regs), cmp_rdist, NULL); + + gicv3.rdist_regions= rdist_regs; + + /* Collect CPU base addresses */ + count = acpi_parse_entries(ACPI_SIG_MADT, sizeof(struct acpi_table_madt), + gic_acpi_parse_madt_cpu, table, + ACPI_MADT_TYPE_GENERIC_INTERRUPT, 0); + if ( count <= 0 ) + panic("GICv3: No valid GICC entries exists"); + + gicv3.rdist_stride = 0; +} +#else +static void __init gicv3_acpi_init(void) { } +#endif + /* Set up the GIC */ static int __init gicv3_init(void) { @@ -1244,7 +1394,10 @@ static int __init gicv3_init(void) return -ENODEV; } - gicv3_dt_init(); + if ( acpi_disabled ) + gicv3_dt_init(); + else + gicv3_acpi_init(); gicv3.map_dbase = ioremap_nocache(dbase, SZ_64K); if ( !gicv3.map_dbase ) @@ -1344,6 +1497,22 @@ DT_DEVICE_START(gicv3, "GICv3", DEVICE_GIC) .init = gicv3_dt_preinit, DT_DEVICE_END +#ifdef CONFIG_ACPI +/* Set up the GIC */ +static int __init gicv3_acpi_preinit(const void *data) +{ + gicv3_info.hw_version = GIC_V3; + register_gic_ops(&gicv3_ops); + + return 0; +} + +ACPI_DEVICE_START(agicv3, "GICv3", DEVICE_GIC) + .class_type = ACPI_MADT_GIC_VERSION_V3, + .init = gicv3_acpi_preinit, +ACPI_DEVICE_END +#endif + /* * Local variables: * mode: C