From patchwork Fri Mar 4 06:15:46 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shannon Zhao X-Patchwork-Id: 63525 Delivered-To: patch@linaro.org Received: by 10.112.199.169 with SMTP id jl9csp292674lbc; Thu, 3 Mar 2016 22:21:42 -0800 (PST) X-Received: by 10.140.35.115 with SMTP id m106mr7944990qgm.13.1457072502073; Thu, 03 Mar 2016 22:21:42 -0800 (PST) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id l10si2340420qgf.61.2016.03.03.22.21.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Mar 2016 22:21:42 -0800 (PST) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xen.org with esmtp (Exim 4.84) (envelope-from ) id 1abj6I-0007Dv-Sv; Fri, 04 Mar 2016 06:20:34 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.84) (envelope-from ) id 1abj6H-0007C8-Co for xen-devel@lists.xen.org; Fri, 04 Mar 2016 06:20:33 +0000 Received: from [85.158.137.68] by server-16.bemta-3.messagelabs.com id E4/C0-02994-03929D65; Fri, 04 Mar 2016 06:20:32 +0000 X-Env-Sender: zhaoshenglong@huawei.com X-Msg-Ref: server-6.tower-31.messagelabs.com!1457072426!599130!1 X-Originating-IP: [58.251.152.64] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 8.11; banners=-,-,- X-VirusChecked: Checked Received: (qmail 27732 invoked from network); 4 Mar 2016 06:20:31 -0000 Received: from szxga01-in.huawei.com (HELO szxga01-in.huawei.com) (58.251.152.64) by server-6.tower-31.messagelabs.com with RC4-SHA encrypted SMTP; 4 Mar 2016 06:20:31 -0000 Received: from 172.24.1.49 (EHLO szxeml428-hub.china.huawei.com) ([172.24.1.49]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DFX12109; Fri, 04 Mar 2016 14:17:06 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by szxeml428-hub.china.huawei.com (10.82.67.183) with Microsoft SMTP Server id 14.3.235.1; Fri, 4 Mar 2016 14:16:34 +0800 From: Shannon Zhao To: Date: Fri, 4 Mar 2016 14:15:46 +0800 Message-ID: <1457072152-16128-17-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1457072152-16128-1-git-send-email-zhaoshenglong@huawei.com> References: <1457072152-16128-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020205.56D92863.00C7, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: c92a5002190c4ad6412890db10ceb12f Cc: hangaohuai@huawei.com, stefano.stabellini@citrix.com, shannon.zhao@linaro.org, zhaoshenglong@huawei.com Subject: [Xen-devel] [PATCH v5 16/22] arm/acpi: Configure SPI interrupt type and route to Dom0 dynamically X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" From: Shannon Zhao Interrupt information is described in DSDT and is not available at the time of booting. Check if the interrupt is permitted to access and set the interrupt type, route it to guest dynamically only for SPI and Dom0. Signed-off-by: Parth Dixit Signed-off-by: Shannon Zhao --- v5: add a small function to get the irq type from ICFG --- xen/arch/arm/vgic.c | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index ee35683..52378a3 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -25,6 +25,8 @@ #include #include #include +#include +#include #include @@ -334,6 +336,21 @@ void vgic_disable_irqs(struct vcpu *v, uint32_t r, int n) } } +#ifdef CONFIG_ACPI +#define VGIC_ICFG_MASK(intr) ( 1 << ( ( 2 * ( intr % 16 ) ) + 1 ) ) + +static unsigned int get_the_irq_type(struct vcpu *v, int n, int index) +{ + struct vgic_irq_rank *vr = vgic_get_rank(v, n); + uint32_t tr = vr->icfg[index >> 4]; + + if ( tr & VGIC_ICFG_MASK(index) ) + return IRQ_TYPE_EDGE_BOTH; + else + return IRQ_TYPE_LEVEL_MASK; +} +#endif + void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n) { const unsigned long mask = r; @@ -342,9 +359,30 @@ void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n) unsigned long flags; int i = 0; struct vcpu *v_target; +#ifdef CONFIG_ACPI + struct domain *d = v->domain; + int ret; +#endif while ( (i = find_next_bit(&mask, 32, i)) < 32 ) { irq = i + (32 * n); +#ifdef CONFIG_ACPI + /* Set the irq type and route it to guest only for SPI and Dom0 */ + if( irq_access_permitted(d, irq) && is_hardware_domain(d) && + ( irq >= 32 ) && ( !acpi_disabled ) ) + { + ret = irq_set_spi_type(irq, get_the_irq_type(v, n, i)); + if ( ret ) + printk(XENLOG_WARNING "The irq type is not correct\n"); + + vgic_reserve_virq(d, irq); + + ret = route_irq_to_guest(d, irq, irq, NULL); + if ( ret ) + printk(XENLOG_ERR "Unable to route IRQ %u to domain %u\n", + irq, d->domain_id); + } +#endif v_target = __vgic_get_target_vcpu(v, irq); p = irq_to_pending(v_target, irq); set_bit(GIC_IRQ_GUEST_ENABLED, &p->status);