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[192.237.175.120]) by mx.google.com with ESMTPS id w129si6377827qka.233.2016.05.05.09.35.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 05 May 2016 09:35:47 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ayMEa-0001jT-EY; Thu, 05 May 2016 16:34:40 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ayMEZ-0001ht-7F for xen-devel@lists.xen.org; Thu, 05 May 2016 16:34:39 +0000 Received: from [193.109.254.147] by server-2.bemta-14.messagelabs.com id C9/61-03279-E167B275; Thu, 05 May 2016 16:34:38 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrOLMWRWlGSWpSXmKPExsVysyfVTVe2TDv c4Od3I4slHxezODB6HN39mymAMYo1My8pvyKBNeNZwwSWgkmCFW+u/mduYPzP28XIxSEksJFR 4uvZr0wQzmlGidatk1m6GDk52AQ0Je58/sQEYosISEtc+3yZEaSIWaCZUWL6otdsIAlhgSCJS /s2gtksAqoSX8/0sIPYvAIuEpP3TAaLSwjISZw8NpkVxOYUcJVYen4l2AIhoJqTOyaxTWDkXs DIsIpRvTi1qCy1SNdUL6koMz2jJDcxM0fX0NBELze1uDgxPTUnMalYLzk/dxMj0MMMQLCDcd1 i50OMkhxMSqK825W0w4X4kvJTKjMSizPii0pzUosPMcpwcChJ8MqVAuUEi1LTUyvSMnOAoQaT luDgURLhlQBJ8xYXJOYWZ6ZDpE4xKkqJ8yqAJARAEhmleXBtsPC+xCgrJczLCHSIEE9BalFuZ gmq/CtGcQ5GJWHeFJApPJl5JXDTXwEtZgJa/H6uJsjikkSElFQDY8tH0+rqfWkLux4ULFsgXc my1MJ0ToOVvX7P/OKUR9Kv4j4VtzNWzd9ibbCWdedDvUNW9fN6NhReKNkanX3SMm3/U3b7Ms8 Jy+8fdXUPmSEiZNKitqfijnpqalueyNEbfxoO6l9eeTN+7wHXS06h17g2+1olvFyzdety/1Dx nqX83g9Xpu37rcRSnJFoqMVcVJwIADjeoMRqAgAA X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-14.tower-27.messagelabs.com!1462466077!27615605!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 8.34; banners=-,-,- X-VirusChecked: Checked Received: (qmail 40344 invoked from network); 5 May 2016 16:34:37 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-14.tower-27.messagelabs.com with SMTP; 5 May 2016 16:34:37 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 71EAC3A; Thu, 5 May 2016 09:34:44 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.215.28]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B8B0C3F252; Thu, 5 May 2016 09:34:35 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 5 May 2016 17:34:13 +0100 Message-Id: <1462466065-30212-5-git-send-email-julien.grall@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1462466065-30212-1-git-send-email-julien.grall@arm.com> References: <1462466065-30212-1-git-send-email-julien.grall@arm.com> Cc: andre.przywara@arm.com, Julien Grall , sstabellini@kernel.org, wei.chen@arm.com, steve.capper@arm.com Subject: [Xen-devel] [RFC 04/16] xen/arm: arm64: Import flush_icache_range from Linux v4.6-rc3 X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" Flushing the icache will required when the support Xen patching will be added. Also import the macro icache_line_size which is used by flush_icache_range. Signed-off-by: Julien Grall --- xen/arch/arm/arm64/cache.S | 45 +++++++++++++++++++++++++++++++++++++++++++++ xen/include/asm-arm/page.h | 2 ++ 2 files changed, 47 insertions(+) diff --git a/xen/arch/arm/arm64/cache.S b/xen/arch/arm/arm64/cache.S index eff4e16..bc5a8f7 100644 --- a/xen/arch/arm/arm64/cache.S +++ b/xen/arch/arm/arm64/cache.S @@ -30,6 +30,51 @@ .endm /* + * icache_line_size - get the minimum I-cache line size from the CTR register. + */ + .macro icache_line_size, reg, tmp + mrs \tmp, ctr_el0 // read CTR + and \tmp, \tmp, #0xf // cache line size encoding + mov \reg, #4 // bytes per word + lsl \reg, \reg, \tmp // actual cache line size + .endm + +/* + * flush_icache_range(start,end) + * + * Ensure that the I and D caches are coherent within specified region. + * This is typically used when code has been written to a memory region, + * and will be executed. + * + * - start - virtual start address of region + * - end - virtual end address of region + */ +ENTRY(flush_icache_range) + dcache_line_size x2, x3 + sub x3, x2, #1 + bic x4, x0, x3 +1: + dc cvau, x4 // clean D line to PoU + add x4, x4, x2 + cmp x4, x1 + b.lo 1b + dsb ish + + icache_line_size x2, x3 + sub x3, x2, #1 + bic x4, x0, x3 +1: + ic ivau, x4 // invalidate I line PoU + add x4, x4, x2 + cmp x4, x1 + b.lo 1b + dsb ish + isb + mov x0, #0 + ret +ENDPROC(flush_icache_range) + +/* * __flush_dcache_area(kaddr, size) * * Ensure that the data held in the page kaddr is written back to the diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h index 05d9f82..a94e826 100644 --- a/xen/include/asm-arm/page.h +++ b/xen/include/asm-arm/page.h @@ -328,6 +328,8 @@ static inline int clean_and_invalidate_dcache_va_range return 0; } +int flush_icache_range(unsigned long start, unsigned long end); + /* Macros for flushing a single small item. The predicate is always * compile-time constant so this will compile down to 3 instructions in * the common case. */