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[192.237.175.120]) by mx.google.com with ESMTPS id s202si4804062vkb.70.2016.06.22.04.17.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 22 Jun 2016 04:17:37 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bFg8F-0002F3-Tc; Wed, 22 Jun 2016 11:15:43 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bFg8E-0002Dv-BB for xen-devel@lists.xen.org; Wed, 22 Jun 2016 11:15:42 +0000 Received: from [85.158.139.211] by server-10.bemta-5.messagelabs.com id 46/6C-12215-D537A675; Wed, 22 Jun 2016 11:15:41 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrGLMWRWlGSWpSXmKPExsVysyfVTTe2OCv c4FE/j8WSj4tZHBg9ju7+zRTAGMWamZeUX5HAmtG96A1LwVGRioNNMg2M7/i7GLk4hAQ2MUq8 bm5mhHBOM0q8avrB0sXIycEmoClx5/MnJhBbREBa4trny4wgNrOAg8Sbj/fAaoSB7CmbtoLFW QRUJdb2rwWr5xVwkTjefhssLiEgJ3Hy2GRWEJtTwFXi5NHJYHEhoJrbB/awTmDkXsDIsIpRoz i1qCy1SNfIRC+pKDM9oyQ3MTNH19DAVC83tbg4MT01JzGpWC85P3cTI9C/9QwMjDsYb072O8Q oycGkJMorr5wVLsSXlJ9SmZFYnBFfVJqTWnyIUYaDQ0mC93k+UE6wKDU9tSItMwcYaDBpCQ4e JRHe1yBp3uKCxNzizHSI1ClGRSlxXtMCoIQASCKjNA+uDRbclxhlpYR5GRkYGIR4ClKLcjNLU OVfMYpzMCoJ85qATOHJzCuBm/4KaDET0OJl/ekgi0sSEVJSDYxpVn6XYwOCW1tS7DsOF89wSl 1YmG+pwz978eIchkmR+oc0FjlNuFS3vMDMVWjCbhZt9uJp+93EdspyXTr5b/2sz6E/TO7P23e vbdpXWxuzreUFh/hss9InhescLs9ML7vP+0U7JGtrUdCDsM3sS3a3tHv8OLr1ouKPbu8KNqFt v5VaH+17dEqJpTgj0VCLuag4EQBbNg3EaQIAAA== X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-11.tower-206.messagelabs.com!1466594140!33942864!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests=UPPERCASE_25_50 X-StarScan-Received: X-StarScan-Version: 8.46; banners=-,-,- X-VirusChecked: Checked Received: (qmail 42833 invoked from network); 22 Jun 2016 11:15:41 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-11.tower-206.messagelabs.com with SMTP; 22 Jun 2016 11:15:41 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 640F83B0; Wed, 22 Jun 2016 04:16:27 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.215.28]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C91513F213; Wed, 22 Jun 2016 04:15:39 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Wed, 22 Jun 2016 12:15:18 +0100 Message-Id: <1466594130-19251-4-git-send-email-julien.grall@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1466594130-19251-1-git-send-email-julien.grall@arm.com> References: <1466594130-19251-1-git-send-email-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH v4 03/15] xen/arm: Add macros to handle the MIDR X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" Add new macros to easily get different parts of the register and to check if a given MIDR match a CPU model range. The latter will be really useful to handle errata later. The macros have been imported from the header arch/arm64/include/asm/cputype.h in Linux v4.6-rc3. Also remove MIDR_MASK which is unused. Signed-off-by: Julien Grall Acked-by: Stefano Stabellini --- Changes in v2: - Add Stefano's acked-by --- xen/include/asm-arm/processor.h | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index 284ad6a..dba9b9a 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -9,7 +9,40 @@ #include /* MIDR Main ID Register */ -#define MIDR_MASK 0xff0ffff0 +#define MIDR_REVISION_MASK 0xf +#define MIDR_RESIVION(midr) ((midr) & MIDR_REVISION_MASK) +#define MIDR_PARTNUM_SHIFT 4 +#define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT) +#define MIDR_PARTNUM(midr) \ + (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT) +#define MIDR_ARCHITECTURE_SHIFT 16 +#define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT) +#define MIDR_ARCHITECTURE(midr) \ + (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT) +#define MIDR_VARIANT_SHIFT 20 +#define MIDR_VARIANT_MASK (0xf << MIDR_VARIANT_SHIFT) +#define MIDR_VARIANT(midr) \ + (((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT) +#define MIDR_IMPLEMENTOR_SHIFT 24 +#define MIDR_IMPLEMENTOR_MASK (0xff << MIDR_IMPLEMENTOR_SHIFT) +#define MIDR_IMPLEMENTOR(midr) \ + (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT) + +#define MIDR_CPU_MODEL(imp, partnum) \ + (((imp) << MIDR_IMPLEMENTOR_SHIFT) | \ + (0xf << MIDR_ARCHITECTURE_SHIFT) | \ + ((partnum) << MIDR_PARTNUM_SHIFT)) + +#define MIDR_CPU_MODEL_MASK \ + (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | MIDR_ARCHITECTURE_MASK) + +#define MIDR_IS_CPU_MODEL_RANGE(midr, model, rv_min, rv_max) \ +({ \ + u32 _model = (midr) & MIDR_CPU_MODEL_MASK; \ + u32 _rv = (midr) & (MIDR_REVISION_MASK | MIDR_VARIANT_MASK); \ + \ + _model == (model) && _rv >= (rv_min) && _rv <= (rv_max); \ +}) /* MPIDR Multiprocessor Affinity Register */ #define _MPIDR_UP (30)