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[73.67.244.238]) by smtp.gmail.com with ESMTPSA id q127sm3200756pfb.34.2016.06.23.20.08.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 23 Jun 2016 20:08:24 -0700 (PDT) From: John Stultz To: Guodong Xu , Xinliang Liu Cc: John Stultz Subject: [PATCH 4/6] drm: kirin: Sync with kirin drm driver Date: Thu, 23 Jun 2016 20:08:07 -0700 Message-Id: <1466737689-2303-5-git-send-email-john.stultz@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1466737689-2303-1-git-send-email-john.stultz@linaro.org> References: <1466737689-2303-1-git-send-email-john.stultz@linaro.org> MIME-Version: 1.0 This patch syncs the now moved hisi driver with the upstream kirin driver backport from Guodong's rebase tree. This provides binding documentation as well as device-tree changes, which allow for features like HDMI hotplug support as well as DSI panel support. Credit for the hisilicon/kirin driver we're syncing with goes to Xinliang Liu who authored most of the code. Signed-off-by: John Stultz --- .../bindings/display/hisilicon/dw-dsi.txt | 72 ++ .../bindings/display/hisilicon/hisi-ade.txt | 68 +- .../bindings/display/hisilicon/hisi-drm.txt | 66 -- .../bindings/display/hisilicon/hisi-dsi.txt | 53 -- MAINTAINERS | 10 + arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 58 +- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 87 +- drivers/gpu/drm/Makefile | 2 +- drivers/gpu/drm/hisilicon/Kconfig | 10 - drivers/gpu/drm/hisilicon/kirin/Kconfig | 1 + drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c | 929 +++++++++++++++------ drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h | 158 ++-- drivers/gpu/drm/hisilicon/kirin/hisi_drm_ade.h | 16 - drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h | 512 +++--------- drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c | 803 +++++++++--------- drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c | 255 ++++-- drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h | 23 +- include/drm/drm_mipi_dsi.h | 27 + 18 files changed, 1743 insertions(+), 1407 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/hisilicon/dw-dsi.txt delete mode 100644 Documentation/devicetree/bindings/display/hisilicon/hisi-drm.txt delete mode 100644 Documentation/devicetree/bindings/display/hisilicon/hisi-dsi.txt delete mode 100644 drivers/gpu/drm/hisilicon/kirin/hisi_drm_ade.h -- 1.9.1 diff --git a/Documentation/devicetree/bindings/display/hisilicon/dw-dsi.txt b/Documentation/devicetree/bindings/display/hisilicon/dw-dsi.txt new file mode 100644 index 0000000..d270bfe --- /dev/null +++ b/Documentation/devicetree/bindings/display/hisilicon/dw-dsi.txt @@ -0,0 +1,72 @@ +Device-Tree bindings for DesignWare DSI Host Controller v1.20a driver + +A DSI Host Controller resides in the middle of display controller and external +HDMI converter or panel. + +Required properties: +- compatible: value should be "hisilicon,hi6220-dsi". +- reg: physical base address and length of dsi controller's registers. +- clocks: contains APB clock phandle + clock-specifier pair. +- clock-names: should be "pclk". +- ports: contains DSI controller input and output sub port. + The input port connects to ADE output port with the reg value "0". + The output port with the reg value "1", it could connect to panel or + any other bridge endpoints. + See Documentation/devicetree/bindings/graph.txt for more device graph info. + +A example of HiKey board hi6220 SoC and board specific DT entry: +Example: + +SoC specific: + dsi: dsi@f4107800 { + compatible = "hisilicon,hi6220-dsi"; + reg = <0x0 0xf4107800 0x0 0x100>; + clocks = <&media_ctrl HI6220_DSI_PCLK>; + clock-names = "pclk"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* 0 for input port */ + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <&ade_out>; + }; + }; + }; + }; + + +Board specific: + &dsi { + status = "ok"; + + ports { + /* 1 for output port */ + port@1 { + reg = <1>; + + dsi_out0: endpoint@0 { + remote-endpoint = <&adv7533_in>; + }; + }; + }; + }; + + &i2c2 { + ... + + adv7533: adv7533@39 { + ... + + port { + adv7533_in: endpoint { + remote-endpoint = <&dsi_out0>; + }; + }; + }; + }; + diff --git a/Documentation/devicetree/bindings/display/hisilicon/hisi-ade.txt b/Documentation/devicetree/bindings/display/hisilicon/hisi-ade.txt index 2777a2c..38dc9d6 100644 --- a/Documentation/devicetree/bindings/display/hisilicon/hisi-ade.txt +++ b/Documentation/devicetree/bindings/display/hisilicon/hisi-ade.txt @@ -5,15 +5,31 @@ data from memory, do composition, do post image processing, generate RGB timing stream and transfer to DSI. Required properties: -- compatible: value should be one of the following - "hisilicon,hi6220-ade". -- reg: physical base address and length of the controller's registers. -- reg-names: name of physical base. -- interrupt: the interrupt number. -- clocks: the clocks needed. -- clock-names: the name of the clocks. -- ade_core_clk_rate: ADE core clock rate. -- media_noc_clk_rate: media noc module clock rate. +- compatible: value should be "hisilicon,hi6220-ade". +- reg: physical base address and length of the ADE controller's registers. +- hisilicon,noc-syscon: ADE NOC QoS syscon. +- resets: The ADE reset controller node. +- interrupt: the ldi vblank interrupt number used. +- clocks: a list of phandle + clock-specifier pairs, one for each entry + in clock-names. +- clock-names: should contain: + "clk_ade_core" for the ADE core clock. + "clk_codec_jpeg" for the media NOC QoS clock, which use the same clock with + jpeg codec. + "clk_ade_pix" for the ADE pixel clok. +- assigned-clocks: Should contain "clk_ade_core" and "clk_codec_jpeg" clocks' + phandle + clock-specifier pairs. +- assigned-clock-rates: clock rates, one for each entry in assigned-clocks. + The rate of "clk_ade_core" could be "360000000" or "180000000"; + The rate of "clk_codec_jpeg" could be or less than "1440000000". + These rate values could be configured according to performance and power + consumption. +- port: the output port. This contains one endpoint subnode, with its + remote-endpoint set to the phandle of the connected DSI input endpoint. + See Documentation/devicetree/bindings/graph.txt for more device graph info. + +Optional properties: +- dma-coherent: Present if dma operations are coherent. A example of HiKey board hi6220 SoC specific DT entry: @@ -21,22 +37,28 @@ Example: ade: ade@f4100000 { compatible = "hisilicon,hi6220-ade"; - reg = <0x0 0xf4100000 0x0 0x7800>, - <0x0 0xf4410000 0x0 0x1000>; - reg-names = "ade_base", - "media_base"; - interrupts = <0 115 4>; + reg = <0x0 0xf4100000 0x0 0x7800>; + reg-names = "ade_base"; + hisilicon,noc-syscon = <&medianoc_ade>; + resets = <&media_ctrl MEDIA_ADE>; + interrupts = <0 115 4>; /* ldi interrupt */ clocks = <&media_ctrl HI6220_ADE_CORE>, <&media_ctrl HI6220_CODEC_JPEG>, - <&media_ctrl HI6220_ADE_PIX_SRC>, - <&media_ctrl HI6220_PLL_SYS>, - <&media_ctrl HI6220_PLL_SYS_MEDIA>; + <&media_ctrl HI6220_ADE_PIX_SRC>; + /*clock name*/ clock-names = "clk_ade_core", - "aclk_codec_jpeg_src", - "clk_ade_pix", - "clk_syspll_src", - "clk_medpll_src"; - ade_core_clk_rate = <360000000>; - media_noc_clk_rate = <288000000>; + "clk_codec_jpeg", + "clk_ade_pix"; + + assigned-clocks = <&media_ctrl HI6220_ADE_CORE>, + <&media_ctrl HI6220_CODEC_JPEG>; + assigned-clock-rates = <360000000>, <288000000>; + dma-coherent; + + port { + ade_out: endpoint { + remote-endpoint = <&dsi_in>; + }; + }; }; diff --git a/Documentation/devicetree/bindings/display/hisilicon/hisi-drm.txt b/Documentation/devicetree/bindings/display/hisilicon/hisi-drm.txt deleted file mode 100644 index fd93026..0000000 --- a/Documentation/devicetree/bindings/display/hisilicon/hisi-drm.txt +++ /dev/null @@ -1,66 +0,0 @@ -Hisilicon DRM master device - -The Hisilicon DRM master device is a virtual device needed to list all -the other display relevant nodes that comprise the display subsystem. - - -Required properties: -- compatible: Should be "hisilicon,-dss" -- #address-cells: should be set to 2. -- #size-cells: should be set to 2. -- range: to allow probing of subdevices. - -Optional properties: -- dma-coherent: Present if dma operations are coherent. - -Required sub nodes: -All the device nodes of display subsystem of SoC should be the sub nodes. -Such as display controller node, DSI node and so on. - -A example of HiKey board hi6220 SoC specific DT entry: -Example: - - display-subsystem { - compatible = "hisilicon,hi6220-dss"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-coherent; - - ade: ade@f4100000 { - compatible = "hisilicon,hi6220-ade"; - reg = <0x0 0xf4100000 0x0 0x7800>, - <0x0 0xf4410000 0x0 0x1000>; - reg-names = "ade_base", - "media_base"; - interrupts = <0 115 4>; /* ldi interrupt */ - - clocks = <&media_ctrl HI6220_ADE_CORE>, - <&media_ctrl HI6220_CODEC_JPEG>, - <&media_ctrl HI6220_ADE_PIX_SRC>, - <&media_ctrl HI6220_PLL_SYS>, - <&media_ctrl HI6220_PLL_SYS_MEDIA>; - /*clock name*/ - clock-names = "clk_ade_core", - "aclk_codec_jpeg_src", - "clk_ade_pix", - "clk_syspll_src", - "clk_medpll_src"; - ade_core_clk_rate = <360000000>; - media_noc_clk_rate = <288000000>; - }; - - dsi: dsi@0xf4107800 { - compatible = "hisilicon,hi6220-dsi"; - reg = <0x0 0xf4107800 0x0 0x100>; - clocks = <&media_ctrl HI6220_DSI_PCLK>; - clock-names = "pclk_dsi"; - - port { - dsi_out: endpoint { - remote-endpoint = <&adv_in>; - }; - }; - - }; - }; diff --git a/Documentation/devicetree/bindings/display/hisilicon/hisi-dsi.txt b/Documentation/devicetree/bindings/display/hisilicon/hisi-dsi.txt deleted file mode 100644 index 30abaa85..0000000 --- a/Documentation/devicetree/bindings/display/hisilicon/hisi-dsi.txt +++ /dev/null @@ -1,53 +0,0 @@ -Device-Tree bindings for hisilicon DSI controller driver - -A DSI controller resides in the middle of display controller and external -HDMI converter. - -Required properties: -- compatible: value should be one of the following - "hisilicon,hi6220-dsi". -- reg: physical base address and length of the controller's registers. -- clocks: the clocks needed. -- clock-names: the name of the clocks. -- port: DSI controller output port. This contains one endpoint subnode, with its - remote-endpoint set to the phandle of the connected external HDMI endpoint. - See Documentation/devicetree/bindings/graph.txt for device graph info. - -A example of HiKey board hi6220 SoC and board specific DT entry: -Example: - -SoC specific: - dsi: dsi@0xf4107800 { - compatible = "hisilicon,hi6220-dsi"; - reg = <0x0 0xf4107800 0x0 0x100>; - clocks = <&media_ctrl HI6220_DSI_PCLK>; - clock-names = "pclk_dsi"; - - port { - dsi_out: endpoint { - remote-endpoint = <&adv_in>; - }; - }; - - }; - -Board specific: - i2c2: i2c@f7102000 { - status = "ok"; - - adv7533: adv7533@39 { - compatible = "adi,adv7533"; - reg = <0x39>; - interrupt-parent = <&gpio1>; - interrupts = <1 2>; - pd-gpio = <&gpio0 4 0>; - adi,dsi-lanes = <4>; - - port { - adv_in: endpoint { - remote-endpoint = <&dsi_out>; - }; - }; - }; - }; - diff --git a/MAINTAINERS b/MAINTAINERS index ab65bbe..6e8cfea 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3705,6 +3705,16 @@ S: Maintained F: drivers/gpu/drm/gma500 F: include/drm/gma500* +DRM DRIVERS FOR HISILICON +M: Xinliang Liu +R: Xinwei Kong +R: Chen Feng +L: dri-devel@lists.freedesktop.org +T: git git://github.com/xin3liang/linux.git +S: Maintained +F: drivers/gpu/drm/hisilicon/ +F: Documentation/devicetree/bindings/display/hisilicon/ + DRM DRIVERS FOR NVIDIA TEGRA M: Thierry Reding M: Terje Bergström diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index 5d5e240..c33e713 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -107,15 +107,15 @@ interrupts = <1 2>; pd-gpio = <&gpio0 4 0>; adi,dsi-lanes = <4>; + adi,disable-timing-generator; port { - adv_in: endpoint { - remote-endpoint = <&dsi_out>; + adv7533_in: endpoint { + remote-endpoint = <&dsi_out0>; }; }; }; }; - uart1: uart@f7111000 { status = "ok"; }; @@ -336,3 +336,55 @@ }; }; }; + +&ade { + status = "ok"; +}; + +&dsi { + #address-cells = <1>; + #size-cells = <0>; + mux-gpio = <&gpio0 1 0>; + status = "ok"; + + ports { + /* 1 for output port */ + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + dsi_out0: endpoint@0 { + reg = <0>; + remote-endpoint = <&adv7533_in>; + }; + + dsi_out1: endpoint@1 { + reg = <1>; + remote-endpoint = <&panel0_in>; + }; + }; + }; + + /* For panel reg's value should >= 1 */ + panel@1 { + compatible = "innolux,n070icn-pb1"; + reg = <1>; + power-on-delay= <50>; + reset-delay = <100>; + init-delay = <100>; + panel-width-mm = <58>; + panel-height-mm = <103>; + pwr-en-gpio = <&gpio2 1 0>; + bl-en-gpio = <&gpio2 3 0>; + pwm-gpio = <&gpio12 7 0>; + + port { + panel0_in: endpoint { + remote-endpoint = <&dsi_out1>; + }; + }; + }; +}; + + diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 80aa50b..09e2c71 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -255,6 +255,7 @@ compatible = "hisilicon,hi6220-mediactrl", "syscon"; reg = <0x0 0xf4410000 0x0 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; }; pm_ctrl: pm_ctrl@f7032000 { @@ -271,6 +272,11 @@ mboxes = <&mailbox 1 0 11>; }; + medianoc_ade: medianoc_ade@f4520000 { + compatible = "syscon"; + reg = <0x0 0xf4520000 0x0 0x4000>; + }; + uart0: uart@f8015000 { /* console */ compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xf8015000 0x0 0x1000>; @@ -705,7 +711,7 @@ pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>; num-cs = <1>; cs-gpios = <&gpio6 2 0>; - status = "ok"; + status = "disabled"; }; i2c0: i2c@f7100000 { @@ -925,46 +931,51 @@ }; }; - display-subsystem { - compatible = "hisilicon,hi6220-dss"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ade: ade@f4100000 { - compatible = "hisilicon,hi6220-ade"; - reg = <0x0 0xf4100000 0x0 0x7800>, - <0x0 0xf4410000 0x0 0x1000>, - <0x0 0xf4520000 0x0 0x1000>; - reg-names = "ade_base", - "media_base", - "media_noc_base"; - interrupts = <0 115 4>; /* ldi interrupt */ - - clocks = <&media_ctrl HI6220_ADE_CORE>, - <&media_ctrl HI6220_CODEC_JPEG>, - <&media_ctrl HI6220_ADE_PIX_SRC>, - <&media_ctrl HI6220_PLL_SYS>, - <&media_ctrl HI6220_PLL_SYS_MEDIA>; - /*clock name*/ - clock-names = "clk_ade_core", - "aclk_codec_jpeg_src", - "clk_ade_pix", - "clk_syspll_src", - "clk_medpll_src"; - ade_core_clk_rate = <360000000>; - media_noc_clk_rate = <288000000>; + ade: ade@f4100000 { + compatible = "hisilicon,hi6220-ade"; + reg = <0x0 0xf4100000 0x0 0x7800>; + reg-names = "ade_base"; + hisilicon,noc-syscon = <&medianoc_ade>; + resets = <&media_ctrl MEDIA_ADE>; + interrupts = <0 115 4>; /* ldi interrupt */ + + clocks = <&media_ctrl HI6220_ADE_CORE>, + <&media_ctrl HI6220_CODEC_JPEG>, + <&media_ctrl HI6220_ADE_PIX_SRC>; + /*clock name*/ + clock-names = "clk_ade_core", + "clk_codec_jpeg", + "clk_ade_pix"; + + assigned-clocks = <&media_ctrl HI6220_ADE_CORE>, + <&media_ctrl HI6220_CODEC_JPEG>; + assigned-clock-rates = <360000000>, <288000000>; + dma-coherent; + status = "disabled"; + + port { + ade_out: endpoint { + remote-endpoint = <&dsi_in>; + }; }; + }; + + dsi: dsi@f4107800 { + compatible = "hisilicon,hi6220-dsi"; + reg = <0x0 0xf4107800 0x0 0x100>; + clocks = <&media_ctrl HI6220_DSI_PCLK>; + clock-names = "pclk"; + status = "disabled"; - dsi: dsi@0xf4107800 { - compatible = "hisilicon,hi6220-dsi"; - reg = <0x0 0xf4107800 0x0 0x100>; - clocks = <&media_ctrl HI6220_DSI_PCLK>; - clock-names = "pclk_dsi"; + ports { + #address-cells = <1>; + #size-cells = <0>; - port { - dsi_out: endpoint { - remote-endpoint = <&adv_in>; + /* 0 for input port */ + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <&ade_out>; }; }; }; diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index e7efcb7..95ba482 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -75,4 +75,4 @@ obj-y += i2c/ obj-y += panel/ obj-y += bridge/ obj-$(CONFIG_DRM_FSL_DCU) += fsl-dcu/ -obj-$(CONFIG_DRM_HISI) += hisilicon/ +obj-y += hisilicon/ diff --git a/drivers/gpu/drm/hisilicon/Kconfig b/drivers/gpu/drm/hisilicon/Kconfig index 7503981..558c61b 100644 --- a/drivers/gpu/drm/hisilicon/Kconfig +++ b/drivers/gpu/drm/hisilicon/Kconfig @@ -1,13 +1,3 @@ -config DRM_HISI - tristate "DRM Support for Hisilicon SoCs Platform" - depends on DRM - select DRM_KMS_HELPER - select DRM_GEM_CMA_HELPER - select DRM_KMS_CMA_HELPER - select DRM_MIPI_DSI - help - Choose this option if you have a hisilicon chipsets(hi6220). - If M is selected the module will be called hisi-drm. # # hisilicon drm device configuration. # Please keep this list sorted alphabetically diff --git a/drivers/gpu/drm/hisilicon/kirin/Kconfig b/drivers/gpu/drm/hisilicon/kirin/Kconfig index 5dcbc8d..57f6017 100644 --- a/drivers/gpu/drm/hisilicon/kirin/Kconfig +++ b/drivers/gpu/drm/hisilicon/kirin/Kconfig @@ -4,6 +4,7 @@ config DRM_HISI_KIRIN select DRM_KMS_HELPER select DRM_GEM_CMA_HELPER select DRM_KMS_CMA_HELPER + select HISI_KIRIN_DW_DSI help Choose this option if you have a hisilicon Kirin chipsets(hi6220). If M is selected the module will be called kirin-drm. diff --git a/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c index fe94ccb..aebb8fc 100644 --- a/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c +++ b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c @@ -1,10 +1,12 @@ /* - * Hisilicon hi6220 SoC dsi driver + * DesignWare MIPI DSI Host Controller v1.02 driver + * + * Copyright (c) 2016 Linaro Limited. + * Copyright (c) 2014-2016 Hisilicon Limited. * - * Copyright (c) 2014-2015 Hisilicon Limited. * Author: - * Xinliang Liu * Xinliang Liu + * Xinliang Liu * Xinwei Kong * * This program is free software; you can redistribute it and/or modify @@ -16,27 +18,39 @@ #include #include #include +#include +#include