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[192.237.175.120]) by mx.google.com with ESMTPS id e9si4507716ita.27.2016.07.14.09.24.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Jul 2016 09:24:39 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bNjOx-0003QH-F5; Thu, 14 Jul 2016 16:22:15 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bNjOw-0003Ow-Ae for xen-devel@lists.xen.org; Thu, 14 Jul 2016 16:22:14 +0000 Received: from [85.158.137.68] by server-1.bemta-3.messagelabs.com id 46/9A-28758-53CB7875; Thu, 14 Jul 2016 16:22:13 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrELMWRWlGSWpSXmKPExsVysyfVTdd0T3u 4wefzLBZLPi5mcWD0OLr7N1MAYxRrZl5SfkUCa8adh2eZC/rlK74v2srewHhCvIuRi0NIYCOj xJvXxxkhnNOMElcerGHpYuTkYBPQlLjz+RMTiC0iIC1x7fNlRhCbWaBQ4vrZJ2wgtrBAhMTRN S2sIDaLgKrEz7sXmUFsXgEXiZ2zroL1SgjISZw8NhmshlPAVWLF7k9gvUJANXOf3mSewMi9gJ FhFaN6cWpRWWqRrqFeUlFmekZJbmJmjq6hgbFebmpxcWJ6ak5iUrFecn7uJkagfxmAYAfj8o9 OhxglOZiURHm1+9vChfiS8lMqMxKLM+KLSnNSiw8xanBwCEw4O3c6kxRLXn5eqpIEb+Du9nAh waLU9NSKtMwcYADClEpw8CiJ8EaBpHmLCxJzizPTIVKnGBWlxHnjQBICIImM0jy4NljQX2KUl RLmZQQ6SoinILUoN7MEVf4VozgHo5Iwbw7IFJ7MvBK46a+AFjMBLbY2B1tckoiQkmpgjGB7nc LE/1G2T94x4yinXFyQzC//dQu/iPsdSrgWcuJobIbj+vcRbeeWbFf2lM0r/e3+4YnWWjeFfc1 qDld9668+eNkw36M+sFqmpv1y6vNsIYEjHod+MTZXzObizPz8rIZvm6Hvp86kP8Ii+z8daOC6 kShecMD4jeOlh2Uz5yRXnw9g+XBRiaU4I9FQi7moOBEAjluTLnUCAAA= X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-10.tower-31.messagelabs.com!1468513332!49950173!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 8.77; banners=-,-,- X-VirusChecked: Checked Received: (qmail 23878 invoked from network); 14 Jul 2016 16:22:12 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-10.tower-31.messagelabs.com with SMTP; 14 Jul 2016 16:22:12 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B279F2F; Thu, 14 Jul 2016 09:23:17 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.215.28]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2E1BF3F4F6; Thu, 14 Jul 2016 09:22:11 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 14 Jul 2016 17:21:57 +0100 Message-Id: <1468513325-29492-2-git-send-email-julien.grall@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1468513325-29492-1-git-send-email-julien.grall@arm.com> References: <1468513325-29492-1-git-send-email-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, shankerd@codeaurora.org, steve.capper@arm.com Subject: [Xen-devel] [PATCH v2 1/9] xen/arm: gic: Consolidate the IRQ affinity set in a single place X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" The code to set the IRQ affinity is duplicated: once in gicv{2,3}_set_properties and the other is gicv{2,3}_irq_set_affinity. Remove the code from gicv{2,3}_set_properties and call directly the affinity set helper from the common code. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- Changes in v2: - Add Stefano's reviewed-by --- xen/arch/arm/gic-v2.c | 10 +--------- xen/arch/arm/gic-v3.c | 10 ---------- xen/arch/arm/gic.c | 3 ++- xen/include/asm-arm/gic.h | 1 - 4 files changed, 3 insertions(+), 21 deletions(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 3893ece..6c7dbfe 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -236,16 +236,10 @@ static unsigned int gicv2_read_irq(void) return (readl_gicc(GICC_IAR) & GICC_IA_IRQ); } -/* - * needs to be called with a valid cpu_mask, ie each cpu in the mask has - * already called gic_cpu_init - */ static void gicv2_set_irq_properties(struct irq_desc *desc, - const cpumask_t *cpu_mask, - unsigned int priority) + unsigned int priority) { uint32_t cfg, actual, edgebit; - unsigned int mask = gicv2_cpu_mask(cpu_mask); unsigned int irq = desc->irq; unsigned int type = desc->arch.type; @@ -276,8 +270,6 @@ static void gicv2_set_irq_properties(struct irq_desc *desc, IRQ_TYPE_LEVEL_HIGH; } - /* Set target CPU mask (RAZ/WI on uniprocessor) */ - writeb_gicd(mask, GICD_ITARGETSR + irq); /* Set priority */ writeb_gicd(priority, GICD_IPRIORITYR + irq); diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index cbda066..d6ab0e9 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -472,13 +472,10 @@ static inline uint64_t gicv3_mpidr_to_affinity(int cpu) } static void gicv3_set_irq_properties(struct irq_desc *desc, - const cpumask_t *cpu_mask, unsigned int priority) { uint32_t cfg, actual, edgebit; - uint64_t affinity; void __iomem *base; - unsigned int cpu = gicv3_get_cpu_from_mask(cpu_mask); unsigned int irq = desc->irq; unsigned int type = desc->arch.type; @@ -516,13 +513,6 @@ static void gicv3_set_irq_properties(struct irq_desc *desc, IRQ_TYPE_LEVEL_HIGH; } - affinity = gicv3_mpidr_to_affinity(cpu); - /* Make sure we don't broadcast the interrupt */ - affinity &= ~GICD_IROUTER_SPI_MODE_ANY; - - if ( irq >= NR_GIC_LOCAL_IRQS ) - writeq_relaxed(affinity, (GICD + GICD_IROUTER + irq * 8)); - /* Set priority */ if ( irq < NR_GIC_LOCAL_IRQS ) writeb_relaxed(priority, GICD_RDIST_SGI_BASE + GICR_IPRIORITYR0 + irq); diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 12bb0ab..5726a05 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -106,7 +106,8 @@ static void gic_set_irq_properties(struct irq_desc *desc, const cpumask_t *cpu_mask, unsigned int priority) { - gic_hw_ops->set_irq_properties(desc, cpu_mask, priority); + gic_hw_ops->set_irq_properties(desc, priority); + desc->handler->set_affinity(desc, cpu_mask); } /* Program the GIC to route an interrupt to the host (i.e. Xen) diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index b073c53..2fc6126 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -331,7 +331,6 @@ struct gic_hw_operations { unsigned int (*read_irq)(void); /* Set IRQ property */ void (*set_irq_properties)(struct irq_desc *desc, - const cpumask_t *cpu_mask, unsigned int priority); /* Send SGI */ void (*send_SGI)(enum gic_sgi sgi, enum gic_sgi_mode irqmode,