From patchwork Thu Jul 14 16:21:58 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 72026 Delivered-To: patch@linaro.org Received: by 10.140.29.52 with SMTP id a49csp165020qga; Thu, 14 Jul 2016 09:24:47 -0700 (PDT) X-Received: by 10.36.139.67 with SMTP id g64mr15785948ite.75.1468513485539; Thu, 14 Jul 2016 09:24:45 -0700 (PDT) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id f74si4503380iod.184.2016.07.14.09.24.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Jul 2016 09:24:45 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bNjOy-0003Rq-Qt; Thu, 14 Jul 2016 16:22:16 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bNjOx-0003Q2-9A for xen-devel@lists.xen.org; Thu, 14 Jul 2016 16:22:15 +0000 Received: from [85.158.137.68] by server-6.bemta-3.messagelabs.com id BB/10-24961-63CB7875; Thu, 14 Jul 2016 16:22:14 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrGLMWRWlGSWpSXmKPExsVysyfVTddsT3u 4wZrNPBZLPi5mcWD0OLr7N1MAYxRrZl5SfkUCa8aKS1kFvYoV796sZWlgPCDZxcjFISSwkVHi /PXLbBDOaUaJXXfvsncxcnKwCWhK3Pn8iQnEFhGQlrj2+TIjiM0sUChx/ewTNhBbWMBP4s2TD rA4i4CqxInL68HqeQVcJCb9ewRWIyEgJ3Hy2GRWEJtTwFVixe5PYHEhoJq5T28yT2DkXsDIsI pRozi1qCy1SNfIQC+pKDM9oyQ3MTNH19DAWC83tbg4MT01JzGpWC85P3cTI9C/9QwMjDsYm0/ 4HWKU5GBSEuXV7m8LF+JLyk+pzEgszogvKs1JLT7EKMPBoSTBG7i7PVxIsCg1PbUiLTMHGGgw aQkOHiUR3iiQNG9xQWJucWY6ROoUo6KUOG8cSEIAJJFRmgfXBgvuS4yyUsK8jAwMDEI8BalFu ZklqPKvGMU5GJWEeXNApvBk5pXATX8FtJgJaLG1OdjikkSElFQDo9SrZ9cfu3Zb7/8rxC94eP OKI13HN2/cV3bMYV71kk2yzu2FDvnXZZvNNDV2zdkw4c0GWZll7LKs7mtOXveTjE0oaZ5yM1t 61qw9k9Z4LV0ox9VT3L/vdadH7XrfZpcDVtUlByZaTfLI1Z0WU+0q27F9y/L4d7ciXM4rndK6 aBpygNd73q2bq5RYijMSDbWYi4oTAVsxlkFpAgAA X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-5.tower-31.messagelabs.com!1468513333!47488906!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 8.77; banners=-,-,- X-VirusChecked: Checked Received: (qmail 9574 invoked from network); 14 Jul 2016 16:22:13 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-5.tower-31.messagelabs.com with SMTP; 14 Jul 2016 16:22:13 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DDE0F28; Thu, 14 Jul 2016 09:23:18 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.215.28]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 59DD73F4F6; Thu, 14 Jul 2016 09:22:12 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 14 Jul 2016 17:21:58 +0100 Message-Id: <1468513325-29492-3-git-send-email-julien.grall@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1468513325-29492-1-git-send-email-julien.grall@arm.com> References: <1468513325-29492-1-git-send-email-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, shankerd@codeaurora.org, steve.capper@arm.com Subject: [Xen-devel] [PATCH v2 2/9] xen/arm: gic: Do not configure affinity during routing X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" The affinity of a guest IRQ is set every time the guest enable it (see vgic_enable_irqs). It is not necessary to set the affinity when the IRQ is routed to the guest because Xen will never receive the IRQ until it hass been enabled by the guest. To keep gic_route_irq_to_{xen,guest} behaving the same way (i.e just setting up the routing), the affinity of IRQ routed to Xen is moved into __setup_irq. Signed-off-by: Julien grall --- Changes in v2: - Patch renamed - Set the affinity for IRQ routed to Xen in __setup_irq --- xen/arch/arm/gic.c | 11 +++-------- xen/arch/arm/irq.c | 4 ++-- xen/include/asm-arm/gic.h | 3 +-- 3 files changed, 6 insertions(+), 12 deletions(-) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 5726a05..bc814a0 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -97,24 +97,19 @@ void gic_restore_state(struct vcpu *v) } /* - * needs to be called with a valid cpu_mask, ie each cpu in the mask has - * already called gic_cpu_init * - desc.lock must be held * - arch.type must be valid (i.e != IRQ_TYPE_INVALID) */ static void gic_set_irq_properties(struct irq_desc *desc, - const cpumask_t *cpu_mask, unsigned int priority) { gic_hw_ops->set_irq_properties(desc, priority); - desc->handler->set_affinity(desc, cpu_mask); } /* Program the GIC to route an interrupt to the host (i.e. Xen) * - needs to be called with desc.lock held */ -void gic_route_irq_to_xen(struct irq_desc *desc, const cpumask_t *cpu_mask, - unsigned int priority) +void gic_route_irq_to_xen(struct irq_desc *desc, unsigned int priority) { ASSERT(priority <= 0xff); /* Only 8 bits of priority */ ASSERT(desc->irq < gic_number_lines());/* Can't route interrupts that don't exist */ @@ -123,7 +118,7 @@ void gic_route_irq_to_xen(struct irq_desc *desc, const cpumask_t *cpu_mask, desc->handler = gic_hw_ops->gic_host_irq_type; - gic_set_irq_properties(desc, cpu_mask, priority); + gic_set_irq_properties(desc, priority); } /* Program the GIC to route an interrupt to a guest @@ -155,7 +150,7 @@ int gic_route_irq_to_guest(struct domain *d, unsigned int virq, desc->handler = gic_hw_ops->gic_guest_irq_type; set_bit(_IRQ_GUEST, &desc->status); - gic_set_irq_properties(desc, cpumask_of(v_target->processor), priority); + gic_set_irq_properties(desc, priority); p->desc = desc; res = 0; diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c index 2f8af72..3fc22f2 100644 --- a/xen/arch/arm/irq.c +++ b/xen/arch/arm/irq.c @@ -370,6 +370,7 @@ int setup_irq(unsigned int irq, unsigned int irqflags, struct irqaction *new) /* First time the IRQ is setup */ if ( disabled ) { + gic_route_irq_to_xen(desc, GIC_PRI_IRQ); /* It's fine to use smp_processor_id() because: * For PPI: irq_desc is banked * For SPI: we don't care for now which CPU will receive the @@ -377,8 +378,7 @@ int setup_irq(unsigned int irq, unsigned int irqflags, struct irqaction *new) * TODO: Handle case where SPI is setup on different CPU than * the targeted CPU and the priority. */ - gic_route_irq_to_xen(desc, cpumask_of(smp_processor_id()), - GIC_PRI_IRQ); + irq_set_affinity(desc, cpumask_of(smp_processor_id())); desc->handler->startup(desc); } diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 2fc6126..7ba3846 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -223,8 +223,7 @@ enum gic_version { extern enum gic_version gic_hw_version(void); /* Program the GIC to route an interrupt */ -extern void gic_route_irq_to_xen(struct irq_desc *desc, const cpumask_t *cpu_mask, - unsigned int priority); +extern void gic_route_irq_to_xen(struct irq_desc *desc, unsigned int priority); extern int gic_route_irq_to_guest(struct domain *, unsigned int virq, struct irq_desc *desc, unsigned int priority);