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[192.237.175.120]) by mx.google.com with ESMTPS id e200si1887971ita.20.2016.09.22.05.56.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 22 Sep 2016 05:56:04 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bn3W5-0004ZN-QX; Thu, 22 Sep 2016 12:54:17 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bn3W4-0004Yc-N5 for xen-devel@lists.xen.org; Thu, 22 Sep 2016 12:54:16 +0000 Received: from [85.158.143.35] by server-4.bemta-6.messagelabs.com id 5D/A7-29421-874D3E75; Thu, 22 Sep 2016 12:54:16 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrBIsWRWlGSWpSXmKPExsVi9XuGg275lcf hBq/XiVos+biYxYHR4+ju30wBjFGsmXlJ+RUJrBmPr3UyFjwVqdiy9ihbA+MKwS5GLg4hgVOM EkufN7BDOHsYJW7vn8baxcjJwSagJXF++g92EFtEQFZiddccsCJmgTVMEhtOdzKDJIQFIiUu3 pgO1sAioCrx/NBbIJuDg1fAU+LFXVmQsISAhsTK3gksIDYnUHjCkfVg5UICHhIrrywEs3kFBC VOznwCVsMsICFx8MULZoheRYm29SfZIGxJiYMrbrCA3CABcvX+04+hEqYSB7f8ZpvAKDgLyax ZSGYtYGRaxahRnFpUllqka2Spl1SUmZ5RkpuYmaNraGCml5taXJyYnpqTmFSsl5yfu4kRGKIM QLCD8cCiwEOMkhxMSqK8F/ofhwvxJeWnVGYkFmfEF5XmpBYfYpTh4FCS4E24DJQTLEpNT61Iy 8wBRgtMWoKDR0mEtxgkzVtckJhbnJkOkTrFqCglzlsHkhAASWSU5sG1wSL0EqOslDAvI9AhQj wFqUW5mSWo8q8YxTkYlYR5xUCm8GTmlcBNfwW0mAlo8ZafD0AWlyQipKQaGPl+uqnmcJQs3Nj J+fNOsUfMRyaL1P8z1RKs+fWnNgjLFNxe7nrI9MBCjymOXxSv9j90yNjew6FlvsLmuuPm6gkZ xxquVU24mCVvu6DpTUvvU021m4rhW7WZ+e84Ln7t3hiyZ9UZNfX95i1qz0tufHjU/rr9g1mRQ I6uKoN3zP7tKo71kk9OKrEUZyQaajEXFScCAIQIcjPLAgAA X-Env-Sender: zhaoshenglong@huawei.com X-Msg-Ref: server-2.tower-21.messagelabs.com!1474548849!20627227!1 X-Originating-IP: [58.251.152.64] X-SpamReason: No, hits=0.0 required=7.0 tests=UPPERCASE_25_50 X-StarScan-Received: X-StarScan-Version: 8.84; banners=-,-,- X-VirusChecked: Checked Received: (qmail 48315 invoked from network); 22 Sep 2016 12:54:14 -0000 Received: from szxga01-in.huawei.com (HELO szxga01-in.huawei.com) (58.251.152.64) by server-2.tower-21.messagelabs.com with RC4-SHA encrypted SMTP; 22 Sep 2016 12:54:14 -0000 Received: from 172.24.1.36 (EHLO szxeml431-hub.china.huawei.com) ([172.24.1.36]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DRK49283; Thu, 22 Sep 2016 20:53:12 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by szxeml431-hub.china.huawei.com (10.82.67.208) with Microsoft SMTP Server id 14.3.235.1; Thu, 22 Sep 2016 20:53:00 +0800 From: z00226004 To: Date: Thu, 22 Sep 2016 20:52:31 +0800 Message-ID: <1474548753-12596-15-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1474548753-12596-1-git-send-email-zhaoshenglong@huawei.com> References: <1474548753-12596-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020205.57E3D43B.006C, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 059a9294fd35557234d4cd1f101e47f8 Cc: sstabellini@kernel.org, wei.liu2@citrix.com, Andrew Cooper , ian.jackson@eu.citrix.com, peter.huangpeng@huawei.com, julien.grall@arm.com, shannon.zhao@linaro.org, Jan Beulich , boris.ostrovsky@oracle.com Subject: [Xen-devel] [PATCH v6 14/16] public/hvm/params.h: Add macros for HVM_PARAM_CALLBACK_TYPE_PPI X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" From: Shannon Zhao Add macros for HVM_PARAM_CALLBACK_TYPE_PPI operation values and update them in evtchn_fixup(). Also use HVM_PARAM_CALLBACK_IRQ_TYPE_MASK in hvm_set_callback_via(). Cc: Jan Beulich Cc: Andrew Cooper Signed-off-by: Shannon Zhao Acked-by: Julien Grall --- xen/arch/arm/domain_build.c | 9 ++++++--- xen/arch/x86/hvm/irq.c | 2 +- xen/include/public/hvm/params.h | 3 +++ 3 files changed, 10 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 35ab08d..0cf7dc3 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -2016,9 +2016,12 @@ static void evtchn_fixup(struct domain *d, struct kernel_info *kinfo) d->arch.evtchn_irq); /* Set the value of domain param HVM_PARAM_CALLBACK_IRQ */ - val = (u64)HVM_PARAM_CALLBACK_TYPE_PPI << 56; - val |= (2 << 8); /* Active-low level-sensitive */ - val |= d->arch.evtchn_irq & 0xff; + val = MASK_INSR(HVM_PARAM_CALLBACK_TYPE_PPI, + HVM_PARAM_CALLBACK_IRQ_TYPE_MASK); + /* Active-low level-sensitive */ + val |= MASK_INSR(HVM_PARAM_CALLBACK_TYPE_PPI_FLAG_LOW_LEVEL, + HVM_PARAM_CALLBACK_TYPE_PPI_FLAG_MASK); + val |= d->arch.evtchn_irq; d->arch.hvm_domain.params[HVM_PARAM_CALLBACK_IRQ] = val; /* diff --git a/xen/arch/x86/hvm/irq.c b/xen/arch/x86/hvm/irq.c index 5323d7c..e597114 100644 --- a/xen/arch/x86/hvm/irq.c +++ b/xen/arch/x86/hvm/irq.c @@ -325,7 +325,7 @@ void hvm_set_callback_via(struct domain *d, uint64_t via) unsigned int gsi=0, pdev=0, pintx=0; uint8_t via_type; - via_type = (uint8_t)(via >> 56) + 1; + via_type = (uint8_t)MASK_EXTR(via, HVM_PARAM_CALLBACK_IRQ_TYPE_MASK) + 1; if ( ((via_type == HVMIRQ_callback_gsi) && (via == 0)) || (via_type > HVMIRQ_callback_vector) ) via_type = HVMIRQ_callback_none; diff --git a/xen/include/public/hvm/params.h b/xen/include/public/hvm/params.h index f7338a3..5c50e2e 100644 --- a/xen/include/public/hvm/params.h +++ b/xen/include/public/hvm/params.h @@ -30,6 +30,7 @@ */ #define HVM_PARAM_CALLBACK_IRQ 0 +#define HVM_PARAM_CALLBACK_IRQ_TYPE_MASK 0xFF00000000000000 /* * How should CPU0 event-channel notifications be delivered? * @@ -66,6 +67,8 @@ * This is only used by ARM/ARM64 and masking/eoi the interrupt associated to * the notification is handled by the interrupt controller. */ +#define HVM_PARAM_CALLBACK_TYPE_PPI_FLAG_MASK 0xFF00 +#define HVM_PARAM_CALLBACK_TYPE_PPI_FLAG_LOW_LEVEL 2 #endif /*