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[209.85.220.65]) by mx.google.com with SMTPS id n10-v6sor247542pge.36.2018.07.19.22.15.08 for (Google Transport Security); Thu, 19 Jul 2018 22:15:08 -0700 (PDT) Received-SPF: pass (google.com: domain of sumit.garg@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KhST3RXk; spf=pass (google.com: domain of sumit.garg@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=sumit.garg@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=uvbbSbQRPwx6R0SA3ZnjYxO8pi8W7EY0Hm3Ou1Vf5dY=; b=KhST3RXkUyHELQ4R7X85WaqR88oXnWYGH5/Qt7ktCJ3pSVnt6kLhDuu9Pdf2a+5eYd UHYGOanqgS10rL+B39RKw2r2U1I9ge07eEzrrOffTUlzh3G4Vuh/C6v5EhLXvCjJlylV vNlO3INbsRqs2ZGgGDydLNrxle1ObKPdeQ0/E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=uvbbSbQRPwx6R0SA3ZnjYxO8pi8W7EY0Hm3Ou1Vf5dY=; b=ZRbTFIjwbwsL3ItvjFEjgFLYwipXJDVATO9srVYpVfJ25FqH2wE/EhX6Et2Vq2Lt7L HahbsLItIawbIBHTAOQZG96ve4XHJerlREony9u12hSUynZJxKxymzfzc7QFefIteGMd hTQCckyn2GOOHa1NcUwJyuIQjKtIvPuxRnDgij0MjRtr719Y7ZNgkKNW8vawfGdQg9O6 WsIdALk3pt+2KO2hDZ0HIRiNzQutU0n4crNP9pmVfh4k2aEwzvrVDSuk0IKEWYTv4nnH HK3xJyI5/D5rVQmy6RtBhPMtYu0vI11beoQakONlDNzXba+wokIy1+92WBin/uIK6Jyf ySVQ== X-Gm-Message-State: AOUpUlFJM35PSw813T05+ypvp2TqW7pH9t2GL661gQ49MqFdWrDCiSM7 w3lDW/FtP82fREE2Ty6aIdp3x3bl X-Google-Smtp-Source: AAOMgpfPsTqyrjA7b/bHX+AGjhF0OV9Z8XpUVchwqGTihbgSJ+GvgCWGjbVdodXGBCapopD5NrHmwg== X-Received: by 2002:a65:448a:: with SMTP id l10-v6mr646704pgq.382.1532063708063; Thu, 19 Jul 2018 22:15:08 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([117.212.88.88]) by smtp.gmail.com with ESMTPSA id r19-v6sm986661pgo.68.2018.07.19.22.15.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 19 Jul 2018 22:15:07 -0700 (PDT) From: Sumit Garg To: daniel.thompson@linaro.org Cc: patches@linaro.org, Sumit Garg Subject: [PATCH] synquacer: Enable optional OP-TEE support Date: Fri, 20 Jul 2018 10:44:54 +0530 Message-Id: <1532063694-3466-1-git-send-email-sumit.garg@linaro.org> X-Mailer: git-send-email 2.7.4 OP-TEE loading is optional on Developerbox controlled via SCP firmware. To check if OP-TEE is loaded or not, we use DRAM1 region info passed by SCP firmware. Signed-off-by: Sumit Garg --- plat/socionext/synquacer/platform.mk | 4 ++++ plat/socionext/synquacer/sq_bl31_setup.c | 35 ++++++++++++++++++++++---------- 2 files changed, 28 insertions(+), 11 deletions(-) -- 2.7.4 diff --git a/plat/socionext/synquacer/platform.mk b/plat/socionext/synquacer/platform.mk index 546f84a..96427a1 100644 --- a/plat/socionext/synquacer/platform.mk +++ b/plat/socionext/synquacer/platform.mk @@ -18,6 +18,10 @@ ERRATA_A53_855873 := 1 # Libraries include lib/xlat_tables_v2/xlat_tables.mk +ifeq (${SPD},opteed) +TF_CFLAGS_aarch64 += -DBL32_BASE=0xfc000000 +endif + PLAT_PATH := plat/socionext/synquacer PLAT_INCLUDES := -I$(PLAT_PATH)/include \ -I$(PLAT_PATH)/drivers/scpi \ diff --git a/plat/socionext/synquacer/sq_bl31_setup.c b/plat/socionext/synquacer/sq_bl31_setup.c index 461c8de..9e5fa6f 100644 --- a/plat/socionext/synquacer/sq_bl31_setup.c +++ b/plat/socionext/synquacer/sq_bl31_setup.c @@ -58,6 +58,8 @@ uint32_t sq_get_spsr_for_bl33_entry(void) void bl31_early_platform_setup(bl31_params_t *from_bl2, void *plat_params_from_bl2) { + struct draminfo di = {0}; + /* Initialize the console to provide early debug support */ (void)console_pl011_register(PLAT_SQ_BOOT_UART_BASE, PLAT_SQ_BOOT_UART_CLK_IN_HZ, @@ -70,15 +72,29 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2, assert(from_bl2 == NULL); assert(plat_params_from_bl2 == NULL); + /* Initialize power controller before setting up topology */ + plat_sq_pwrc_setup(); + #ifdef BL32_BASE - /* Populate entry point information for BL32 */ - SET_PARAM_HEAD(&bl32_image_ep_info, - PARAM_EP, - VERSION_1, - 0); - SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); - bl32_image_ep_info.pc = BL32_BASE; - bl32_image_ep_info.spsr = sq_get_spsr_for_bl32_entry(); + scpi_get_draminfo(&di); + + /* + * Check if OP-TEE has been loaded in Secure RAM allocated + * from DRAM1 region + */ + if ((di.base1 + di.size1) <= BL32_BASE) { + NOTICE("OP-TEE has been loaded by SCP firmware\n"); + /* Populate entry point information for BL32 */ + SET_PARAM_HEAD(&bl32_image_ep_info, + PARAM_EP, + VERSION_1, + 0); + SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); + bl32_image_ep_info.pc = BL32_BASE; + bl32_image_ep_info.spsr = sq_get_spsr_for_bl32_entry(); + } else { + NOTICE("OP-TEE has not been loaded by SCP firmware\n"); + } #endif /* BL32_BASE */ /* Populate entry point information for BL33 */ @@ -125,9 +141,6 @@ void bl31_platform_setup(void) /* Allow access to the System counter timer module */ sq_configure_sys_timer(); - - /* Initialize power controller before setting up topology */ - plat_sq_pwrc_setup(); } void bl31_plat_runtime_setup(void)