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[209.85.220.65]) by mx.google.com with SMTPS id w28-v6sor415215pgm.32.2018.08.02.03.53.15 for (Google Transport Security); Thu, 02 Aug 2018 03:53:16 -0700 (PDT) Received-SPF: pass (google.com: domain of sumit.garg@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JHMYoDV7; spf=pass (google.com: domain of sumit.garg@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=sumit.garg@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LuNE06Zl9W3RH+jQszrGU96pHh5yl5iSeaF7SVYmiRU=; b=JHMYoDV7NlAAIBcOuHDoxfI/XZq2g29CAOU7x/VxN75KUsjOqATo/bqWlcenK/lQxJ WepgIIqI2tYRPIP6B1g0/LH9dAw+YAFRHj5KM4YjNd8OuVKUmIxjTmTp1uvF4n8N/03v o0LnHkgISVhB5/cJXaJUmsDb3EFU0aM5h9vNY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LuNE06Zl9W3RH+jQszrGU96pHh5yl5iSeaF7SVYmiRU=; b=Dk9LTiWW9kHy+gUUm1Sru8SkAYnPKRS7q0RlMlRVfiDtEqwrShSgj9IM5nUI9LpXB2 mqqCy6hmO3xwTalKcQcGhRlG38v1BfoNJmMTzURyjEkQL9/E9DDyd9TYsbf4oF8xG2rZ xj1618tz9OppnmGwVBlb7d0tNIiRSrvW9n2DyJxqos5CoHB3eUoUdtx4+nD8SPKeTkW8 OBhaeRUMlq3Y7pkd3GcL7S878Ej7wha+x1/nDDr2QboxIgdXrYIxtfMLoDYR3igKkMCL YLXj02Tzqx0Qefja9pzAYgXvWCRqyKUUkltgK+euROTuksLlfQ1eSKe0xbAxEc9TgNC/ yL7Q== X-Gm-Message-State: AOUpUlGQh6pEnj2UVvDZpj/p9HPmXJRnG4KeObf6TQHOA1TSTYSKN0mS BWA5xiOWhFKMTC4OJ9TB1PkqCVtO X-Google-Smtp-Source: AAOMgpcmCg9V6a9FwEirL18PwuX9brcmh+bbeP+ZKSFjBZNPsd07EQSCBVFAsApYKW2ri2ZKa0MRDg== X-Received: by 2002:a63:de4c:: with SMTP id y12-v6mr1088270pgi.435.1533207195660; Thu, 02 Aug 2018 03:53:15 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([117.197.43.141]) by smtp.gmail.com with ESMTPSA id b67-v6sm3426580pfd.74.2018.08.02.03.53.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 02 Aug 2018 03:53:15 -0700 (PDT) From: Sumit Garg To: daniel.thompson@linaro.org, ard.biesheuvel@linaro.org Cc: patches@linaro.org, Sumit Garg Subject: [edk2][PATCH edk2-platforms 2/2] Silicon/SynQuacer: Add status property in PCIe & SDHC DT nodes Date: Thu, 2 Aug 2018 16:22:38 +0530 Message-Id: <1533207158-18652-2-git-send-email-sumit.garg@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1533207158-18652-1-git-send-email-sumit.garg@linaro.org> References: <1533207158-18652-1-git-send-email-sumit.garg@linaro.org> Add status = "disabled" property by default for PCIe and SDHC DT nodes. If required, update them at runtime with status = "okay". Using this method we don't need extra DTB_PADDING. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sumit Garg --- .../Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 3 ++ .../SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c | 40 ++++------------------ 2 files changed, 10 insertions(+), 33 deletions(-) -- 2.7.4 diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index d6a5f013e58c..003e21bd6f85 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -473,6 +473,7 @@ msi-map = <0x000 &its 0x0 0x7f00>; dma-coherent; + status = "disabled"; }; pcie1: pcie@70000000 { @@ -492,6 +493,7 @@ msi-map = <0x0 &its 0x10000 0x7f00>; dma-coherent; + status = "disabled"; }; gpio: gpio@51000000 { @@ -537,6 +539,7 @@ clocks = <&clk_alw_c_0 &clk_alw_b_0>; clock-names = "core", "iface"; dma-coherent; + status = "disabled"; }; clk_alw_1_8: spi_ihclk { diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c index 77db30c204fe..96090c20502c 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c @@ -22,32 +22,6 @@ #include #include -// add enough space for three instances of 'status = "disabled"' -#define DTB_PADDING 64 - -STATIC -VOID -DisableDtNode ( - IN VOID *Dtb, - IN CONST CHAR8 *NodePath - ) -{ - INT32 Node; - INT32 Rc; - - Node = fdt_path_offset (Dtb, NodePath); - if (Node < 0) { - DEBUG ((DEBUG_ERROR, "%a: failed to locate DT path '%a': %a\n", - __FUNCTION__, NodePath, fdt_strerror (Node))); - return; - } - Rc = fdt_setprop_string (Dtb, Node, "status", "disabled"); - if (Rc < 0) { - DEBUG ((DEBUG_ERROR, "%a: failed to set status to 'disabled' on '%a': %a\n", - __FUNCTION__, NodePath, fdt_strerror (Rc))); - } -} - STATIC VOID EnableDtNode ( @@ -105,7 +79,7 @@ DtPlatformLoadDtb ( return EFI_NOT_FOUND; } - CopyDtbSize = OrigDtbSize + DTB_PADDING; + CopyDtbSize = OrigDtbSize; CopyDtb = AllocatePool (CopyDtbSize); if (CopyDtb == NULL) { return EFI_OUT_OF_RESOURCES; @@ -118,17 +92,17 @@ DtPlatformLoadDtb ( return EFI_NOT_FOUND; } - if (!(PcdGet8 (PcdPcieEnableMask) & BIT0)) { - DisableDtNode (CopyDtb, "/pcie@60000000"); + if (PcdGet8 (PcdPcieEnableMask) & BIT0) { + EnableDtNode (CopyDtb, "/pcie@60000000"); } - if (!(PcdGet8 (PcdPcieEnableMask) & BIT1)) { - DisableDtNode (CopyDtb, "/pcie@70000000"); + if (PcdGet8 (PcdPcieEnableMask) & BIT1) { + EnableDtNode (CopyDtb, "/pcie@70000000"); } SettingsVal = PcdGet64 (PcdPlatformSettings); Settings = (SYNQUACER_PLATFORM_VARSTORE_DATA *)&SettingsVal; - if (Settings->EnableEmmc == EMMC_DISABLED) { - DisableDtNode (CopyDtb, "/sdhci@52300000"); + if (Settings->EnableEmmc == EMMC_ENABLED) { + EnableDtNode (CopyDtb, "/sdhci@52300000"); } if (IsOpteePresent()) {