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[209.85.220.65]) by mx.google.com with SMTPS id o10-v6sor45173872plk.56.2018.11.21.22.53.21 for (Google Transport Security); Wed, 21 Nov 2018 22:53:21 -0800 (PST) Received-SPF: pass (google.com: domain of sumit.garg@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=I6fTnqN0; spf=pass (google.com: domain of sumit.garg@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=sumit.garg@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZRSf/PnOlFiPbqot3PWxBg57/D2oit07iiy9kH0bfxc=; b=I6fTnqN0ethq27A181OyjpTjmiPRuvsvofRNPbWODKFRpaC3ErqNvC3Ciq0dlUpjnf +tuHLmGdyZkvKEUAb6vV5ombmfR86oJk8YXd3si9uoQyAUgTdQcadJtjPAoK9T0nnCFu km4Z2JY12PFfR0te3VbE5r7r0hFLsvdaltKKM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZRSf/PnOlFiPbqot3PWxBg57/D2oit07iiy9kH0bfxc=; b=rzza5kUENwDUYwdhgg89ZWoufYnzbOMIfLdurxOZH09WFaiN9UMSoE45Mtx6YEryql KI1w54KjmfvJXWnt8YZxOohUoz60W5Lri9GUoooWxmdkKBR1WgbB6IK1ryg4KuuH9A3K ioyILkwuSj7tlH7IzI0Tdzxoza1er9RCWuhEqjDQoLkC5dEnS71LzBhe+i7gNg7cTNXU CswA2EDq1NtQEA3gbNBKab0gw7mJ87qQzNJNi22R+sA0WhIV8fxVRzsRHQZ/XWwcA9f2 UVrrpI/LJ6iG7g8dLhRTZXQmmdhO+WK4s8JBNw3qh0pZDAoiOzVTN278pAgADO6TncZ4 LTNA== X-Gm-Message-State: AA+aEWYiuzZHZd3BxAq/x+S8xi4lwhJ6TQ6MKYZ9srxzE7V+URApbqS+ oQxm9kYJBMWCBZUDcGvxZ4LZ4MTx X-Google-Smtp-Source: AFSGD/VBmHzEMEvfsm5svdNKKlXO4JqribQtcxfwSe1hltP9F4pbXm/AA6ituMgfiWHpjAETwmpecw== X-Received: by 2002:a17:902:2bc5:: with SMTP id l63-v6mr10133591plb.241.1542869601344; Wed, 21 Nov 2018 22:53:21 -0800 (PST) Return-Path: Received: from localhost.localdomain ([117.252.69.224]) by smtp.gmail.com with ESMTPSA id c4sm18745043pfm.151.2018.11.21.22.53.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Nov 2018 22:53:20 -0800 (PST) From: Sumit Garg To: daniel.thompson@linaro.org Cc: patches@linaro.org, Sumit Garg Subject: [PATCH v4 2/3] synquacer: Add secure timer interrupt framework Date: Thu, 22 Nov 2018 12:22:56 +0530 Message-Id: <1542869577-32435-2-git-send-email-sumit.garg@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1542869577-32435-1-git-send-email-sumit.garg@linaro.org> References: <1542869577-32435-1-git-send-email-sumit.garg@linaro.org> Currently there is no means to perform background housekeeping in secure world on Synquacer platforms. Provide an (optional) periodic timer to allow any housekeeping to be performed. Although it could be expanded, at present the code is fairly simple because we expect only a single PTA to exploit the timer interrupt. The secure timer interrupt is configured to fire every 2ms. Signed-off-by: Sumit Garg --- core/arch/arm/include/arm64.h | 4 ++ core/arch/arm/plat-synquacer/main.c | 30 ++++++++++-- core/arch/arm/plat-synquacer/platform_config.h | 2 + core/arch/arm/plat-synquacer/sub.mk | 1 + core/arch/arm/plat-synquacer/timer_fiq.c | 67 ++++++++++++++++++++++++++ core/arch/arm/plat-synquacer/timer_fiq.h | 13 +++++ 6 files changed, 112 insertions(+), 5 deletions(-) create mode 100644 core/arch/arm/plat-synquacer/timer_fiq.c create mode 100644 core/arch/arm/plat-synquacer/timer_fiq.h -- 2.7.4 diff --git a/core/arch/arm/include/arm64.h b/core/arch/arm/include/arm64.h index 2c1fd8c..0cf14c0 100644 --- a/core/arch/arm/include/arm64.h +++ b/core/arch/arm/include/arm64.h @@ -305,6 +305,10 @@ DEFINE_REG_READ_FUNC_(cntfrq, uint32_t, cntfrq_el0) DEFINE_REG_READ_FUNC_(cntpct, uint64_t, cntpct_el0) DEFINE_REG_READ_FUNC_(cntkctl, uint32_t, cntkctl_el1) DEFINE_REG_WRITE_FUNC_(cntkctl, uint32_t, cntkctl_el1) +DEFINE_REG_READ_FUNC_(cntps_ctl, uint32_t, cntps_ctl_el1) +DEFINE_REG_WRITE_FUNC_(cntps_ctl, uint32_t, cntps_ctl_el1) +DEFINE_REG_READ_FUNC_(cntps_cval, uint32_t, cntps_cval_el1) +DEFINE_REG_WRITE_FUNC_(cntps_cval, uint32_t, cntps_cval_el1) DEFINE_REG_READ_FUNC_(pmccntr, uint64_t, pmccntr_el0) diff --git a/core/arch/arm/plat-synquacer/main.c b/core/arch/arm/plat-synquacer/main.c index c3aac4c..714becd 100644 --- a/core/arch/arm/plat-synquacer/main.c +++ b/core/arch/arm/plat-synquacer/main.c @@ -18,6 +18,7 @@ #include #include #include +#include static void main_fiq(void); @@ -46,7 +47,7 @@ const struct thread_handlers *generic_boot_get_handlers(void) static void main_fiq(void) { - panic(); + gic_it_handle(&gic_data); } void console_init(void) @@ -66,12 +67,31 @@ void main_init_gic(void) if (!gicd_base) panic(); - /* Initialize GIC */ - gic_init(&gic_data, 0, gicd_base); + /* On ARMv8-A, GIC configuration is initialized in TF-A */ + gic_init_base_addr(&gic_data, 0, gicd_base); + itr_init(&gic_data.chip); } -void main_secondary_init_gic(void) +static enum itr_return timer_itr_cb(struct itr_handler *h __unused) +{ + /* Reset timer for next FIQ */ + generic_timer_handler(); + + return ITRR_HANDLED; +} + +static struct itr_handler timer_itr = { + .it = IT_SEC_TIMER, + .flags = ITRF_TRIGGER_LEVEL, + .handler = timer_itr_cb, +}; + +static TEE_Result init_timer_itr(void) { - gic_cpu_init(&gic_data); + itr_add(&timer_itr); + itr_enable(IT_SEC_TIMER); + + return TEE_SUCCESS; } +driver_init(init_timer_itr); diff --git a/core/arch/arm/plat-synquacer/platform_config.h b/core/arch/arm/plat-synquacer/platform_config.h index 4d6d545..f9b1b40 100644 --- a/core/arch/arm/plat-synquacer/platform_config.h +++ b/core/arch/arm/plat-synquacer/platform_config.h @@ -19,6 +19,8 @@ #define CONSOLE_UART_CLK_IN_HZ 62500000 #define CONSOLE_BAUDRATE 115200 +#define IT_SEC_TIMER 29 + #define DRAM0_BASE 0x80000000 /* Platform specific defines */ diff --git a/core/arch/arm/plat-synquacer/sub.mk b/core/arch/arm/plat-synquacer/sub.mk index 8ddc2fd..cfa1dc3 100644 --- a/core/arch/arm/plat-synquacer/sub.mk +++ b/core/arch/arm/plat-synquacer/sub.mk @@ -1,2 +1,3 @@ global-incdirs-y += . srcs-y += main.c +srcs-y += timer_fiq.c diff --git a/core/arch/arm/plat-synquacer/timer_fiq.c b/core/arch/arm/plat-synquacer/timer_fiq.c new file mode 100644 index 0000000..c775bb9 --- /dev/null +++ b/core/arch/arm/plat-synquacer/timer_fiq.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: BSD-2-Clause +/* + * Copyright (c) 2018, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static unsigned int timer_lock = SPINLOCK_UNLOCK; +static bool timer_fiq_running; + +void generic_timer_start(void) +{ + uint64_t cval; + uint32_t exceptions = thread_mask_exceptions(THREAD_EXCP_ALL); + + cpu_spin_lock(&timer_lock); + + if (timer_fiq_running == true) + goto exit; + + /* The timer will fire every 2 ms */ + cval = read_cntpct() + (read_cntfrq() / 500); + write_cntps_cval(cval); + + /* Enable the secure physical timer */ + write_cntps_ctl(1); + + timer_fiq_running = true; + +exit: + cpu_spin_unlock(&timer_lock); + thread_set_exceptions(exceptions); +} + +void generic_timer_stop(void) +{ + uint32_t exceptions = thread_mask_exceptions(THREAD_EXCP_ALL); + + cpu_spin_lock(&timer_lock); + + /* Disable the timer */ + write_cntps_ctl(0); + + timer_fiq_running = false; + + cpu_spin_unlock(&timer_lock); + thread_set_exceptions(exceptions); +} + +void generic_timer_handler(void) +{ + uint64_t cval; + + /* Ensure that the timer did assert the interrupt */ + assert((read_cntps_ctl() >> 2)); + + /* Reconfigure timer to fire every 2 ms */ + cval = read_cntpct() + (read_cntfrq() / 500); + write_cntps_cval(cval); +} diff --git a/core/arch/arm/plat-synquacer/timer_fiq.h b/core/arch/arm/plat-synquacer/timer_fiq.h new file mode 100644 index 0000000..4f2091a --- /dev/null +++ b/core/arch/arm/plat-synquacer/timer_fiq.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ +/* + * Copyright (C) 2018, Linaro Limited + */ + +#ifndef __TIMER_FIQ_H +#define __TIMER_FIQ_H + +void generic_timer_start(void); +void generic_timer_stop(void); +void generic_timer_handler(void); + +#endif /* __TIMER_FIQ_H */