From patchwork Fri Jul 17 06:20:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Garg X-Patchwork-Id: 235673 Delivered-To: patches@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp1428574ilg; Thu, 16 Jul 2020 23:21:32 -0700 (PDT) X-Received: by 2002:aa7:952b:: with SMTP id c11mr6454712pfp.186.1594966892689; Thu, 16 Jul 2020 23:21:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594966892; cv=none; d=google.com; s=arc-20160816; b=vMNDdsoUruNKY3htNsuZae8FLJ+3VXgl1JSYpvQMPigqYIcbpvuJA7WOKpk6A9y8A/ /xXIFG/NJ3pkuMbPntHSA6FtDb5cOKsTyzokYV/ph/TccE0SCTj4ZjafUE2hVR5+Ndt9 WkZrnvCAzzrGnLdhdP9u3Rhp7i+OGtMU07CktfpsPuhUNu9FdZsS4m83to+6FyEnMchF /2u2BWx6rVo/eA9LGYC0pWurcAmgqYEQryXzdr9njJGLv8DOkmtZJzbOw2+Spq8l+REx Fu6nS7fjcF8Yk1EuPua5koDBeuIWpP5cpEgKX1pqDXubXzl2/yCjhkPD19YXdJuoU2jY HHYw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=L5QBpzbQ08BmWVXWQQ1Ei99UM9wMUTbD0qwaSmoJOcI=; b=0rQvPaARb+gg4bb/6W5ulboruXdFloLZpL8vYMLN4gNCo45PTE6DfGyFCutCa9wu/3 t1YB/jHhXFdc2/2h3DT9Jrl+niZcBIs0VBu4FdLjhk5f0OaAPZ07JuWMdK0u9lv9Xu04 cHZHV/vBVEs9TKFIZUV+T+mhLwj9ydPbQs0QCz3P43AkrFMqeEy3X35fHgbkfKlGJpfH vmVgW/1DwZc6ywbEJDLs9jqhjq35TdMpGUbYc9A+BLJfteghQo4S5tK1iGQ+KZQCs7NB OWVWqLtogD2RNxVyx+DBQKNcJmq5y3XK727waggw6DAlbAKsy7wnmLino7zLjAX0/ndD eKDA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gTC7pGqe; spf=pass (google.com: domain of sumit.garg@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=sumit.garg@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id u187sor9529168pfc.23.2020.07.16.23.21.32 for (Google Transport Security); Thu, 16 Jul 2020 23:21:32 -0700 (PDT) Received-SPF: pass (google.com: domain of sumit.garg@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gTC7pGqe; spf=pass (google.com: domain of sumit.garg@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=sumit.garg@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=L5QBpzbQ08BmWVXWQQ1Ei99UM9wMUTbD0qwaSmoJOcI=; b=gTC7pGqexKEtOt/EEe5nAmuhbNNrpxIivm+6PfiC7zsLJ7gWwvyjPmjs7iLibIwl3T nGxrIenzEXgxrzMI3b7fLfvpwM4akS7HU14lj+D3i9TTKncBPEjf7S6WIk79ea2zDrcs xa17j/4QC3oozBgUU6inzXPqtkIs7kN8GI3le3xqJKqKTmD+DThySzae9dsUX4Z8oJcQ xPj7E2ccd7yk+LRFJhyM7v3Us5NaSOhDP14RM/4rtDvNDRAvhjXUUANPf1rS2vc2Rg9m ewixmrB6dqLnMDYE6nFJX7BWMSJoc210IfrzL4dLJ/z0n+GTOt8mmpazqTQmjUpcHBJu TdtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=L5QBpzbQ08BmWVXWQQ1Ei99UM9wMUTbD0qwaSmoJOcI=; b=Jh2uN3xYReHFR5QLwuGJs9X69imJdPy3K2393RMv5r7EKXtvbsx1RmE6c08C1P12WB hcZlTDX0Lz6GyErOV6Gfbl93QLmB+zDL7Sqy8HnOGkGjXDY7coice0bh4NoQbG6+uxgU oJbC2qSq2V4DuExoSdOBy5Y18mX8kqel+NKT5GOGwvLWkjgQUV67b0JXbRN+WMglLBpr RgvQM40tfG02GrpygIW+KSocoI40mZcra8tp+JUhJ/BH2PME5jHngIudDDg3bfzjzTpk YrxIGiRzv7O3LIFnhEzOfKrE7GfSLFSXzI4v+nAyKA/5UzdLtV6rbMw1KWMShEOINhuQ YBcQ== X-Gm-Message-State: AOAM532swlsGyE/fc+m6fJGRXO2adFCt+rIyV6FX2YxsvpCKeCdWDr6R SeEyGh9ccHMyXWdnbsNVrxTSpsh0B8vn7Q== X-Google-Smtp-Source: ABdhPJxG7sl50KcDKc9bA7QScxvgGLQCM+m84k0PqpBCOIaAdsu6y4LI6J/BGnqoXKCGCL977I3MSA== X-Received: by 2002:aa7:9419:: with SMTP id x25mr6855850pfo.67.1594966892217; Thu, 16 Jul 2020 23:21:32 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([117.210.211.74]) by smtp.gmail.com with ESMTPSA id b4sm6630466pfo.137.2020.07.16.23.21.29 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 16 Jul 2020 23:21:31 -0700 (PDT) From: Sumit Garg To: daniel.thompson@linaro.org Cc: patches@linaro.org, Sumit Garg Subject: [RFC INTERNAL v3 3/4] serial: amba-pl011: Re-order APIs definition Date: Fri, 17 Jul 2020 11:50:56 +0530 Message-Id: <1594966857-5215-4-git-send-email-sumit.garg@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1594966857-5215-1-git-send-email-sumit.garg@linaro.org> References: <1594966857-5215-1-git-send-email-sumit.garg@linaro.org> Re-order pl011_hwinit() and pl011_enable_interrupts() APIs definition to allow their re-use in polling mode. Signed-off-by: Sumit Garg --- drivers/tty/serial/amba-pl011.c | 148 ++++++++++++++++++++-------------------- 1 file changed, 74 insertions(+), 74 deletions(-) -- 2.7.4 diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c index 8efd7c2..0983c5e 100644 --- a/drivers/tty/serial/amba-pl011.c +++ b/drivers/tty/serial/amba-pl011.c @@ -1581,6 +1581,80 @@ static void pl011_break_ctl(struct uart_port *port, int break_state) spin_unlock_irqrestore(&uap->port.lock, flags); } +static int pl011_hwinit(struct uart_port *port) +{ + struct uart_amba_port *uap = + container_of(port, struct uart_amba_port, port); + int retval; + + /* Optionaly enable pins to be muxed in and configured */ + pinctrl_pm_select_default_state(port->dev); + + /* + * Try to enable the clock producer. + */ + retval = clk_prepare_enable(uap->clk); + if (retval) + return retval; + + uap->port.uartclk = clk_get_rate(uap->clk); + + /* Clear pending error and receive interrupts */ + pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS | + UART011_FEIS | UART011_RTIS | UART011_RXIS, + uap, REG_ICR); + + /* + * Save interrupts enable mask, and enable RX interrupts in case if + * the interrupt is used for NMI entry. + */ + uap->im = pl011_read(uap, REG_IMSC); + pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC); + + if (dev_get_platdata(uap->port.dev)) { + struct amba_pl011_data *plat; + + plat = dev_get_platdata(uap->port.dev); + if (plat->init) + plat->init(); + } + return 0; +} + +/* + * Enable interrupts, only timeouts when using DMA + * if initial RX DMA job failed, start in interrupt mode + * as well. + */ +static void pl011_enable_interrupts(struct uart_amba_port *uap) +{ + unsigned int i; + + spin_lock_irq(&uap->port.lock); + + /* Clear out any spuriously appearing RX interrupts */ + pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR); + + /* + * RXIS is asserted only when the RX FIFO transitions from below + * to above the trigger threshold. If the RX FIFO is already + * full to the threshold this can't happen and RXIS will now be + * stuck off. Drain the RX FIFO explicitly to fix this: + */ + for (i = 0; i < uap->fifosize * 2; ++i) { + if (pl011_read(uap, REG_FR) & UART01x_FR_RXFE) + break; + + pl011_read(uap, REG_DR); + } + + uap->im = UART011_RTIM; + if (!pl011_dma_rx_running(uap)) + uap->im |= UART011_RXIM; + pl011_write(uap->im, uap, REG_IMSC); + spin_unlock_irq(&uap->port.lock); +} + #ifdef CONFIG_CONSOLE_POLL static void pl011_quiesce_irqs(struct uart_port *port) @@ -1639,46 +1713,6 @@ static void pl011_put_poll_char(struct uart_port *port, #endif /* CONFIG_CONSOLE_POLL */ -static int pl011_hwinit(struct uart_port *port) -{ - struct uart_amba_port *uap = - container_of(port, struct uart_amba_port, port); - int retval; - - /* Optionaly enable pins to be muxed in and configured */ - pinctrl_pm_select_default_state(port->dev); - - /* - * Try to enable the clock producer. - */ - retval = clk_prepare_enable(uap->clk); - if (retval) - return retval; - - uap->port.uartclk = clk_get_rate(uap->clk); - - /* Clear pending error and receive interrupts */ - pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS | - UART011_FEIS | UART011_RTIS | UART011_RXIS, - uap, REG_ICR); - - /* - * Save interrupts enable mask, and enable RX interrupts in case if - * the interrupt is used for NMI entry. - */ - uap->im = pl011_read(uap, REG_IMSC); - pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC); - - if (dev_get_platdata(uap->port.dev)) { - struct amba_pl011_data *plat; - - plat = dev_get_platdata(uap->port.dev); - if (plat->init) - plat->init(); - } - return 0; -} - static bool pl011_split_lcrh(const struct uart_amba_port *uap) { return pl011_reg_to_offset(uap, REG_LCRH_RX) != @@ -1707,40 +1741,6 @@ static int pl011_allocate_irq(struct uart_amba_port *uap) return request_irq(uap->port.irq, pl011_int, IRQF_SHARED, "uart-pl011", uap); } -/* - * Enable interrupts, only timeouts when using DMA - * if initial RX DMA job failed, start in interrupt mode - * as well. - */ -static void pl011_enable_interrupts(struct uart_amba_port *uap) -{ - unsigned int i; - - spin_lock_irq(&uap->port.lock); - - /* Clear out any spuriously appearing RX interrupts */ - pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR); - - /* - * RXIS is asserted only when the RX FIFO transitions from below - * to above the trigger threshold. If the RX FIFO is already - * full to the threshold this can't happen and RXIS will now be - * stuck off. Drain the RX FIFO explicitly to fix this: - */ - for (i = 0; i < uap->fifosize * 2; ++i) { - if (pl011_read(uap, REG_FR) & UART01x_FR_RXFE) - break; - - pl011_read(uap, REG_DR); - } - - uap->im = UART011_RTIM; - if (!pl011_dma_rx_running(uap)) - uap->im |= UART011_RXIM; - pl011_write(uap->im, uap, REG_IMSC); - spin_unlock_irq(&uap->port.lock); -} - static int pl011_startup(struct uart_port *port) { struct uart_amba_port *uap =