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[192.237.175.120]) by mx.google.com with ESMTPS id o70si21034558vke.205.2016.05.29.23.12.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 29 May 2016 23:12:41 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1b7GQ9-0008PI-TG; Mon, 30 May 2016 06:11:25 +0000 Received: from mail6.bemta6.messagelabs.com ([85.158.143.247]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1b7GQ9-0008OS-4j for xen-devel@lists.xen.org; Mon, 30 May 2016 06:11:25 +0000 Received: from [85.158.143.35] by server-1.bemta-6.messagelabs.com id 65/D7-30266-C89DB475; Mon, 30 May 2016 06:11:24 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrPIsWRWlGSWpSXmKPExsVyMfTAFt2em97 hBlNfMlos+biYxYHR4+ju30wBjFGsmXlJ+RUJrBnvly1hKjggUHF4onYD42beLkYuDiGBiYwS q1qWM4I4LALzmCUWb1nF2sXIySEh0M8q0fkpDMKOkZiwaC0LhF0lsXrLQaYuRg6gbiWJjgkVE IN+MUqsXnibDaSGTUBF4vubfqg5ZhLnT85kArFFBKQlrn2+zAhiMwtkStz4MpEdxBYWCJY4ef w7WA2LgKrEn2UdYDW8AhYSM79B1EsA7Xp15RjYDZwClhLzF7wBiwsB1fydfpVtAqPgAkaGVYz qxalFZalFukZ6SUWZ6RkluYmZObqGBmZ6uanFxYnpqTmJScV6yfm5mxiBwcYABDsYl/11OsQo ycGkJMrrxuEdLsSXlJ9SmZFYnBFfVJqTWnyIUYaDQ0mCt/MGUE6wKDU9tSItMwcY9jBpCQ4eJ RFeXpA0b3FBYm5xZjpE6hSjMceW39fWMnFsm3pvLZMQS15+XqqUOK8rSKkASGlGaR7cIFg8Xm KUlRLmZQQ6TYinILUoN7MEVf4VozgHo5Iw70SQKTyZeSVw+14BncIEdIrZOS+QU0oSEVJSDYz O05ZP/KAYmT3XMD0l/7XYjdKWHv2qy8tduhdekjzlrqxTErRW/NjLpzKLVNZ8cRZzu3R2gqvo Ka22LttDP1LEDhgGTSpf4TplqoLX+f6TuXtvX9ZQmVK390V61cHMjB1CS0JuJiyy2JBpUiYXN Y3t5ISwB7oRTJZ7/DlOXfou03Ilh7f//z0lluKMREMt5qLiRABGcRJiwgIAAA== X-Env-Sender: wei.chen@linaro.org X-Msg-Ref: server-5.tower-21.messagelabs.com!1464588682!16473139!1 X-Originating-IP: [209.85.192.180] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 8.46; banners=-,-,- X-VirusChecked: Checked Received: (qmail 53933 invoked from network); 30 May 2016 06:11:23 -0000 Received: from mail-pf0-f180.google.com (HELO mail-pf0-f180.google.com) (209.85.192.180) by server-5.tower-21.messagelabs.com with AES128-GCM-SHA256 encrypted SMTP; 30 May 2016 06:11:23 -0000 Received: by mail-pf0-f180.google.com with SMTP id 62so17041398pfd.1 for ; Sun, 29 May 2016 23:11:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uTfBdpYCbH2SAbPjQK18Rt9gNWkNwNzu8kfH+bqu1t0=; b=JeYQDtSkSX412REYAruD4P6qz7P/YKsFt1W/vwbcIiUnuJ3q7xjhDL9Q9f58bahVO+ gNFrHWo2P/lnQzzCkmY2J1yMeGCdWOHzvi9I3M9gghP+KUj5soGbdHfi2B65e9gDbn7G 49X2gLTIr347AgRAeAL+IJeRI50jObi9zu6U4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uTfBdpYCbH2SAbPjQK18Rt9gNWkNwNzu8kfH+bqu1t0=; b=K6Z3VzvedXwAe7EywAfrd790OYU9TB+fYWbUFD8l+zKHfU80eMniL25XwpoktlPQEa XcZ6+JUoWS19gl0EuY/9BSdlGBojKJHoZ4nJu8+ic9BoVgRO0UjfiSjO/Ur2+FTOZ0O1 o3hYGz9u0rpG3q4VlJODCfoA+5/tAL4vhdZbccBinJbi+yDZ0V2QauPlCtAcrBsdhTZx cE5S3bs+V2O2eKhyfuoA5ZC5qmxQhpRSSFHdrf9ykAT2sBD7pEHE49v9s96rPViW3z0h ZF0bS4vJwKrry2uNGncYLSc9SUnkw7Mku6gLYgxbVnyGljdLek7dIiVx3vf/WhcHI9h8 93Tg== X-Gm-Message-State: ALyK8tKkKJt2vF214R/lsqCo4DaMtQCLJDlBuJ/btbQtjXoD18nGpt4SunvLG/CuqO99I/JT X-Received: by 10.98.95.197 with SMTP id t188mr8729335pfb.162.1464588682277; Sun, 29 May 2016 23:11:22 -0700 (PDT) Received: from localhost.members.linode.com ([2400:8900::f03c:91ff:fe56:1324]) by smtp.gmail.com with ESMTPSA id r86sm29679366pfb.21.2016.05.29.23.11.20 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 29 May 2016 23:11:21 -0700 (PDT) From: Wei Chen X-Google-Original-From: Wei Chen To: xen-devel@lists.xen.org Date: Mon, 30 May 2016 14:10:49 +0800 Message-Id: <20160530061050.10771-4-Wei.Chen@linaro.org> X-Mailer: git-send-email 2.9.0.rc0 In-Reply-To: <20160530061050.10771-1-Wei.Chen@linaro.org> References: <20160530061050.10771-1-Wei.Chen@linaro.org> Cc: julien.grall@arm.com, sstabellini@kernel.org, Wei Chen , steve.capper@arm.com Subject: [Xen-devel] [PATCH v3 3/4] xen:arm: arm64: Add correct MPIDR_HWID_MASK value for ARM64 X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" Currently, MPIDR_HWID_MASK is using the bit definition of AArch32 MPIDR register. But from D7.2.67 of ARM ARM (DDI 0487A.i) we can see there are 4 levels of affinity on AArch64 whilst AArch32 has only 3. So, this value is not correct when Xen is running on AArch64. Now, we use the value 0xff00ffffff for this macro on AArch64. But neither of this value and its bitwise invert value can be used in mov instruction with the encoding of {imm16:shift} or {imms:immr}. So we have to use ldr to load the bitwise invert value to register. The details of mov immediate encoding are listed in C4.2.5 of ARM ARM (DDI 0487A.i). Signed-off-by: Wei Chen --- v2-->v3: 1. Add version information of mentioned ARM ARM. v1-->v2: Address Julien's comments 1. Fix typos in commit messages. 2. Explain valid MPIDR_HWID_MASK value in AArch64. 3. Simply explain mov immediate encoding. --- xen/arch/arm/arm64/head.S | 2 +- xen/include/asm-arm/processor.h | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index d5831f2..3090beb 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -270,7 +270,7 @@ common_start: tbz x0, _MPIDR_SMP, 1f /* Multiprocessor extension not supported? */ tbnz x0, _MPIDR_UP, 1f /* Uniprocessor system? */ - mov x13, #(~MPIDR_HWID_MASK) + ldr x13, =(~MPIDR_HWID_MASK) bic x24, x0, x13 /* Mask out flags to get CPU ID */ 1: diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index b4cce7e..284ad6a 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -18,7 +18,11 @@ #define MPIDR_SMP (_AC(1,U) << _MPIDR_SMP) #define MPIDR_AFF0_SHIFT (0) #define MPIDR_AFF0_MASK (_AC(0xff,U) << MPIDR_AFF0_SHIFT) +#ifdef CONFIG_ARM_64 +#define MPIDR_HWID_MASK _AC(0xff00ffffff,UL) +#else #define MPIDR_HWID_MASK _AC(0xffffff,U) +#endif #define MPIDR_INVALID (~MPIDR_HWID_MASK) #define MPIDR_LEVEL_BITS (8)