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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:47 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:43 +0000 Message-Id: <20180305160415.16760-26-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 25/57] ARM: evtchn: Handle level triggered IRQs correctly X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The event channel IRQ has level triggered semantics, however the current VGIC treats everything as edge triggered. To correctly process those IRQs, we have to lower the (virtual) IRQ line at some point in time, depending on whether ther interrupt condition still prevails. Check the per-VCPU evtchn_upcall_pending variable to make the interrupt line match its status, and call this function upon every hypervisor entry. Signed-off-by: Andre Przywara --- Changelog RFC ... v1: - no changes xen/arch/arm/domain.c | 7 +++++++ xen/arch/arm/traps.c | 1 + xen/include/asm-arm/event.h | 1 + 3 files changed, 9 insertions(+) diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index a7bba3ad44..11a46aa27f 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -955,6 +955,13 @@ void vcpu_mark_events_pending(struct vcpu *v) vgic_inject_irq(v->domain, v, v->domain->arch.evtchn_irq, true); } +void vcpu_update_evtchn_irq(struct vcpu *v) +{ + bool pending = vcpu_info(v, evtchn_upcall_pending); + + vgic_inject_irq(v->domain, v, v->domain->arch.evtchn_irq, pending); +} + /* The ARM spec declares that even if local irqs are masked in * the CPSR register, an irq should wake up a cpu from WFI anyway. * For this reason we need to check for irqs that need delivery, diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 0713723bb7..fcf5db50ae 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -2029,6 +2029,7 @@ static void enter_hypervisor_head(struct cpu_user_regs *regs) * triggered interrupts before syncing back the VGIC state. */ vtimer_sync(current); + vcpu_update_evtchn_irq(current); vgic_sync_from_lrs(current); } diff --git a/xen/include/asm-arm/event.h b/xen/include/asm-arm/event.h index c4c79fa87d..eafb2e7f3e 100644 --- a/xen/include/asm-arm/event.h +++ b/xen/include/asm-arm/event.h @@ -6,6 +6,7 @@ void vcpu_kick(struct vcpu *v); void vcpu_mark_events_pending(struct vcpu *v); +void vcpu_update_evtchn_irq(struct vcpu *v); void vcpu_block_unless_event_pending(struct vcpu *v); static inline int vcpu_event_delivery_is_enabled(struct vcpu *v)