From patchwork Fri Mar 9 16:35:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 131161 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp1198371lja; Fri, 9 Mar 2018 08:41:26 -0800 (PST) X-Google-Smtp-Source: AG47ELtZGI4ZlHElo9gKCJm1M+xfsqNGuTQAh8i9DDPU+CrMYOEEQbOF9JTTzKUaTWRLCX5PYtQB X-Received: by 10.107.166.14 with SMTP id p14mr36033325ioe.289.1520613685679; Fri, 09 Mar 2018 08:41:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520613685; cv=none; d=google.com; s=arc-20160816; b=Q9WPGo0kXB9SAmgb0r/gJN82dO1Bz3dB9JAcbNktt1NYGv1FJpcYWgjv/i9FtyBcNn 9rH7fas5n2oZUITtLvxqKMN200aBdkgDUSIaIcDKchThmKc5WnlVC/syel0N+u4sYjGs Yo3jTvyqFzQAz2sHmeCebnRgiZi2Rs7zIdOgKVJbf2uY6dG6kjVHQ63eftb4XBRwBza3 hiCSGI34P8rhb80vzRjWKuA1BWwemrGrwF7EudWcjw60G+riEYPDZ1BNt9OES/m8CCVJ cI370qYG/nvl7YvA6p4E3aCTlsvVVj7d7Y7WEfUzwPzPO3UI6BWjCyTDinhbcLmeUjXE t+Jg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=atgTtWtU4c9+28CP2hggptl+NhblYseEIeRMY2UV0g4=; b=Jk4DT/OH4VPv/bLxaZZepcSgsSTCPnQzqBVcmQfEjUwqqf4S0lzbtXcilb4M5TeD00 0foHktgA/Ww+RZ3eBUtXzYdWxbbjzaTFd0qITkjEfIIZnoRUnm3f3EdSamYxVhf/00oa kiASEcV/2gcvDrGOVXMaqbOafLxQzEWDrLYncVGEo+CzVKXUtQrt1SW8cwyQ1XL5JTM0 4p8CX/WBlFyKs2qut9ik5dJ1UTUxLv5TOid6cMkx6zcWtLJZL8rcZBn7+oeByh2Bl9NG xgTJF1nKU9xGh2vU6xbsz2ENFPZTt0YRKYsT6sDJNeD+uwtoW7h38+V12HQPxIuYQ/DH bLcQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id s3si1159172ioe.131.2018.03.09.08.41.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Mar 2018 08:41:25 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1euL3E-0001YD-Ll; Fri, 09 Mar 2018 16:39:24 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1euL3D-0001XT-Ah for xen-devel@lists.xenproject.org; Fri, 09 Mar 2018 16:39:23 +0000 X-Inumbo-ID: 35cd7af6-23b8-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 35cd7af6-23b8-11e8-b9b1-635ca7ef6cff; Fri, 09 Mar 2018 16:37:51 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 06DC21529; Fri, 9 Mar 2018 08:35:24 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1B84B3F487; Fri, 9 Mar 2018 08:35:22 -0800 (PST) From: julien.grall@arm.com To: xen-devel@lists.xenproject.org Date: Fri, 9 Mar 2018 16:35:10 +0000 Message-Id: <20180309163511.18808-6-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180309163511.18808-1-julien.grall@arm.com> References: <20180309163511.18808-1-julien.grall@arm.com> Cc: andre.przywara@arm.com, Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH 5/6] xen/arm: GIC: Only set pirq in the LR when hw_status is set X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Julien Grall The field pirq should only be valid when the virtual interrupt is associated to a physical interrupt. This change will help to extend gic_lr for supporting specific virtual interrupt field (e.g eoi, source) that clashes with the PIRQ field. Signed-off-by: Julien Grall Reviewed-by: Andre Przywara --- xen/arch/arm/gic-v2.c | 13 ++++++++++--- xen/arch/arm/gic-v3.c | 10 +++++++--- xen/include/asm-arm/gic.h | 2 +- 3 files changed, 18 insertions(+), 7 deletions(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 90d8f652d3..daf8c61258 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -466,20 +466,24 @@ static void gicv2_read_lr(int lr, struct gic_lr *lr_reg) uint32_t lrv; lrv = readl_gich(GICH_LR + lr * 4); - lr_reg->pirq = (lrv >> GICH_V2_LR_PHYSICAL_SHIFT) & GICH_V2_LR_PHYSICAL_MASK; lr_reg->virq = (lrv >> GICH_V2_LR_VIRTUAL_SHIFT) & GICH_V2_LR_VIRTUAL_MASK; lr_reg->priority = (lrv >> GICH_V2_LR_PRIORITY_SHIFT) & GICH_V2_LR_PRIORITY_MASK; lr_reg->pending = (lrv & GICH_V2_LR_PENDING) == GICH_V2_LR_PENDING; lr_reg->active = (lrv & GICH_V2_LR_ACTIVE) == GICH_V2_LR_ACTIVE; lr_reg->hw_status = (lrv & GICH_V2_LR_HW) == GICH_V2_LR_HW; + + if ( lr_reg->hw_status ) + { + lr_reg->pirq = lrv >> GICH_V2_LR_PHYSICAL_SHIFT; + lr_reg->pirq &= GICH_V2_LR_PHYSICAL_MASK; + } } static void gicv2_write_lr(int lr, const struct gic_lr *lr_reg) { uint32_t lrv = 0; - lrv = ( ((lr_reg->pirq & GICH_V2_LR_PHYSICAL_MASK) << GICH_V2_LR_PHYSICAL_SHIFT) | - ((lr_reg->virq & GICH_V2_LR_VIRTUAL_MASK) << GICH_V2_LR_VIRTUAL_SHIFT) | + lrv = (((lr_reg->virq & GICH_V2_LR_VIRTUAL_MASK) << GICH_V2_LR_VIRTUAL_SHIFT) | ((uint32_t)(lr_reg->priority & GICH_V2_LR_PRIORITY_MASK) << GICH_V2_LR_PRIORITY_SHIFT) ); @@ -490,7 +494,10 @@ static void gicv2_write_lr(int lr, const struct gic_lr *lr_reg) lrv |= GICH_V2_LR_PENDING; if ( lr_reg->hw_status ) + { lrv |= GICH_V2_LR_HW; + lrv |= lr_reg->pirq << GICH_V2_LR_PHYSICAL_SHIFT; + } writel_gich(lrv, GICH_LR + lr * 4); } diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 4dbbf0afd2..f73d386df1 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -1006,21 +1006,22 @@ static void gicv3_read_lr(int lr, struct gic_lr *lr_reg) lrv = gicv3_ich_read_lr(lr); - lr_reg->pirq = (lrv >> ICH_LR_PHYSICAL_SHIFT) & ICH_LR_PHYSICAL_MASK; lr_reg->virq = (lrv >> ICH_LR_VIRTUAL_SHIFT) & ICH_LR_VIRTUAL_MASK; lr_reg->priority = (lrv >> ICH_LR_PRIORITY_SHIFT) & ICH_LR_PRIORITY_MASK; lr_reg->pending = (lrv & ICH_LR_STATE_PENDING) == ICH_LR_STATE_PENDING; lr_reg->active = (lrv & ICH_LR_STATE_ACTIVE) == ICH_LR_STATE_ACTIVE; lr_reg->hw_status = (lrv & ICH_LR_HW) == ICH_LR_HW; + + if ( lr_reg->hw_status ) + lr_reg->pirq = (lrv >> ICH_LR_PHYSICAL_SHIFT) & ICH_LR_PHYSICAL_MASK; } static void gicv3_write_lr(int lr_reg, const struct gic_lr *lr) { uint64_t lrv = 0; - lrv = ( ((u64)(lr->pirq & ICH_LR_PHYSICAL_MASK) << ICH_LR_PHYSICAL_SHIFT)| - ((u64)(lr->virq & ICH_LR_VIRTUAL_MASK) << ICH_LR_VIRTUAL_SHIFT) | + lrv = ( ((u64)(lr->virq & ICH_LR_VIRTUAL_MASK) << ICH_LR_VIRTUAL_SHIFT) | ((u64)(lr->priority & ICH_LR_PRIORITY_MASK) << ICH_LR_PRIORITY_SHIFT) ); if ( lr->active ) @@ -1030,7 +1031,10 @@ static void gicv3_write_lr(int lr_reg, const struct gic_lr *lr) lrv |= ICH_LR_STATE_PENDING; if ( lr->hw_status ) + { lrv |= ICH_LR_HW; + lrv |= (uint64_t)lr->pirq << ICH_LR_PHYSICAL_SHIFT; + } /* * When the guest is using vGICv3, all the IRQs are Group 1. Group 0 diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index c32861d4fa..545901b120 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -204,7 +204,7 @@ union gic_state_data { * The LR register format is different for GIC HW version */ struct gic_lr { - /* Physical IRQ */ + /* Physical IRQ -> Only set when hw_status is set. */ uint32_t pirq; /* Virtual IRQ */ uint32_t virq;