From patchwork Thu Mar 15 20:30:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 131867 Delivered-To: patch@linaro.org Received: by 10.46.84.17 with SMTP id i17csp1579557ljb; Thu, 15 Mar 2018 13:33:39 -0700 (PDT) X-Google-Smtp-Source: AG47ELviEanI4mjoTVgwPfVZkrteRO0WM5C2bDA8OpRfHws7NDXnWNIGvue0DwzYLLY+VFbZtIRI X-Received: by 10.107.213.65 with SMTP id x1mr7428404ioc.203.1521146019777; Thu, 15 Mar 2018 13:33:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521146019; cv=none; d=google.com; s=arc-20160816; b=Xq8EAb8O44foyiEhyLqUWTWnzGFl6AdRORCE/a9VKdUXxvya6rl+E1z3RFQn/Xa5pl YqjjEGS8ejrG9AO96o3EOCkhEXtLDi9GKY+jh2NN64sJ5LRKaEJLpxmZxP0ptymYwkvx cLp98+H2oYPIH8egTYQq1Zrj3Tv3FxLxwJg7qZ4gCYiKDVH6+9TpRvzvzbUUot1E7rw4 MItf3t0U7hHLBcfD2kOwwYFQ5pvRZ+5o5XTxZd9pdcj9WvSewd1WHsWCCXkuB4aLQfQo SG7//99vR+NQFNNBsorBEHwpqwSej3QRTVFa3IwCYWrOzqy7W7qgvERyhHIqkJmeLPcL qqug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=zbrkp1eG1WvbLyaKdrTGsUj3xwG5lixcOBYeGbr2ZB8=; b=036zd6Y1d5H8pVGRY9LpHUslLWvQV6uB+WO1nIjvQIByTcDYybTZHvj4aUAUJdaszF p9xzQxlX/NTxqDqtaHFd8JL2E5+qDHqLNfa1P8np9rpzcTe+KoJ4xgGIDHhWN4JmAdm6 ehIA/aiW365UebR5V1+p5qiQB6RAfgC3b4mnaQUoGIr0IVzo3QIbGhUyiUeCl41UlDU0 IU77//mYraYb5D01g5P11Jesk76RPImbXatN+n3SHjJfemMUdahaMDtS1DjdRePhgDMM 2gzDwOeRM7IzUaBEJpcs9uvFrRMn+DFg+J2Dl8nWKIGF4oVRsYJBWmPOswUzTZVkHkSA /9Uw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=LE27TDIK; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id q124-v6si429130itd.47.2018.03.15.13.33.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Mar 2018 13:33:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=LE27TDIK; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ewZWn-00030O-VA; Thu, 15 Mar 2018 20:31:09 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ewZWm-000302-Lo for xen-devel@lists.xenproject.org; Thu, 15 Mar 2018 20:31:08 +0000 X-Inumbo-ID: c671232e-288f-11e8-9728-bc764e045a96 Received: from mail-wm0-x244.google.com (unknown [2a00:1450:400c:c09::244]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id c671232e-288f-11e8-9728-bc764e045a96; Thu, 15 Mar 2018 21:31:02 +0100 (CET) Received: by mail-wm0-x244.google.com with SMTP id 139so12997929wmn.2 for ; Thu, 15 Mar 2018 13:31:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0+Ux+4dfkju/fBjOX8kp0tQc3BP+d+7kn5/p8dINIU4=; b=LE27TDIKKuteNwqbx1s4nNdLWQdCew6M+QiOrIC8LUJ+w3YWCYxNtQf2MADxzbcbqR 1DhTYYMGIS1wcWv/k3C4XBdFEZOlt1Vn2cOFW95AbbFJ8iFDTwCDSgdqlHDlV2K9B9q9 B5WkttxXRK50FGzn09PSwKCc21WqIpbv+Nww8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0+Ux+4dfkju/fBjOX8kp0tQc3BP+d+7kn5/p8dINIU4=; b=D97OzX8SsPSAcq0/6Y2oAYmR1WsnG0Uc/nl7/SrZMAL9kwSLuTdHwsJjAR66HJONS5 0LjnKw06H74rRI2EhS8LOJe5Q1VZ5G4rLsIa0uuioHFV2xAWiQg3M6eZKhVfxlW5/q8R 4AgHqeYOPGXY09VdCoecKOaHZlRUHXAFPDFzJahlNwb9tg0ZkZSbHKxL75IUfm5L7xXQ wVDGRe5jXl2QWOq1DiUr5JoDJl6YK17EkEgaarZyQFLn5q0dTxybLrQDjvquJn1Mqkns xdNhOnLtVSIWxXz/KTsIA7SmQ33ec5YO7o5r2bHhp+9tneySNehae9MxHF2bnjkV0GpZ bY9g== X-Gm-Message-State: AElRT7HzISr1Ww69iPB/LjUtYDju14SsbhYeNCf8E1vzK4GqmXRhPa7W cCvQcHB2LJtppgx6An62YTFlhA== X-Received: by 10.28.66.197 with SMTP id k66mr6161250wmi.58.1521145866005; Thu, 15 Mar 2018 13:31:06 -0700 (PDT) Received: from e104803-lin.lan (mail.andrep.de. [217.160.17.100]) by smtp.gmail.com with ESMTPSA id w125sm3217102wmw.20.2018.03.15.13.31.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 15 Mar 2018 13:31:05 -0700 (PDT) From: Andre Przywara To: Stefano Stabellini , Julien Grall Date: Thu, 15 Mar 2018 20:30:06 +0000 Message-Id: <20180315203050.19791-2-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180315203050.19791-1-andre.przywara@linaro.org> References: <20180315203050.19791-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH v2 01/45] ARM: VGIC: rename gic_event_needs_delivery() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" gic_event_needs_delivery() is not named very intuitively, especially the gic_ prefix is somewhat misleading. Rename it to vgic_vcpu_pending_irq(), which makes it clear that this relates to the virtual GIC and is about interrupts. Also add a VCPU parameter, which makes the code more flexible in the future. The current VGIC expect this to be the current VCPU, so add an assert to spot any regressions. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall Reviewed-by: Stefano Stabellini --- Changelog v1 .. v2: - rename to vgic_vcpu_pending_irq() - add VCPU parameter xen/arch/arm/gic-vgic.c | 16 ++++++++++++++-- xen/include/asm-arm/event.h | 2 +- xen/include/asm-arm/gic.h | 2 +- 3 files changed, 16 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch/arm/gic-vgic.c index ecb07ceb40..61f093db50 100644 --- a/xen/arch/arm/gic-vgic.c +++ b/xen/arch/arm/gic-vgic.c @@ -339,9 +339,18 @@ void gic_clear_pending_irqs(struct vcpu *v) gic_remove_from_lr_pending(v, p); } -int gic_events_need_delivery(void) +/** + * vgic_vcpu_pending_irq() - determine if interrupts need to be injected + * @vcpu: The vCPU on which to check for interrupts. + * + * Checks whether there is an interrupt on the given VCPU which needs + * handling in the guest. This requires at least one IRQ to be pending + * and enabled. + * + * Returns: 1 if the guest should run to handle interrupts, 0 otherwise. + */ +int vgic_vcpu_pending_irq(struct vcpu *v) { - struct vcpu *v = current; struct pending_irq *p; unsigned long flags; const unsigned long apr = gic_hw_ops->read_apr(0); @@ -349,6 +358,9 @@ int gic_events_need_delivery(void) int active_priority; int rc = 0; + /* We rely on reading the VMCR, which is only accessible locally. */ + ASSERT(v == current); + mask_priority = gic_hw_ops->read_vmcr_priority(); active_priority = find_next_bit(&apr, 32, 0); diff --git a/xen/include/asm-arm/event.h b/xen/include/asm-arm/event.h index e8c2a6cb44..c7a415ef57 100644 --- a/xen/include/asm-arm/event.h +++ b/xen/include/asm-arm/event.h @@ -24,7 +24,7 @@ static inline int local_events_need_delivery_nomask(void) * interrupts disabled so this shouldn't be a problem in the general * case. */ - if ( gic_events_need_delivery() ) + if ( vgic_vcpu_pending_irq(current) ) return 1; if ( !vcpu_info(current, evtchn_upcall_pending) ) diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index d568957dd1..49cb94f792 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -238,7 +238,7 @@ int gic_remove_irq_from_guest(struct domain *d, unsigned int virq, extern void vgic_sync_to_lrs(void); extern void gic_clear_pending_irqs(struct vcpu *v); -extern int gic_events_need_delivery(void); +extern int vgic_vcpu_pending_irq(struct vcpu *v); extern void init_maintenance_interrupt(void); extern void gic_raise_guest_irq(struct vcpu *v, unsigned int irq,