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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.33.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:33:17 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:32:24 +0000 Message-Id: <20180321163235.12529-29-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 28/39] ARM: new VGIC: Add event channel IRQ handling X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, Andre Przywara MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The Xen core/arch code relies on two abstracted functions to inject an event channel IRQ and to query its pending state. Implement those to query the state of the new VGIC implementation. Signed-off-by: Andre Przywara Acked-by: Julien Grall Acked-by: Stefano Stabellini --- xen/arch/arm/vgic/vgic.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index 07866d7243..3d818a98ad 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -699,6 +699,29 @@ void vgic_kick_vcpus(struct domain *d) } } +void arch_evtchn_inject(struct vcpu *v) +{ + vgic_inject_irq(v->domain, v, v->domain->arch.evtchn_irq, true); +} + +bool vgic_evtchn_irq_pending(struct vcpu *v) +{ + struct vgic_irq *irq; + unsigned long flags; + bool pending; + + /* Does not work for LPIs. */ + ASSERT(!is_lpi(v->domain->arch.evtchn_irq)); + + irq = vgic_get_irq(v->domain, v, v->domain->arch.evtchn_irq); + spin_lock_irqsave(&irq->irq_lock, flags); + pending = irq_is_pending(irq); + spin_unlock_irqrestore(&irq->irq_lock, flags); + vgic_put_irq(v->domain, irq); + + return pending; +} + struct irq_desc *vgic_get_hw_irq_desc(struct domain *d, struct vcpu *v, unsigned int virq) {