From patchwork Tue Dec 4 20:26:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 152848 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp8503249ljp; Tue, 4 Dec 2018 12:29:15 -0800 (PST) X-Google-Smtp-Source: AFSGD/URFVZx/Za0WHDiYBA3x0Tox8VS8hWV/x6nWsvxtcgyEEL3bGQ7q8m5OL0TivS5StTI3MSD X-Received: by 2002:a25:8e0c:: with SMTP id p12mr4920033ybl.127.1543955355228; Tue, 04 Dec 2018 12:29:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543955355; cv=none; d=google.com; s=arc-20160816; b=g66K3+KOjoGgn0y4Ygn09N/S48kLDPJ2e3M+EvdS3IGrXoyHVwjMYDyZUX91zoN4dO leTO7tMBvBFA7y05f0/rruOibPHrEFf1v9HYRywqX77eq/XfqBalnq0UOxnCClZuKUQ3 Xgz0Dr6lgPyL2psnDeO5oyU/CWJkJQoQM+roHgTl+PN0EYkjSP97a7L/To7NEzaLXWgY AzLZ1op8x5LmEoqgWcuUmvB5KrqgHg6YTxpsxpH4QSm0M0QGl9b8TGtgqV84Z47IaEGP 23ienzJXznlNMbDzSp8gfZcpXXVRUU5lsv4Ofef8pMxFYL70pRHtzYvMo6dnekerZ/gZ 0oug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=TmkIxKLRSpJZMhU+QPf0in+WlSAESKcnR2kh+8bN3ds=; b=VRzhPjPboPoeUfyh6wxgItxYHIMcYo1GbmlFF+F/CDTaO8+zDdZYVrIynVSPoo1zeu sVheWPhsuqGa+Tm+5m51tL9ohgUYX4fPwRP9HZ9vj11dLGyKyI7SB9kr1Z0bhLjFHQ/h MtlC5jtU6w3BtT0aw9dN80a5rMA5xMSq+Y45Pq5s8XT983Q2u7YFztfiXXnH2rtzjsGB qHwzWOWZSpIcwFKpfImzZAuwkFM0qBsLIxSFgCx4UNxSRMGq0Aq2O1T63o90sCrEMPDR yZuOEeu1hRbUQF0trbJDohxmVIx6nkm+IdATRMFY8C/4mN3lVOHqb90eXefY18+j1z6S bKYA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id b66si10678913ywd.460.2018.12.04.12.29.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 04 Dec 2018 12:29:15 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gUHI0-000881-HM; Tue, 04 Dec 2018 20:27:28 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gUHHy-00087K-Sr for xen-devel@lists.xenproject.org; Tue, 04 Dec 2018 20:27:26 +0000 X-Inumbo-ID: 036f5804-f803-11e8-a7ed-d75a0e0d9f14 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id 036f5804-f803-11e8-a7ed-d75a0e0d9f14; Tue, 04 Dec 2018 20:27:26 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 00839165C; Tue, 4 Dec 2018 12:27:26 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 378383F614; Tue, 4 Dec 2018 12:27:25 -0800 (PST) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 4 Dec 2018 20:26:42 +0000 Message-Id: <20181204202651.8836-9-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181204202651.8836-1-julien.grall@arm.com> References: <20181204202651.8836-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH for-4.12 v2 08/17] xen/arm: vsysreg: Add wrapper to handle sysreg access trapped by HCR_EL2.TVM X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" A follow-up patch will require to emulate some accesses to system registers trapped by HCR_EL2.TVM. When set, all NS EL1 writes to the virtual memory control registers will be trapped to the hypervisor. This patch adds the infrastructure to passthrough the access to the host registers. Note that HCR_EL2.TVM will be set in a follow-up patch dynamically. Signed-off-by: Julien Grall --- Changes in v2: - Add missing include vreg.h - Update documentation reference to the lastest one --- xen/arch/arm/arm64/vsysreg.c | 58 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/xen/arch/arm/arm64/vsysreg.c b/xen/arch/arm/arm64/vsysreg.c index 6e60824572..16ac9c344a 100644 --- a/xen/arch/arm/arm64/vsysreg.c +++ b/xen/arch/arm/arm64/vsysreg.c @@ -21,8 +21,49 @@ #include #include #include +#include #include +/* + * Macro to help generating helpers for registers trapped when + * HCR_EL2.TVM is set. + * + * Note that it only traps NS write access from EL1. + */ +#define TVM_REG(reg) \ +static bool vreg_emulate_##reg(struct cpu_user_regs *regs, \ + uint64_t *r, bool read) \ +{ \ + GUEST_BUG_ON(read); \ + WRITE_SYSREG64(*r, reg); \ + \ + return true; \ +} + +/* Defining helpers for emulating sysreg registers. */ +TVM_REG(SCTLR_EL1) +TVM_REG(TTBR0_EL1) +TVM_REG(TTBR1_EL1) +TVM_REG(TCR_EL1) +TVM_REG(ESR_EL1) +TVM_REG(FAR_EL1) +TVM_REG(AFSR0_EL1) +TVM_REG(AFSR1_EL1) +TVM_REG(MAIR_EL1) +TVM_REG(AMAIR_EL1) +TVM_REG(CONTEXTIDR_EL1) + +/* Macro to generate easily case for co-processor emulation */ +#define GENERATE_CASE(reg) \ + case HSR_SYSREG_##reg: \ + { \ + bool res; \ + \ + res = vreg_emulate_sysreg64(regs, hsr, vreg_emulate_##reg); \ + ASSERT(res); \ + break; \ + } + void do_sysreg(struct cpu_user_regs *regs, const union hsr hsr) { @@ -44,6 +85,23 @@ void do_sysreg(struct cpu_user_regs *regs, break; /* + * HCR_EL2.TVM + * + * ARMv8 (DDI 0487D.a): Table D1-38 + */ + GENERATE_CASE(SCTLR_EL1) + GENERATE_CASE(TTBR0_EL1) + GENERATE_CASE(TTBR1_EL1) + GENERATE_CASE(TCR_EL1) + GENERATE_CASE(ESR_EL1) + GENERATE_CASE(FAR_EL1) + GENERATE_CASE(AFSR0_EL1) + GENERATE_CASE(AFSR1_EL1) + GENERATE_CASE(MAIR_EL1) + GENERATE_CASE(AMAIR_EL1) + GENERATE_CASE(CONTEXTIDR_EL1) + + /* * MDCR_EL2.TDRA * * ARMv8 (DDI 0487A.d): D1-1508 Table D1-57