From patchwork Fri Dec 14 11:58:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 153830 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1972933ljp; Fri, 14 Dec 2018 04:01:16 -0800 (PST) X-Google-Smtp-Source: AFSGD/WiAhPxX0XOadsjpBABhOC5ihV0FmItE/+zvUIeRHhcgYCXuans+DON23rh1ILnG48UJvuI X-Received: by 2002:a25:3cc1:: with SMTP id j184mr2494315yba.439.1544788876553; Fri, 14 Dec 2018 04:01:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544788876; cv=none; d=google.com; s=arc-20160816; b=E3zdwUxF/z3NTUXMXeMWzObt+AECp6mrLk7Ff006i31/lq1D2pOKDy0xktOkqySVzk N+SmoUq3qp4ZEEikv87WBdnmjZaaum9bdYvXbHQygQLOfWrf0Fa0aVTz6JtSgLF+b1s5 Mww3/XAYKukyayY1TggyM9JeVC60FwjSfUxXnJjFLoU83EFthYLeMpS5KsFmXituk++R 937zfxkzMV6wEQ+VpzJ6eo8C1rYJeMFfaWqqcajsCasBJSzPVlPePn9h7GGh+MqEMmYA v/ebc/E5B829xA3nY0dlqZqN70/uyfBG+JEZorFoCLPZgU3RABsKET+oY5xmlQXm2TCe tg9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=TmkIxKLRSpJZMhU+QPf0in+WlSAESKcnR2kh+8bN3ds=; b=TeRSZyJg7HesuCtBnFUT2NELuLSkT5vJhgq9JaTXk9cKYSSNuFfy/biqZSPSm52HXA CucRGJWVJvcaK1wwAA12fhWRxkHUt9TA12VFfdsFDjyxzCRehr9DxzCVNaS0oX4KRh7q cmxZEt1ad/5amKXS+HNAl97rA8HTDNMXhCzQEdeDw8BkNwk3z/YHAvq3MEks31ylPL6z 3r3LAV0C+DGOjPlelRASK7Ds4dQoxEKNkxZ4u7gLg5TQgNYJbGiyM9wyN5364/1EmI3B vGRlMZjRjZRomNcMmE6v8Va2GcUB+8esU/fC0Tcw9kqVzyYYosZv/SegQNIOcIYfSOd6 dowA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id f192-v6si2658505yba.423.2018.12.14.04.01.16 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 14 Dec 2018 04:01:16 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gXm7W-0001Hy-QX; Fri, 14 Dec 2018 11:59:06 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gXm7V-0001Hi-DS for xen-devel@lists.xenproject.org; Fri, 14 Dec 2018 11:59:05 +0000 X-Inumbo-ID: a6e9704a-ff97-11e8-8e1d-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id a6e9704a-ff97-11e8-8e1d-bc764e045a96; Fri, 14 Dec 2018 11:59:04 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CC97B1650; Fri, 14 Dec 2018 03:59:03 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0FEAD3F575; Fri, 14 Dec 2018 03:59:02 -0800 (PST) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Fri, 14 Dec 2018 11:58:52 +0000 Message-Id: <20181214115855.6713-3-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181214115855.6713-1-julien.grall@arm.com> References: <20181214115855.6713-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH for-4.12 v3 2/5] xen/arm: vsysreg: Add wrapper to handle sysreg access trapped by HCR_EL2.TVM X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" A follow-up patch will require to emulate some accesses to system registers trapped by HCR_EL2.TVM. When set, all NS EL1 writes to the virtual memory control registers will be trapped to the hypervisor. This patch adds the infrastructure to passthrough the access to the host registers. Note that HCR_EL2.TVM will be set in a follow-up patch dynamically. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- Changes in v2: - Add missing include vreg.h - Update documentation reference to the lastest one --- xen/arch/arm/arm64/vsysreg.c | 58 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/xen/arch/arm/arm64/vsysreg.c b/xen/arch/arm/arm64/vsysreg.c index 6e60824572..16ac9c344a 100644 --- a/xen/arch/arm/arm64/vsysreg.c +++ b/xen/arch/arm/arm64/vsysreg.c @@ -21,8 +21,49 @@ #include #include #include +#include #include +/* + * Macro to help generating helpers for registers trapped when + * HCR_EL2.TVM is set. + * + * Note that it only traps NS write access from EL1. + */ +#define TVM_REG(reg) \ +static bool vreg_emulate_##reg(struct cpu_user_regs *regs, \ + uint64_t *r, bool read) \ +{ \ + GUEST_BUG_ON(read); \ + WRITE_SYSREG64(*r, reg); \ + \ + return true; \ +} + +/* Defining helpers for emulating sysreg registers. */ +TVM_REG(SCTLR_EL1) +TVM_REG(TTBR0_EL1) +TVM_REG(TTBR1_EL1) +TVM_REG(TCR_EL1) +TVM_REG(ESR_EL1) +TVM_REG(FAR_EL1) +TVM_REG(AFSR0_EL1) +TVM_REG(AFSR1_EL1) +TVM_REG(MAIR_EL1) +TVM_REG(AMAIR_EL1) +TVM_REG(CONTEXTIDR_EL1) + +/* Macro to generate easily case for co-processor emulation */ +#define GENERATE_CASE(reg) \ + case HSR_SYSREG_##reg: \ + { \ + bool res; \ + \ + res = vreg_emulate_sysreg64(regs, hsr, vreg_emulate_##reg); \ + ASSERT(res); \ + break; \ + } + void do_sysreg(struct cpu_user_regs *regs, const union hsr hsr) { @@ -44,6 +85,23 @@ void do_sysreg(struct cpu_user_regs *regs, break; /* + * HCR_EL2.TVM + * + * ARMv8 (DDI 0487D.a): Table D1-38 + */ + GENERATE_CASE(SCTLR_EL1) + GENERATE_CASE(TTBR0_EL1) + GENERATE_CASE(TTBR1_EL1) + GENERATE_CASE(TCR_EL1) + GENERATE_CASE(ESR_EL1) + GENERATE_CASE(FAR_EL1) + GENERATE_CASE(AFSR0_EL1) + GENERATE_CASE(AFSR1_EL1) + GENERATE_CASE(MAIR_EL1) + GENERATE_CASE(AMAIR_EL1) + GENERATE_CASE(CONTEXTIDR_EL1) + + /* * MDCR_EL2.TDRA * * ARMv8 (DDI 0487A.d): D1-1508 Table D1-57