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[192.237.175.120]) by mx.google.com with ESMTPS id r186si5797543ywg.107.2019.03.27.11.47.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Mar 2019 11:47:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1h9DYi-0001kp-2S; Wed, 27 Mar 2019 18:45:56 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1h9DYh-0001kO-A2 for xen-devel@lists.xenproject.org; Wed, 27 Mar 2019 18:45:55 +0000 X-Inumbo-ID: 8d201b26-50c0-11e9-bc90-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 8d201b26-50c0-11e9-bc90-bc764e045a96; Wed, 27 Mar 2019 18:45:54 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2DDE41596; Wed, 27 Mar 2019 11:45:54 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EE6DA3F557; Wed, 27 Mar 2019 11:45:52 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Wed, 27 Mar 2019 18:45:27 +0000 Message-Id: <20190327184531.30986-9-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190327184531.30986-1-julien.grall@arm.com> References: <20190327184531.30986-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 08/12] xen/arm: cpufeature: Match register size with value size in cpus_have_const_cap X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Artem_Mygaiev@epam.com, Oleksandr_Tyshchenko@epam.com, Julien Grall , sstabellini@kernel.org, Andrii_Anisov@epam.com MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Clang is pickier than GCC for the register size in asm statement. It expects the register size to match the value size. The asm statement expects a 32-bit (resp. 64-bit) value on Arm32 (resp. Arm64) whereas the value is a boolean (Clang consider to be 32-bit). It would be possible to impose 32-bit register for both architecture but this require the code to use __OP32. However, it does no really improve the assembly generated. Instead, replace switch the variable to use register_t. Signed-off-by: Julien Grall --- xen/include/asm-arm/cpufeature.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/include/asm-arm/cpufeature.h b/xen/include/asm-arm/cpufeature.h index c2c8f3417c..d06f09ecfa 100644 --- a/xen/include/asm-arm/cpufeature.h +++ b/xen/include/asm-arm/cpufeature.h @@ -67,7 +67,7 @@ static inline bool cpus_have_cap(unsigned int num) /* System capability check for constant cap */ #define cpus_have_const_cap(num) ({ \ - bool __ret; \ + register_t __ret; \ \ asm volatile (ALTERNATIVE("mov %0, #0", \ "mov %0, #1", \