From patchwork Tue May 14 12:11:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 164137 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp2540668ili; Tue, 14 May 2019 05:13:04 -0700 (PDT) X-Google-Smtp-Source: APXvYqy5WfrddjTH2bXK46K/vtMehd9svnZGwYGiFneJFnRg3Q2GIgbbS7eBfq4Nkg2EQq/L1DEb X-Received: by 2002:a24:4a81:: with SMTP id k123mr3426384itb.159.1557835984148; Tue, 14 May 2019 05:13:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557835984; cv=none; d=google.com; s=arc-20160816; b=XYDzZG+GS40aB++M8zrwqKTd1cZ0Sczh5ZpIwC46CcuN5J6hleh4GyQJ4i653/MoCj BaXiDPAE+0aOgQ6ZUhEkAfZEVWUevVqYmSrB7Na7/OkftqwpUNbRwzEnPxLrJ8OzyFrE IGA1J3KLmmdUK3smxfDgVLYQnCwo2Yix5UbIEcDTpFeAWsesShT1fqgyLsQzGelXm55X rnyCpoi9Ligl4f7RQZW2B2bkAoktt6tnC4Y0ftSQ2ILtQk+HrBQWg228U4RPngV3SKEM 33ekHKVjxvBdfL4Vj1mOSCFEE/XUxjTFraKX6POSflYlTJzShs1zNWX903yo+5UBzAKx MBCw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=l7IMz6SmFkbIDcRqmOwsxEm6qLyqX/4jEzjnX1BC1qQ=; b=uOm0uTKap/aYJQHkdXuRLaMsGkzJq2araOqZ/o4AFggUzD0B3ZytBBrBMg2Q3YwR5H Ootda/DYy7V9OckzH/yihmN0l6xcIEKzrOFDY4GEGWXyfQOU/as1p8xNJjA+zJI+48AT 6ru0YzSpGZnOgoNZV6cU8rsLmNzjQ+y1FFKVgRj2PA/yopAzeWEeo1Za2TVbFet+1BNp W8K6bjJh1i4AbzeW0+3oH72YwSMEtVpYjV1DKSH7fbe2sjQ5ntpI21HkiP+2eAfpG8Y4 uTfsJv0+G9hxRz/LItBHG5CjXOjJihCIqFBQb2GVgdnEy20eg57qLPq7F+JR9MeEoL2S t/JA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id p20si11327314jam.1.2019.05.14.05.13.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 14 May 2019 05:13:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWHX-0006EB-Od; Tue, 14 May 2019 12:11:43 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWHV-0006DS-O4 for xen-devel@lists.xenproject.org; Tue, 14 May 2019 12:11:41 +0000 X-Inumbo-ID: 6e6b95e8-7641-11e9-8980-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 6e6b95e8-7641-11e9-8980-bc764e045a96; Tue, 14 May 2019 12:11:40 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A10CC15AB; Tue, 14 May 2019 05:11:40 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 905D03F71E; Tue, 14 May 2019 05:11:39 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 14 May 2019 13:11:25 +0100 Message-Id: <20190514121132.26732-2-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190514121132.26732-1-julien.grall@arm.com> References: <20190514121132.26732-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH MM-PART1 v3 1/8] xen/arm: Don't boot Xen on platform using AIVIVT instruction caches X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Oleksandr_Tyshchenko@epam.com, Julien Grall , Stefano Stabellini , Andrii_Anisov@epam.com MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The AIVIVT is a type of instruction cache available on Armv7. This is the only cache not implementing the IVIPT extension and therefore requiring specific care. To simplify maintenance requirements, Xen will not boot on platform using AIVIVT cache. This should not be an issue because Xen Arm32 can only boot on a small number of processors (see arch/arm/arm32/proc-v7.S). All of them are not using AIVIVT cache. Signed-off-by: Julien Grall Acked-by: Stefano Stabellini --- Changes in v3: - Patch added --- xen/arch/arm/setup.c | 5 +++++ xen/include/asm-arm/processor.h | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c index ccb0f181ea..faaf029b99 100644 --- a/xen/arch/arm/setup.c +++ b/xen/arch/arm/setup.c @@ -526,10 +526,15 @@ static void __init setup_mm(unsigned long dtb_paddr, size_t dtb_size) unsigned long boot_mfn_start, boot_mfn_end; int i; void *fdt; + const uint32_t ctr = READ_CP32(CTR); if ( !bootinfo.mem.nr_banks ) panic("No memory bank\n"); + /* We only supports instruction caches implementing the IVIPT extension. */ + if ( ((ctr >> CTR_L1Ip_SHIFT) & CTR_L1Ip_MASK) == CTR_L1Ip_AIVIVT ) + panic("AIVIVT instruction cache not supported\n"); + init_pdx(); ram_start = bootinfo.mem.bank[0].start; diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index b5f515805d..04b05b3f39 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -6,6 +6,11 @@ #endif #include +/* CTR Cache Type Register */ +#define CTR_L1Ip_MASK 0x3 +#define CTR_L1Ip_SHIFT 14 +#define CTR_L1Ip_AIVIVT 0x1 + /* MIDR Main ID Register */ #define MIDR_REVISION_MASK 0xf #define MIDR_RESIVION(midr) ((midr) & MIDR_REVISION_MASK)