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[192.237.175.120]) by mx.google.com with ESMTPS id b81si185867itb.103.2019.06.10.12.33.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 10 Jun 2019 12:33:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1haQ20-0007kt-BS; Mon, 10 Jun 2019 19:32:36 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1haQ1z-0007kH-Gp for xen-devel@lists.xenproject.org; Mon, 10 Jun 2019 19:32:35 +0000 X-Inumbo-ID: 7ea70a16-8bb6-11e9-a861-33f576285945 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id 7ea70a16-8bb6-11e9-a861-33f576285945; Mon, 10 Jun 2019 19:32:33 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7E7C2C0A; Mon, 10 Jun 2019 12:32:33 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 965C33F73C; Mon, 10 Jun 2019 12:32:32 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Mon, 10 Jun 2019 20:32:10 +0100 Message-Id: <20190610193215.23704-13-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190610193215.23704-1-julien.grall@arm.com> References: <20190610193215.23704-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 12/17] xen/arm64: head: Move assembly switch to the runtime PT in secondary CPUs path X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: andre.przywara@arm.com, Julien Grall , Stefano Stabellini , andrii_anisov@epam.com, Oleksandr_Tyshchenko@epam.com MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The assembly switch to the runtime PT is only necessary for the secondary CPUs. So move the code in the secondary CPUs path. While this is definitely not compliant with the Arm Arm as we are switching between two differents set of page-tables without turning off the MMU. Turning off the MMU is impossible here as the ID map may clash with other mappings in the runtime page-tables. This will require more rework to avoid the problem. So for now add a TODO in the code. Signed-off-by: Julien Grall Acked-by: Stefano Stabellini --- xen/arch/arm/arm64/head.S | 33 +++++++++++++++++---------------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index d673f7c0d8..6be4af7579 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -344,6 +344,23 @@ GLOBAL(init_secondary) br x0 secondary_switched: bl setup_fixmap + + /* + * Non-boot CPUs need to move on to the proper pagetables, which were + * setup in init_secondary_pagetables. + * + * XXX: This is not compliant with the Arm Arm. + */ + ldr x4, =init_ttbr /* VA of TTBR0_EL2 stashed by CPU 0 */ + ldr x4, [x4] /* Actual value */ + dsb sy + msr TTBR0_EL2, x4 + dsb sy + isb + tlbi alle2 + dsb sy /* Ensure completion of TLB flush */ + isb + b launch ENDPROC(init_secondary) @@ -657,22 +674,6 @@ ENDPROC(setup_fixmap) launch: PRINT("- Ready -\r\n") - /* The boot CPU should go straight into C now */ - cbz x22, launch - - /* Non-boot CPUs need to move on to the proper pagetables, which were - * setup in init_secondary_pagetables. */ - - ldr x4, =init_ttbr /* VA of TTBR0_EL2 stashed by CPU 0 */ - ldr x4, [x4] /* Actual value */ - dsb sy - msr TTBR0_EL2, x4 - dsb sy - isb - tlbi alle2 - dsb sy /* Ensure completion of TLB flush */ - isb - ldr x0, =init_data add x0, x0, #INITINFO_stack /* Find the boot-time stack */ ldr x0, [x0]