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[192.237.175.120]) by mx.google.com with ESMTPS id n17si7168973jam.99.2019.06.10.12.33.33 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 10 Jun 2019 12:33:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1haQ26-0007tl-9L; Mon, 10 Jun 2019 19:32:42 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1haQ24-0007q8-5Z for xen-devel@lists.xenproject.org; Mon, 10 Jun 2019 19:32:40 +0000 X-Inumbo-ID: 81f53be7-8bb6-11e9-8980-bc764e045a96 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 81f53be7-8bb6-11e9-8980-bc764e045a96; Mon, 10 Jun 2019 19:32:39 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1740C346; Mon, 10 Jun 2019 12:32:39 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2F32B3F73C; Mon, 10 Jun 2019 12:32:38 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Mon, 10 Jun 2019 20:32:15 +0100 Message-Id: <20190610193215.23704-18-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190610193215.23704-1-julien.grall@arm.com> References: <20190610193215.23704-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 17/17] xen/arm64: Zero BSS after the MMU and D-cache is turned on X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: andre.przywara@arm.com, Julien Grall , Stefano Stabellini , andrii_anisov@epam.com, Oleksandr_Tyshchenko@epam.com MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" At the moment BSS is zeroed before the MMU and D-Cache is turned on. In other words, the cache will be bypassed when zeroing the BSS section. Per the Image protocol [1], the state of the cache for BSS region is not known because it is not part of the "loaded kernel image". This means that the cache will need to be invalidated twice for the BSS region: 1) Before zeroing to remove any dirty cache line. Otherwise they may get evicted while zeroing and therefore overriding the value. 2) After zeroing to remove any cache line that may have been speculated. Otherwise when turning on MMU and D-Cache, the CPU may see old values. However, the only reason to have the BSS zeroed early is because the boot page tables are part of BSS. To avoid the two cache invalidations, it is possible to move the page tables in the section .data.page_aligned. A new macro DEFINE_BOOT_PAGE_TABLE is introduced to create and mark page-tables used before BSS is zeroed. This includes all boot_* but also xen_fixmap as zero_bss() will print a message when earlyprintk is enabled. [1] linux/Documentation/arm64/booting.txt Acked-by: Stefano Stabellini --- Note that the arm32 support is not there yet. This will need to be addressed here or separately depending on when the Arm32 boot rework is sent. --- xen/arch/arm/arm64/head.S | 6 +++--- xen/arch/arm/mm.c | 23 +++++++++++++++++------ 2 files changed, 20 insertions(+), 9 deletions(-) diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index 130ab66d8e..6c3edbbc81 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -291,7 +291,6 @@ real_start_efi: mov x22, #0 /* x22 := is_secondary_cpu */ bl check_cpu_mode - bl zero_bss bl cpu_init bl create_page_tables bl enable_mmu @@ -312,6 +311,7 @@ primary_switched: /* Use a virtual address to access the UART. */ ldr x23, =EARLY_UART_VIRTUAL_ADDRESS #endif + bl zero_bss PRINT("- Ready -\r\n") /* Setup the arguments for start_xen and jump to C world */ mov x0, x20 /* x0 := phys_offset */ @@ -423,8 +423,8 @@ zero_bss: cbnz x26, skip_bss PRINT("- Zero BSS -\r\n") - load_paddr x0, __bss_start /* Load paddr of start & end of bss */ - load_paddr x1, __bss_end + ldr x0, =__bss_start /* x0 := vaddr(__bss_start) */ + ldr x1, =__bss_end /* x1 := vaddr(__bss_start) */ 1: str xzr, [x0], #8 cmp x0, x1 diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index 6a549e9283..0b2d07a258 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -48,6 +48,17 @@ #undef mfn_to_virt #define mfn_to_virt(mfn) __mfn_to_virt(mfn_x(mfn)) +/* + * Macros to define page-tables: + * - DEFINE_BOOT_PAGE_TABLE is used to define page-table that are used + * in assembly code before BSS is zeroed. + * - DEFINE_PAGE_TABLE{,S} are used to define one or multiple + * page-tables to be used after BSS is zeroed (typically they are only used + * in C). + */ +#define DEFINE_BOOT_PAGE_TABLE(name) \ +lpae_t __aligned(PAGE_SIZE) __section(".data.page_aligned") name[LPAE_ENTRIES] + #define DEFINE_PAGE_TABLES(name, nr) \ lpae_t __aligned(PAGE_SIZE) name[LPAE_ENTRIES * (nr)] @@ -76,13 +87,13 @@ lpae_t __aligned(PAGE_SIZE) name[LPAE_ENTRIES * (nr)] * Finally, if EARLY_PRINTK is enabled then xen_fixmap will be mapped * by the CPU once it has moved off the 1:1 mapping. */ -DEFINE_PAGE_TABLE(boot_pgtable); +DEFINE_BOOT_PAGE_TABLE(boot_pgtable); #ifdef CONFIG_ARM_64 -DEFINE_PAGE_TABLE(boot_first); -DEFINE_PAGE_TABLE(boot_first_id); +DEFINE_BOOT_PAGE_TABLE(boot_first); +DEFINE_BOOT_PAGE_TABLE(boot_first_id); #endif -DEFINE_PAGE_TABLE(boot_second); -DEFINE_PAGE_TABLE(boot_third); +DEFINE_BOOT_PAGE_TABLE(boot_second); +DEFINE_BOOT_PAGE_TABLE(boot_third); /* Main runtime page tables */ @@ -135,7 +146,7 @@ static __initdata int xenheap_first_first_slot = -1; */ static DEFINE_PAGE_TABLES(xen_second, 2); /* First level page table used for fixmap */ -DEFINE_PAGE_TABLE(xen_fixmap); +DEFINE_BOOT_PAGE_TABLE(xen_fixmap); /* First level page table used to map Xen itself with the XN bit set * as appropriate. */ static DEFINE_PAGE_TABLE(xen_xenmap);