From patchwork Mon Aug 12 17:30:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 171097 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3120016ily; Mon, 12 Aug 2019 10:31:38 -0700 (PDT) X-Google-Smtp-Source: APXvYqyOPWHdliztBdzG209/fNIIe6ce5LYu+rnj72TYzOn5IZ3ofNZsmK5YB7a+w6ca7lOb2wYb X-Received: by 2002:a05:6638:113:: with SMTP id x19mr18868032jao.83.1565631097967; Mon, 12 Aug 2019 10:31:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1565631097; cv=none; d=google.com; s=arc-20160816; b=fIdL6IMhuKvThPzE8QoDlrXicUH2o9uAyZfm/yUrUoxGB/xAATw8XjB+hanmtc7vOY 9PBxT40ASY0HkzIw5TMCG8LZFLBKq24Bbr+7UfMOwI81sXW3h/43IdzVrYCxIrLHRuxf ytELboNL8HdVPXL+blSxMpv0pjV+KEkTcW8x5CFND1/FqNj7q5bOt3f6VaQafkkTMngr Q907DGVEOu3Cl6Uq6iKR0qzYIbeVHfpkCmvl258rst4oOq8LEjnT2qUiM1NiPdQmc33X BDFvCeb3qb4uef88iboU13tQSI8x61P7XAyqzOkRK5XIfoad1EvAgeOD/D/Owj00pPCv k4SA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=key0p2HeXqhGi80mjYVIrqmvSBp0HUbWEpXOsRB2apQ=; b=N/9LPTZjzezCxsQ0tzvCVaePYCjOxXtz6Hdde7YPQtdhTVANiMTjZRYYaLMnIi2Nrp 8TXKY9YZcxwV2d+M4cBbZMKbQ78YTyCDPs40l6islNfTCRKcy5uoIyTY7RagfvlwHv1z y2N10TTl3VGPirilbkc1l92lRhLNOKZTf9vFr9xdjO6LP3khvC2RsNP9LFwrIjgA3dPm 48/Ej6UXpWwbVOBNgKSnEr06uUFLXgb5Zgd/gy4Ce3EKXtoiK62QzBATHfw0NnObSPyj Z2RgJ1wQzii6pC9d8QIOlNIM4x5IiwOaUIa1mwZuudBJu4W7b1ltQZApO91x3O/vS6VC 8DYA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id t11si17427704jai.13.2019.08.12.10.31.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 12 Aug 2019 10:31:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hxE9g-0006uN-EE; Mon, 12 Aug 2019 17:30:48 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hxE9e-0006sA-Be for xen-devel@lists.xenproject.org; Mon, 12 Aug 2019 17:30:46 +0000 X-Inumbo-ID: ea9bd597-bd26-11e9-8980-bc764e045a96 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id ea9bd597-bd26-11e9-8980-bc764e045a96; Mon, 12 Aug 2019 17:30:45 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 55D921993; Mon, 12 Aug 2019 10:30:45 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A3B8F3F706; Mon, 12 Aug 2019 10:30:44 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Mon, 12 Aug 2019 18:30:11 +0100 Message-Id: <20190812173019.11956-21-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190812173019.11956-1-julien.grall@arm.com> References: <20190812173019.11956-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH v3 20/28] xen/arm32: head: Remove 1:1 mapping as soon as it is not used X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , Stefano Stabellini , Volodymyr Babchuk MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The 1:1 mapping may clash with other parts of the Xen virtual memory layout. At the moment, Xen is handling the clash by only creating a mapping to the runtime virtual address before enabling the MMU. The rest of the mappings (such as the fixmap) will be mapped after the MMU is enabled. However, the code doing the mapping is not safe as it replace mapping without using the Break-Before-Make sequence. As the 1:1 mapping can be anywhere in the memory, it is easier to remove all the entries added as soon as the 1:1 mapping is not used rather than adding the Break-Before-Make sequence everywhere. It is difficult to track where exactly the 1:1 mapping was created without a full rework of create_page_tables(). Instead, introduce a new function remove_identity_mapping() will look where is the top-level entry for the 1:1 mapping and remove it. The new function is only called for the boot CPU. Secondary CPUs will switch directly to the runtime page-tables so there are no need to remove the 1:1 mapping. Note that this still doesn't make the Secondary CPUs path safe but it is not making it worst. Signed-off-by: Julien Grall --- It is very likely we will need to re-introduce the 1:1 mapping to cater secondary CPUs boot and suspend/resume. For now, the attempt is to make boot CPU path fully Arm Arm compliant. Changes in v3: - Remove unused label - Avoid harcoding slots Changes in v2: - Patch added --- xen/arch/arm/arm32/head.S | 86 +++++++++++++++++++++++++++++++++++++---------- 1 file changed, 69 insertions(+), 17 deletions(-) diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S index 8f945d318a..34fc9ffcee 100644 --- a/xen/arch/arm/arm32/head.S +++ b/xen/arch/arm/arm32/head.S @@ -32,6 +32,10 @@ #define PT_UPPER(x) (PT_##x & 0xf00) #define PT_LOWER(x) (PT_##x & 0x0ff) +/* Convenience defines to get slot used by Xen mapping. */ +#define XEN_FIRST_SLOT first_table_offset(XEN_VIRT_START) +#define XEN_SECOND_SLOT second_table_offset(XEN_VIRT_START) + #if (defined (CONFIG_EARLY_PRINTK)) && (defined (EARLY_PRINTK_INC)) #include EARLY_PRINTK_INC #endif @@ -158,6 +162,13 @@ past_zImage: ldr r0, =primary_switched mov pc, r0 primary_switched: + /* + * The 1:1 map may clash with other parts of the Xen virtual memory + * layout. As it is not used anymore, remove it completely to + * avoid having to worry about replacing existing mapping + * afterwards. + */ + bl remove_identity_mapping bl setup_fixmap #ifdef CONFIG_EARLY_PRINTK /* Use a virtual address to access the UART. */ @@ -474,12 +485,63 @@ enable_mmu: mov pc, lr ENDPROC(enable_mmu) -setup_fixmap: +/* + * Remove the 1:1 map for the page-tables. It is not easy to keep track + * where the 1:1 map was mapped, so we will look for the top-level entry + * exclusive to the 1:1 map and remove it. + * + * Inputs: + * r9 : paddr(start) + * + * Clobbers r0 - r3 + */ +remove_identity_mapping: + /* r2:r3 := invalid page-table entry */ + mov r2, #0x0 + mov r3, #0x0 /* - * Now we can install the fixmap and dtb mappings, since we - * don't need the 1:1 map any more + * Find the first slot used. Remove the entry for the first + * table if the slot is not XEN_FIRST_SLOT. For slot XEN_FIRST_SLOT, + * the 1:1 mapping was done in the second table. */ - dsb + lsr r1, r9, #FIRST_SHIFT + mov_w r0, LPAE_ENTRY_MASK + and r1, r1, r0 /* r1 := first slot */ + cmp r1, #XEN_FIRST_SLOT + beq 1f + /* It is not in slot 0, remove the entry */ + ldr r0, =boot_pgtable /* r0 := root table */ + lsl r1, r1, #3 /* r1 := Slot offset */ + strd r2, r3, [r0, r1] + b identity_mapping_removed + +1: + /* + * Find the second slot used. Remove the entry for the first + * table if the slot is not XEN_SECOND_SLOT. For slot XEN_SECOND_SLOT, + * it means the 1:1 mapping was not created. + */ + lsr r1, r9, #SECOND_SHIFT + mov_w r0, LPAE_ENTRY_MASK + and r1, r1, r0 /* r1 := second slot */ + cmp r1, #XEN_SECOND_SLOT + beq identity_mapping_removed + /* It is not in slot 1, remove the entry */ + ldr r0, =boot_second /* r0 := second table */ + lsl r1, r1, #3 /* r1 := Slot offset */ + strd r2, r3, [r0, r1] + +identity_mapping_removed: + /* See asm-arm/arm32/flushtlb.h for the explanation of the sequence. */ + dsb nshst + mcr CP32(r0, TLBIALLH) + dsb nsh + isb + + mov pc, lr +ENDPROC(remove_identity_mapping) + +setup_fixmap: #if defined(CONFIG_EARLY_PRINTK) /* Fixmap is only used by early printk */ /* Add UART to the fixmap table */ ldr r1, =xen_fixmap /* r1 := vaddr (xen_fixmap) */ @@ -489,7 +551,6 @@ setup_fixmap: orr r2, r2, #PT_LOWER(DEV_L3) /* r2:r3 := 4K dev map including UART */ mov r3, #0x0 strd r2, r3, [r1, #(FIXMAP_CONSOLE*8)] /* Map it in the first fixmap's slot */ -1: /* Map fixmap into boot_second */ ldr r1, =boot_second /* r1 := vaddr (boot_second) */ @@ -501,19 +562,10 @@ setup_fixmap: mov r4, r4, lsr #(SECOND_SHIFT - 3) /* r4 := Slot for FIXMAP(0) */ mov r3, #0x0 strd r2, r3, [r1, r4] /* Map it in the fixmap's slot */ -#endif - - /* - * Flush the TLB in case the 1:1 mapping happens to clash with - * the virtual addresses used by the fixmap or DTB. - */ - dsb /* Ensure any page table updates made above - * have occurred. */ - isb - mcr CP32(r0, TLBIALLH) /* Flush hypervisor TLB */ - dsb /* Ensure completion of TLB flush */ - isb + /* Ensure any page table updates made above have occurred. */ + dsb nshst +#endif mov pc, lr ENDPROC(setup_fixmap)