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[209.85.220.41]) by mx.google.com with SMTPS id na7sor6420658pjb.22.2021.10.14.00.26.42 for (Google Transport Security); Thu, 14 Oct 2021 00:26:42 -0700 (PDT) Received-SPF: pass (google.com: domain of sumit.garg@linaro.org designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NE5md1Eb; spf=pass (google.com: domain of sumit.garg@linaro.org designates 209.85.220.41 as permitted sender) smtp.mailfrom=sumit.garg@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=o/ihjVhEyFVt5hRFiCCjoBklsGrWdBtHp+Qld8OwdOk=; b=NE5md1EbLnU/B+5Mb/gZbdJiOpo+MQ8OLx72bhvKKipWEFAkaTUFZonUT7UndWJSkc cp4qG+XyV+le/5eIhjDblSaPasrnlkvakwRGR/h1ZHm23PpSNiMqlkSQ6Jt/yGUj/8cq XIPITfz7Odr4tT3LLdvhJ65aKIK5sjPmue7kXqSgBbZG8yjf7LExS5oaIgZSCSLI8jIs Z3FDhTD5V9dcbV9h2bRUT2vOmkgyhVLuhK3IG28NXg+KswVtub0sZuJTkWrbLox/CfKj SJwnTjkgCOS3yTcA+3j+W8hrutE9GTX8nL0eqZrpspMs/Pe7h1N7ZSXu+vPTNomtzhBv 47yA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=o/ihjVhEyFVt5hRFiCCjoBklsGrWdBtHp+Qld8OwdOk=; b=0tIs21z1k0pBP3m+3tIcrQLkJriC0e/qcfl7uQBaYM+5l9XmH1rjqqA1rE3mEOZuoS 4YyG42P8xzSvVuHttX0QldNX83/D/mLwtkFhWFIjwnORvbOkWzJ6CkJ081s4zQCSIz0j gRdkM96ucZtOCSOFnYAF/PD+tWm0fWPGDczQuJ6gE0Kl9dyvvvIayjvCziKzkM8RbV/K xEuAPfDvdxqGCunObc1rOLPvJLhVR5mCX6RQJ7w1U8h846Ik3Cx1cqqHbnJmxemqUAtd 6FjSgfr49oq2CdNXYUSdHYP3+T0EsQsVP9m3tQrPB62RJP661tnwhZ131k2QhR+ZiGz3 WSUA== X-Gm-Message-State: AOAM530+waKZqzOlxL304a8QLeNZFOimsuDpirGcuYJ9FJhrv7cBQcp3 qD54OqZShcUwiRjxReLcmiHe0P/viMUUEsV1QMI= X-Google-Smtp-Source: ABdhPJy4uBwbauwYpJ122iNFcqgM+M160Y7a9s21auKjr2ZXZ1GisBwa1SnkNFJeFgIoVtaaENpyxg== X-Received: by 2002:a17:90a:ac03:: with SMTP id o3mr4561591pjq.130.1634196401841; Thu, 14 Oct 2021 00:26:41 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([223.178.212.208]) by smtp.gmail.com with ESMTPSA id s8sm1454377pfh.186.2021.10.14.00.26.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 00:26:40 -0700 (PDT) From: Sumit Garg To: sumit.garg@linaro.org Cc: patches@linaro.org Subject: [PATCH] arm64: Enable perf events based hard lockup detector Date: Thu, 14 Oct 2021 12:56:32 +0530 Message-Id: <20211014072632.23796-1-sumit.garg@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 With the recent feature added to enable perf events to use pseudo NMIs as interrupts on platforms which support GICv3 or later, its now been possible to enable hard lockup detector (or NMI watchdog) on arm64 platforms. So enable corresponding support. One thing to note here is that normally lockup detector is initialized just after the early initcalls but PMU on arm64 comes up much later as device_initcall(). So we need to re-initialize lockup detection once PMU has been initialized. Signed-off-by: Sumit Garg --- arch/arm64/Kconfig | 2 ++ arch/arm64/kernel/perf_event.c | 41 ++++++++++++++++++++++++++++++++-- drivers/perf/arm_pmu.c | 5 +++++ include/linux/perf/arm_pmu.h | 2 ++ 4 files changed, 48 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index e07e7de9ac49..f81c4621fcac 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -190,6 +190,8 @@ config ARM64 select HAVE_NMI select HAVE_PATA_PLATFORM select HAVE_PERF_EVENTS + select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI + select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && HAVE_PERF_EVENTS_NMI select HAVE_PERF_REGS select HAVE_PERF_USER_STACK_DUMP select HAVE_REGS_AND_STACK_ACCESS_API diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index d07788dad388..b40307fe4214 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -23,6 +23,8 @@ #include #include #include +#include +#include /* ARMv8 Cortex-A53 specific event types. */ #define ARMV8_A53_PERFCTR_PREF_LINEFILL 0xC2 @@ -1284,10 +1286,21 @@ static struct platform_driver armv8_pmu_driver = { static int __init armv8_pmu_driver_init(void) { + int ret; + if (acpi_disabled) - return platform_driver_register(&armv8_pmu_driver); + ret = platform_driver_register(&armv8_pmu_driver); else - return arm_pmu_acpi_probe(armv8_pmuv3_init); + ret = arm_pmu_acpi_probe(armv8_pmuv3_init); + + /* + * Try to re-initialize lockup detector after PMU init in + * case PMU events are triggered via NMIs. + */ + if (ret == 0 && arm_pmu_irq_is_nmi()) + lockup_detector_init(); + + return ret; } device_initcall(armv8_pmu_driver_init) @@ -1345,3 +1358,27 @@ void arch_perf_update_userpage(struct perf_event *event, userpg->cap_user_time_zero = 1; userpg->cap_user_time_short = 1; } + +#ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF +/* + * Safe maximum CPU frequency in case a particular platform doesn't implement + * cpufreq driver. Although, architecture doesn't put any restrictions on + * maximum frequency but 5 GHz seems to be safe maximum given the available + * Arm CPUs in the market which are clocked much less than 5 GHz. On the other + * hand, we can't make it much higher as it would lead to a large hard-lockup + * detection timeout on parts which are running slower (eg. 1GHz on + * Developerbox) and doesn't possess a cpufreq driver. + */ +#define SAFE_MAX_CPU_FREQ 5000000000UL // 5 GHz +u64 hw_nmi_get_sample_period(int watchdog_thresh) +{ + unsigned int cpu = smp_processor_id(); + unsigned long max_cpu_freq; + + max_cpu_freq = cpufreq_get_hw_max_freq(cpu) * 1000UL; + if (!max_cpu_freq) + max_cpu_freq = SAFE_MAX_CPU_FREQ; + + return (u64)max_cpu_freq * watchdog_thresh; +} +#endif diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c index 3cbc3baf087f..2aecb0c34290 100644 --- a/drivers/perf/arm_pmu.c +++ b/drivers/perf/arm_pmu.c @@ -697,6 +697,11 @@ static int armpmu_get_cpu_irq(struct arm_pmu *pmu, int cpu) return per_cpu(hw_events->irq, cpu); } +bool arm_pmu_irq_is_nmi(void) +{ + return has_nmi; +} + /* * PMU hardware loses all context when a CPU goes offline. * When a CPU is hotplugged back in, since some hardware registers are diff --git a/include/linux/perf/arm_pmu.h b/include/linux/perf/arm_pmu.h index 505480217cf1..bf7966776c55 100644 --- a/include/linux/perf/arm_pmu.h +++ b/include/linux/perf/arm_pmu.h @@ -163,6 +163,8 @@ int arm_pmu_acpi_probe(armpmu_init_fn init_fn); static inline int arm_pmu_acpi_probe(armpmu_init_fn init_fn) { return 0; } #endif +bool arm_pmu_irq_is_nmi(void); + /* Internal functions only for core arm_pmu code */ struct arm_pmu *armpmu_alloc(void); struct arm_pmu *armpmu_alloc_atomic(void);