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[209.85.220.41]) by mx.google.com with SMTPS id b8sor1401500plx.38.2021.10.14.00.36.00 for (Google Transport Security); Thu, 14 Oct 2021 00:36:00 -0700 (PDT) Received-SPF: pass (google.com: domain of sumit.garg@linaro.org designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dxQEcu69; spf=pass (google.com: domain of sumit.garg@linaro.org designates 209.85.220.41 as permitted sender) smtp.mailfrom=sumit.garg@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=o/ihjVhEyFVt5hRFiCCjoBklsGrWdBtHp+Qld8OwdOk=; b=dxQEcu69ub0+0DdPx1X1AKnz1TWhDtYV2otRgeQh3aFArKfkopndjFo3uORGCoI7Ir Z2NSXzFR8Ozm2terCCh4YACyWCI5YprvSvx4OloEPLvvSDjf+RHjD9mtZXDj7EMicPGH BRUiVOHMADOrKv7n5U/c/1NwRMj9MeQB+QS0905ltlgR7+k0D9rJvF41B+rT+txj81Gk 7x6Keicjl5Z+tUT0GvZeTMMVHnsWG9Rm5Wm06zevD+szID/h/XehQCktg6rwLMH1bq2S daG9W1KotLEoQSC0b8OaKn3Q2EadQ32q7GglfnswfQ4E/rQa14Psa5lElWp8HvRRLKdo l+DA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=o/ihjVhEyFVt5hRFiCCjoBklsGrWdBtHp+Qld8OwdOk=; b=uYBa62//nQKMVyYoxnejfsbZkS5ALYJnF/W2rGi06fD0q1o/xr5SJ5XDrMXBCqMnKR nuVHKvXroSpHZ7nJjEodSEiE78e1pFGy/Eo1f34P8rAi9JJf+nyaKxpmOIj7iiOp+s9t KvlTriR4OUMNpzNaIDXTHBMK1cqn+1jn3eBL4GQWS5uK8AZqnfyp6uxsE5vB5mcsiv4P 1E58Yr10UU+Ab6xIFHS2PbVuvkQl+sv8iUj8m6qq/nRA9Az8LwwJBRAPBzjiIC1alNDC I2FXL8SkJ0hF8DAlN5CIV+d05Fy4S7FHBFDgtCxY7JxmZfp0zYPkP/jJ9uZ8LqNu5tUl +lMg== X-Gm-Message-State: AOAM532JO+98EpAPAo11b6GLLi1Ei5XnaFD05y8KrdZRnpZ6BRjeLqp9 AQ8hWibvYjN/kihmZ3K+PIz/KBDTn/YpJOX/UfA= X-Google-Smtp-Source: ABdhPJy4Wz0mM2WVxWHG2/tSgwPpolQ5VdvjY9d3lRBmX5uAgq5ROeUwhqFP+DCuy7NzAjbV3GiK1A== X-Received: by 2002:a17:902:6b07:b0:13e:d5ba:3d8f with SMTP id o7-20020a1709026b0700b0013ed5ba3d8fmr3571504plk.32.1634196959637; Thu, 14 Oct 2021 00:35:59 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([223.178.212.208]) by smtp.gmail.com with ESMTPSA id o4sm1530582pfb.48.2021.10.14.00.35.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Oct 2021 00:35:59 -0700 (PDT) From: Sumit Garg To: sumit.garg@linaro.org Cc: patches@linaro.org Subject: [PATCH] arm64: Enable perf events based hard lockup detector Date: Thu, 14 Oct 2021 13:05:51 +0530 Message-Id: <20211014073551.24345-1-sumit.garg@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 With the recent feature added to enable perf events to use pseudo NMIs as interrupts on platforms which support GICv3 or later, its now been possible to enable hard lockup detector (or NMI watchdog) on arm64 platforms. So enable corresponding support. One thing to note here is that normally lockup detector is initialized just after the early initcalls but PMU on arm64 comes up much later as device_initcall(). So we need to re-initialize lockup detection once PMU has been initialized. Signed-off-by: Sumit Garg --- arch/arm64/Kconfig | 2 ++ arch/arm64/kernel/perf_event.c | 41 ++++++++++++++++++++++++++++++++-- drivers/perf/arm_pmu.c | 5 +++++ include/linux/perf/arm_pmu.h | 2 ++ 4 files changed, 48 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index e07e7de9ac49..f81c4621fcac 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -190,6 +190,8 @@ config ARM64 select HAVE_NMI select HAVE_PATA_PLATFORM select HAVE_PERF_EVENTS + select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI + select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && HAVE_PERF_EVENTS_NMI select HAVE_PERF_REGS select HAVE_PERF_USER_STACK_DUMP select HAVE_REGS_AND_STACK_ACCESS_API diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index d07788dad388..b40307fe4214 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -23,6 +23,8 @@ #include #include #include +#include +#include /* ARMv8 Cortex-A53 specific event types. */ #define ARMV8_A53_PERFCTR_PREF_LINEFILL 0xC2 @@ -1284,10 +1286,21 @@ static struct platform_driver armv8_pmu_driver = { static int __init armv8_pmu_driver_init(void) { + int ret; + if (acpi_disabled) - return platform_driver_register(&armv8_pmu_driver); + ret = platform_driver_register(&armv8_pmu_driver); else - return arm_pmu_acpi_probe(armv8_pmuv3_init); + ret = arm_pmu_acpi_probe(armv8_pmuv3_init); + + /* + * Try to re-initialize lockup detector after PMU init in + * case PMU events are triggered via NMIs. + */ + if (ret == 0 && arm_pmu_irq_is_nmi()) + lockup_detector_init(); + + return ret; } device_initcall(armv8_pmu_driver_init) @@ -1345,3 +1358,27 @@ void arch_perf_update_userpage(struct perf_event *event, userpg->cap_user_time_zero = 1; userpg->cap_user_time_short = 1; } + +#ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF +/* + * Safe maximum CPU frequency in case a particular platform doesn't implement + * cpufreq driver. Although, architecture doesn't put any restrictions on + * maximum frequency but 5 GHz seems to be safe maximum given the available + * Arm CPUs in the market which are clocked much less than 5 GHz. On the other + * hand, we can't make it much higher as it would lead to a large hard-lockup + * detection timeout on parts which are running slower (eg. 1GHz on + * Developerbox) and doesn't possess a cpufreq driver. + */ +#define SAFE_MAX_CPU_FREQ 5000000000UL // 5 GHz +u64 hw_nmi_get_sample_period(int watchdog_thresh) +{ + unsigned int cpu = smp_processor_id(); + unsigned long max_cpu_freq; + + max_cpu_freq = cpufreq_get_hw_max_freq(cpu) * 1000UL; + if (!max_cpu_freq) + max_cpu_freq = SAFE_MAX_CPU_FREQ; + + return (u64)max_cpu_freq * watchdog_thresh; +} +#endif diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c index 3cbc3baf087f..2aecb0c34290 100644 --- a/drivers/perf/arm_pmu.c +++ b/drivers/perf/arm_pmu.c @@ -697,6 +697,11 @@ static int armpmu_get_cpu_irq(struct arm_pmu *pmu, int cpu) return per_cpu(hw_events->irq, cpu); } +bool arm_pmu_irq_is_nmi(void) +{ + return has_nmi; +} + /* * PMU hardware loses all context when a CPU goes offline. * When a CPU is hotplugged back in, since some hardware registers are diff --git a/include/linux/perf/arm_pmu.h b/include/linux/perf/arm_pmu.h index 505480217cf1..bf7966776c55 100644 --- a/include/linux/perf/arm_pmu.h +++ b/include/linux/perf/arm_pmu.h @@ -163,6 +163,8 @@ int arm_pmu_acpi_probe(armpmu_init_fn init_fn); static inline int arm_pmu_acpi_probe(armpmu_init_fn init_fn) { return 0; } #endif +bool arm_pmu_irq_is_nmi(void); + /* Internal functions only for core arm_pmu code */ struct arm_pmu *armpmu_alloc(void); struct arm_pmu *armpmu_alloc_atomic(void);