From patchwork Sun Apr 28 23:02:11 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 16494 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ve0-f197.google.com (mail-ve0-f197.google.com [209.85.128.197]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id CB4342395E for ; Sun, 28 Apr 2013 23:03:56 +0000 (UTC) Received: by mail-ve0-f197.google.com with SMTP id 15sf5821092vea.0 for ; Sun, 28 Apr 2013 16:02:55 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:mime-version:x-beenthere:x-received:received-spf :x-received:x-forwarded-to:x-forwarded-for:delivered-to:x-received :received-spf:x-received:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:x-gm-message-state:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-google-group-id:list-post:list-help:list-archive:list-unsubscribe; bh=BlwSdm02shcm2caYBTTZyARHbj2btIq7ZEKLsQixW+U=; b=SizAqNtas7G1GTzTBtFsJT7Zn3oEU8WOtv8xMyRSX1x6mGMOyD37J6UtluguAddhLY PHj3ncpaLE+nJg45rbd+n0fUkb6mGth8oeUUHznPtdCMbKb5q8Gt9J9nySB/GMkziS+h Jf89NrGLj0NM9fdIf4niKK8SRDv0mX8teZO/EmyEAhOnsPZL7cIh+wrqr6QDvzbOJPi3 dmqoF2/hZg1SceQbOQDx7SC+gJN5xrocsnEmmrztdA8HFaf/3e/ndACh68JVKi+Tltob FP7C70QxwgBM78dOx7Tp+o7RufMEZVTr6J/0sWTreooauZL3Wkyb2ViENoxisPRGAzYf rN0Q== X-Received: by 10.224.18.133 with SMTP id w5mr8499311qaa.1.1367190175662; Sun, 28 Apr 2013 16:02:55 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.58.5 with SMTP id m5ls2522193qeq.40.gmail; Sun, 28 Apr 2013 16:02:55 -0700 (PDT) X-Received: by 10.220.57.197 with SMTP id d5mr16858759vch.47.1367190175498; Sun, 28 Apr 2013 16:02:55 -0700 (PDT) Received: from mail-vc0-f175.google.com (mail-vc0-f175.google.com [209.85.220.175]) by mx.google.com with ESMTPS id fe2si8966255vcb.50.2013.04.28.16.02.55 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 28 Apr 2013 16:02:55 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.220.175 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.220.175; Received: by mail-vc0-f175.google.com with SMTP id lf10so4953090vcb.6 for ; Sun, 28 Apr 2013 16:02:55 -0700 (PDT) X-Received: by 10.52.228.71 with SMTP id sg7mr26627723vdc.51.1367190175329; Sun, 28 Apr 2013 16:02:55 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.58.127.98 with SMTP id nf2csp33815veb; Sun, 28 Apr 2013 16:02:54 -0700 (PDT) X-Received: by 10.180.90.203 with SMTP id by11mr14192314wib.10.1367190174216; Sun, 28 Apr 2013 16:02:54 -0700 (PDT) Received: from mail-we0-x234.google.com (mail-we0-x234.google.com [2a00:1450:400c:c03::234]) by mx.google.com with ESMTPS id mv5si3444478wib.84.2013.04.28.16.02.53 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 28 Apr 2013 16:02:54 -0700 (PDT) Received-SPF: neutral (google.com: 2a00:1450:400c:c03::234 is neither permitted nor denied by best guess record for domain of julien.grall@linaro.org) client-ip=2a00:1450:400c:c03::234; Received: by mail-we0-f180.google.com with SMTP id x43so4819180wey.39 for ; Sun, 28 Apr 2013 16:02:53 -0700 (PDT) X-Received: by 10.180.198.49 with SMTP id iz17mr14111317wic.19.1367190173617; Sun, 28 Apr 2013 16:02:53 -0700 (PDT) Received: from belegaer.uk.xensource.com. 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[46.33.159.2]) by mx.google.com with ESMTPSA id k5sm18711393wiy.5.2013.04.28.16.02.52 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 28 Apr 2013 16:02:53 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Cc: ian.campbell@citrix.com, patches@linaro.org, anthony.perard@citrix.com, stefano.stabellini@eu.citrix.com, Julien Grall Subject: [RFC 28/29] xen/arm: Support secondary cpus boot and switch to hypervisor for the exynos5 Date: Mon, 29 Apr 2013 00:02:11 +0100 Message-Id: <0f985c257a955b46c6314885e9eb69dee6c5cf3c.1367188423.git.julien.grall@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: References: X-Gm-Message-State: ALoCoQkPdpBRjp/g6pYRF6mY6mMZnbXL7o/c5OxxO/5WqRh6PegjNmp2Ep2GYEYS4qiyej79BB0x X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.175 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Use machine ID to know what is the current board. This value is only given to the first CPU by the bootloader. When the exynos 5 starts, there is only one CPU up. Xen needs to start the secondary cpu. The latter boots in secure mode. Signed-off-by: Julien Grall --- xen/arch/arm/arm32/head.S | 19 +++++++- xen/arch/arm/arm32/mode_switch.S | 74 ++++++++++++++++++++++-------- xen/include/asm-arm/platforms/vexpress.h | 11 +++++ 3 files changed, 85 insertions(+), 19 deletions(-) diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S index 55781cd..f701bc0 100644 --- a/xen/arch/arm/arm32/head.S +++ b/xen/arch/arm/arm32/head.S @@ -72,7 +72,7 @@ past_zImage: cpsid aif /* Disable all interrupts */ /* Save the bootloader arguments in less-clobberable registers */ - /* No need to save r1 == Unused ARM-linux machine type */ + mov r5, r1 /* r5: ARM-linux machine type */ mov r8, r2 /* r8 := DTB base address */ /* Find out where we are */ @@ -122,6 +122,20 @@ boot_cpu: teq r12, #0 bleq kick_cpus + /* Secondary CPUs doesn't have machine ID + * - Store machine on boot CPU + * - Load machine ID on secondary CPUs */ + ldr r0, =machine_id /* VA of machine_id */ + add r0, r0, r10 /* PA of machine_id */ + teq r12, #0 + streq r5, [r0] /* On boot CPU save machine ID */ + ldrne r5, [r0] /* If non boot cpu r5 := machine ID */ + + PRINT("- Machine ID ") + mov r0, r5 + bl putn + PRINT(" -\r\n") + /* Check that this CPU has Hyp mode */ mrc CP32(r0, ID_PFR1) and r0, r0, #0xf000 /* Bits 12-15 define virt extensions */ @@ -402,6 +416,9 @@ putn: mov pc, lr #endif /* !EARLY_PRINTK */ +/* Place holder for machine ID */ +machine_id: .word 0x0 + /* * Local variables: * mode: ASM diff --git a/xen/arch/arm/arm32/mode_switch.S b/xen/arch/arm/arm32/mode_switch.S index d6741d0..ab40f18 100644 --- a/xen/arch/arm/arm32/mode_switch.S +++ b/xen/arch/arm/arm32/mode_switch.S @@ -20,14 +20,20 @@ #include #include #include +#include #include #include - -/* XXX: Versatile Express specific code */ -/* wake up secondary cpus */ +/* Wake up secondary cpus + * This code relies on Machine ID and only works for Vexpress and the Arndale + * TODO: Move this code either later (via platform specific desc) or in a bootwrapper + * r5: Machine ID + * Clobber r0 r2 */ .globl kick_cpus kick_cpus: + ldr r0, =MACH_TYPE_SMDK5250 + teq r5, r0 /* Are we running on the arndale? */ + beq kick_cpus_arndale /* write start paddr to v2m sysreg FLAGSSET register */ ldr r0, =(V2M_SYS_MMIO_BASE) /* base V2M sysreg MMIO address */ dsb @@ -38,8 +44,20 @@ kick_cpus: add r2, r2, r10 str r2, [r0, #(V2M_SYS_FLAGSSET)] dsb + ldr r2, =V2M_GIC_BASE_ADDRESS /* r2 := VE gic base address */ + b kick_cpus_sgi +kick_cpus_arndale: + /* write start paddr to CPU 1 sysreg register */ + ldr r0, =(S5P_PA_SYSRAM) + ldr r2, =start + add r2, r2, r10 + str r2, [r0] + dsb + ldr r2, =EXYNOS5_GIC_BASE_ADDRESS /* r2 := Exynos5 gic base address */ +kick_cpus_sgi: /* send an interrupt */ - ldr r0, =(GIC_BASE_ADDRESS + GIC_DR_OFFSET) /* base GICD MMIO address */ + ldr r0, =GIC_DR_OFFSET /* GIC distributor offset */ + add r0, r2 /* r0 := r0 + gic base address */ mov r2, #0x1 str r2, [r0, #(GICD_CTLR * 4)] /* enable distributor */ mov r2, #0xfe0000 @@ -51,13 +69,15 @@ kick_cpus: /* Get up a CPU into Hyp mode. Clobbers r0-r3. * - * Expects r12 == CPU number + * r5: Machine ID + * r12: CPU number * - * This code is specific to the VE model, and not intended to be used + * This code is specific to the VE model/Arndale, and not intended to be used * on production systems. As such it's a bit hackier than the main * boot code in head.S. In future it will be replaced by better * integration with the bootloader/firmware so that Xen always starts - * in Hyp mode. */ + * in Hyp mode. + * Clobber r0 - r4 */ .globl enter_hyp_mode enter_hyp_mode: @@ -68,33 +88,51 @@ enter_hyp_mode: orr r0, r0, #0xb1 /* Set SCD, AW, FW and NS */ bic r0, r0, #0xe /* Clear EA, FIQ and IRQ */ mcr CP32(r0, SCR) + + ldr r2, =MACH_TYPE_SMDK5250 /* r4 := Arndale machine ID */ + /* By default load Arndale defaults values */ + ldr r0, =EXYNOS5_TIMER_FREQUENCY /* r0 := timer's frequency */ + ldr r1, =EXYNOS5_GIC_BASE_ADDRESS /* r1 := GIC base address */ + /* If it's not the Arndale machine ID, load VE values */ + teq r5, r2 + ldrne r0, =V2M_TIMER_FREQUENCY + ldrne r1, =V2M_GIC_BASE_ADDRESS + /* Ugly: the system timer's frequency register is only * programmable in Secure state. Since we don't know where its * memory-mapped control registers live, we can't find out the - * right frequency. Use the VE model's default frequency here. */ - ldr r0, =0x5f5e100 /* 100 MHz */ + * right frequency. */ mcr CP32(r0, CNTFRQ) ldr r0, =0x40c00 /* SMP, c11, c10 in non-secure mode */ mcr CP32(r0, NSACR) - mov r0, #GIC_BASE_ADDRESS - add r0, r0, #GIC_DR_OFFSET + + add r0, r1, #GIC_DR_OFFSET /* Disable the GIC distributor, on the boot CPU only */ - mov r1, #0 + mov r4, #0 teq r12, #0 /* Is this the boot CPU? */ - streq r1, [r0] + streq r4, [r0] /* Continuing ugliness: Set up the GIC so NS state owns interrupts, * The first 32 interrupts (SGIs & PPIs) must be configured on all * CPUs while the remainder are SPIs and only need to be done one, on * the boot CPU. */ add r0, r0, #0x80 /* GICD_IGROUP0 */ mov r2, #0xffffffff /* All interrupts to group 1 */ - teq r12, #0 /* Boot CPU? */ str r2, [r0] /* Interrupts 0-31 (SGI & PPI) */ - streq r2, [r0, #4] /* Interrupts 32-63 (SPI) */ - streq r2, [r0, #8] /* Interrupts 64-95 (SPI) */ + teq r12, #0 /* Boot CPU? */ + bne skip_spis /* Don't route SPIs on secondary CPUs */ + + add r4, r1, #GIC_DR_OFFSET + ldr r4, [r4, #4] /* r4 := Interrupt Controller Type Reg */ + and r4, r4, #GICD_TYPE_LINES /* r4 := number of SPIs */ + /* Assume we have minimum 32 SPIs */ +1: + add r0, r0, #4 /* Go to the new group */ + str r2, [r0] /* Update the group */ + subs r4, r4, #1 + bne 1b +skip_spis: /* Disable the GIC CPU interface on all processors */ - mov r0, #GIC_BASE_ADDRESS - add r0, r0, #GIC_CR_OFFSET + add r0, r1, #GIC_CR_OFFSET mov r1, #0 str r1, [r0] /* Must drop priority mask below 0x80 before entering NS state */ diff --git a/xen/include/asm-arm/platforms/vexpress.h b/xen/include/asm-arm/platforms/vexpress.h index 5cf3aba..982a293 100644 --- a/xen/include/asm-arm/platforms/vexpress.h +++ b/xen/include/asm-arm/platforms/vexpress.h @@ -32,6 +32,17 @@ int vexpress_syscfg(int write, int function, int device, uint32_t *data); #endif +/* Constants below is only used in assembly because the DTS is not yet parsed */ +#ifdef __ASSEMBLY__ + +/* GIC base address */ +#define V2M_GIC_BASE_ADDRESS 0x2c000000 + +/* Timer's frequency */ +#define V2M_TIMER_FREQUENCY 0x5f5e100 /* 100 Mhz */ + +#endif /* __ASSEMBLY__ */ + #endif /* __ASM_ARM_PLATFORMS_VEXPRESS_H */ /* * Local variables: