From patchwork Thu Mar 14 22:07:37 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 15361 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id EAF5423E39 for ; Thu, 14 Mar 2013 22:12:50 +0000 (UTC) Received: from mail-ve0-f178.google.com (mail-ve0-f178.google.com [209.85.128.178]) by fiordland.canonical.com (Postfix) with ESMTP id 8ABADA181F8 for ; Thu, 14 Mar 2013 22:12:50 +0000 (UTC) Received: by mail-ve0-f178.google.com with SMTP id db10so2153242veb.9 for ; Thu, 14 Mar 2013 15:12:50 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:x-forwarded-to:x-forwarded-for:delivered-to:x-received :received-spf:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:x-provags-id:x-gm-message-state; bh=etS/1oX1IupLkIHtKTeGqLdA5txub1292SwObhOytO0=; b=fPbdCPYPuGnEcrkinqTMZY76fKDzw3imKeTMbPtJ+cN9M1EbV3T7xIkVkTdx1rKxh9 58ZCyrJjr4qhnWGbVReeXhQTOSrPJOkrPyxbruVL87GpgouTcRS0Xr1K88eflgyG0eUj jNZBpspDsRLRFU5K3xhioMzNNbIxZyCUnURUt7nJ6nosZlCAvUWwqRR8HV1sNSdUETR6 RnAKnNGd8hsCNYGmTmcdL8CcfJvAL7FWrrFKcU2Ov8qHgQ0/gy2tCFxSrstu9cE3HTj0 1YRPgygO8nLTt5SMDgjWcVbqWzSkqfCEW+kG6vIVjz5smvcfXP3hYG7RT1g17w7GMSKl RpSw== X-Received: by 10.58.205.179 with SMTP id lh19mr4104087vec.7.1363299170013; Thu, 14 Mar 2013 15:12:50 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.58.127.98 with SMTP id nf2csp93840veb; Thu, 14 Mar 2013 15:12:49 -0700 (PDT) X-Received: by 10.14.207.200 with SMTP id n48mr11445885eeo.4.1363299168929; Thu, 14 Mar 2013 15:12:48 -0700 (PDT) Received: from moutng.kundenserver.de (moutng.kundenserver.de. [212.227.126.187]) by mx.google.com with ESMTPS id t8si7392275eeg.180.2013.03.14.15.12.48 (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 14 Mar 2013 15:12:48 -0700 (PDT) Received-SPF: neutral (google.com: 212.227.126.187 is neither permitted nor denied by best guess record for domain of arnd@arndb.de) client-ip=212.227.126.187; Authentication-Results: mx.google.com; spf=neutral (google.com: 212.227.126.187 is neither permitted nor denied by best guess record for domain of arnd@arndb.de) smtp.mail=arnd@arndb.de Received: from wuerfel.lan (HSI-KBW-46-223-90-92.hsi.kabel-badenwuerttemberg.de [46.223.90.92]) by mrelayeu.kundenserver.de (node=mrbap2) with ESMTP (Nemesis) id 0MXWgY-1UCOhl16Yg-00Wld6; Thu, 14 Mar 2013 23:07:43 +0100 From: Arnd Bergmann To: Anton Vorontsov Cc: linux-arm-kernel@vger.kernel.org, patches@linaro.org, Olof Johansson , Florian Fainelli , Imre Kaloz , Arnd Bergmann Subject: [PATCH 5/5] ARM: cns3xxx: initial DT support Date: Thu, 14 Mar 2013 23:07:37 +0100 Message-Id: <1363298857-8131-6-git-send-email-arnd@arndb.de> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1363298857-8131-1-git-send-email-arnd@arndb.de> References: <1363298857-8131-1-git-send-email-arnd@arndb.de> X-Provags-ID: V02:K0:um4pXZqu+tV6AJJRlXnltHghR4h4Pugp7kqJ39MwM1n O6tpR/A9J5BnXsNDvS7mcfNJHpL/X5UXn2HgGgbn7eWvO6B5Pe UIlseuwycGOgQQpg5gSBuHB8lqbqDEaeuwIbnXT6AqTAcgZaTa 6Wma6DM16KzuF6As72XJPSY//nCTkubi1zsGQro1LyzfTu/GBp oXRQ06i3OPZW3M15Y3ZxG2pir6F7pn7QCXDFyDniwpYg3HNuGT MWzW1FPd0xlkO5FeFf/DqIGJCVy2rg4NCeBgVqWBxC8ljGiHM3 e/GzviztKsc5F5G8IjHbaf/yhPIHpsYqFhJzyk1pzwSDMrev8n M28SMw5Thfy9zxkvx+64s5ftRy+4M12Y/HXFVHyA6 X-Gm-Message-State: ALoCoQktfVmBz5fj2LmwFUZ4JJFQ+WHjnZlesI4lrug/gyuUr5st+RcY57DnKGtHmqN23BTeVorh This adds very minimal support for booting cns3xxx using a device tree. It should support the same devices that cns3420vb provides but gets them from the DT. All devices that don't have their own binding are probed through auxdata. This is completely untested and likely incomplete. Booting through ATAGS is made optional, so it can be turned off by anybody who has a DTB file. Signed-off-by: Arnd Bergmann --- arch/arm/mach-cns3xxx/Kconfig | 1 + arch/arm/mach-cns3xxx/Makefile | 8 +-- arch/arm/mach-cns3xxx/core.c | 119 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 125 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-cns3xxx/Kconfig b/arch/arm/mach-cns3xxx/Kconfig index 5720f3d..dbf0df8 100644 --- a/arch/arm/mach-cns3xxx/Kconfig +++ b/arch/arm/mach-cns3xxx/Kconfig @@ -14,6 +14,7 @@ menu "CNS3XXX platform type" config MACH_CNS3420VB bool "Support for CNS3420 Validation Board" + depends on ATAGS help Include support for the Cavium Networks CNS3420 MPCore Platform Baseboard. diff --git a/arch/arm/mach-cns3xxx/Makefile b/arch/arm/mach-cns3xxx/Makefile index 11033f1..a1ff108 100644 --- a/arch/arm/mach-cns3xxx/Makefile +++ b/arch/arm/mach-cns3xxx/Makefile @@ -1,3 +1,5 @@ -obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm.o devices.o -obj-$(CONFIG_PCI) += pcie.o -obj-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o +obj-$(CONFIG_ARCH_CNS3XXX) += cns3xxx.o +cns3xxx-y += core.o pm.o +cns3xxx-$(CONFIG_ATAGS) += devices.o +cns3xxx-$(CONFIG_PCI) += pcie.o +cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c index 012ffdb..49e657c 100644 --- a/arch/arm/mach-cns3xxx/core.c +++ b/arch/arm/mach-cns3xxx/core.c @@ -13,12 +13,18 @@ #include #include #include +#include +#include +#include +#include +#include #include #include #include #include #include "cns3xxx.h" #include "core.h" +#include "pm.h" static struct map_desc cns3xxx_io_desc[] __initdata = { { @@ -276,3 +282,116 @@ void __init cns3xxx_l2x0_init(void) } #endif /* CONFIG_CACHE_L2X0 */ + +static int csn3xxx_usb_power_on(struct platform_device *pdev) +{ + /* + * EHCI and OHCI share the same clock and power, + * resetting twice would cause the 1st controller been reset. + * Therefore only do power up at the first up device, and + * power down at the last down device. + * + * Set USB AHB INCR length to 16 + */ + if (atomic_inc_return(&usb_pwr_ref) == 1) { + cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB); + cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST); + cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST); + __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)), + MISC_CHIP_CONFIG_REG); + } + + return 0; +} + +static void csn3xxx_usb_power_off(struct platform_device *pdev) +{ + /* + * EHCI and OHCI share the same clock and power, + * resetting twice would cause the 1st controller been reset. + * Therefore only do power up at the first up device, and + * power down at the last down device. + */ + if (atomic_dec_return(&usb_pwr_ref) == 0) + cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST); +} + +static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = { + .power_on = csn3xxx_usb_power_on, + .power_off = csn3xxx_usb_power_off, +}; + +static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = { + .num_ports = 1, + .power_on = csn3xxx_usb_power_on, + .power_off = csn3xxx_usb_power_off, +}; + +static struct of_dev_auxdata cns3xxx_auxdata[] __initconst = { + { "intel,usb-ehci", CNS3XXX_USB_BASE, "ehci-platform", &cns3xxx_usb_ehci_pdata }, + { "intel,usb-ohci", CNS3XXX_USB_OHCI_BASE, "ohci-platform", &cns3xxx_usb_ohci_pdata }, + { "cavium,cns3420-ahci", CNS3XXX_SATA2_BASE, "ahci", NULL }, + { "cavium,cns3420-sdhci", CNS3XXX_SDIO_BASE, "ahci", NULL }, + {}, +}; + +static void __init cns3xxx_init(void) +{ + struct device_node *dn; + + cns3xxx_l2x0_init(); + + dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-ahci"); + if (of_device_is_available(dn)) { + u32 tmp; + + tmp = __raw_readl(MISC_SATA_POWER_MODE); + tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */ + tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */ + __raw_writel(tmp, MISC_SATA_POWER_MODE); + + /* Enable SATA PHY */ + cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0); + cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1); + + /* Enable SATA Clock */ + cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA); + + /* De-Asscer SATA Reset */ + cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA)); + } + + dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-sdhci"); + if (of_device_is_available(dn)) { + u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014); + u32 gpioa_pins = __raw_readl(gpioa); + + /* MMC/SD pins share with GPIOA */ + gpioa_pins |= 0x1fff0004; + __raw_writel(gpioa_pins, gpioa); + + cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO)); + cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO)); + } + + pm_power_off = cns3xxx_power_off; + + of_platform_populate(NULL, of_default_bus_match_table, + cns3xxx_auxdata, NULL); +} + +static const char *cns3xxx_dt_compat[] __initdata = { + "cavium,cns3410", + "cavium,cns3420", + NULL, +}; + +DT_MACHINE_START(CNS3XXX_DT, "Cavium Networks CNS3xxx") + .dt_compat = cns3xxx_dt_compat, + .nr_irqs = NR_IRQS_CNS3XXX, + .map_io = cns3xxx_map_io, + .init_irq = cns3xxx_init_irq, + .init_time = cns3xxx_timer_init, + .init_machine = cns3xxx_init, + .restart = cns3xxx_restart, +MACHINE_END